Patent application number | Description | Published |
20130185826 | MATERIALS, SYSTEMS, ORGANISMS, AND METHODS FOR ENHANCING ABIOTIC STRESS TOLERANCE, INCREASING BIOMASS, AND/OR ALTERING LIGNIN COMPOSITION - The present disclosure relates, in some embodiments, to materials, systems, organisms, and methods for enhancing abiotic stress tolerance (e.g., cold, salinity, drought, wind), increasing biomass, and/or altering lignin composition in plants. For example, enhancing abiotic stress tolerance may be achieved using a plant-specific family of transcription factors is APETALA2 (AP2), that includes c-repeat binding factor (e.g., CBF1, CBF3) and AP37 nucleic acids and/or polypeptides. In some embodiments, increasing biomass may be achieved by altering expression of gibberellin oxidases (e.g., GA3ox3/GA2ox4) nucleic acids and/or polypeptides. Altering lignin composition may be achieved by suppression of stem-thickening in pith (e.g., STP1) nucleic acids and/or polypeptides. | 07-18-2013 |
20140283202 | COMPOSITIONS, ORGANISMS, SYSTEMS, AND METHODS FOR ALTERING COLD, DROUGHT, AND SALT TOLERANCE IN PLANTS - The present disclosure relates, in some embodiments, to materials, systems, organisms, and methods for enhancing abiotic stress tolerance (e.g., cold, salinity, drought, heat, wind) and/or enhancing biomass in plants. For example, enhancing abiotic stress tolerance may be achieved in plants having | 09-18-2014 |
Patent application number | Description | Published |
20100296566 | METHOD AND APPARATUS FOR DETERMINING A CALIBRATION SIGNAL - Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system. | 11-25-2010 |
20110033007 | MULTI-BAND, MULTI-DROP CHIP TO CHIP SIGNALING - A system comprising: a first integrated circuit device having a multi-band transmission circuit; second and third integrated circuit devices having respective multi-band reception circuits; and a signaling link including a first stub coupled to the multi-band transmission circuit to receive a multi-band signal therefrom, second and third stubs coupled to the multi-band reception circuits of the second and third integrated circuit devices, respectively, to deliver the multi-band signal thereto, and a plurality of channel segments that extend between the first, second and third stubs to convey the multi-band transmission signal therebetween, and wherein at least one of a physical length, impedance or propagation constant of at least one of the first stub, second stub, third stub or channel segment of the plurality of channel segments is selected to spectrally position a frequency-interval exhibiting attenuated frequency response on the signaling link such that multiple passbands separated by the frequency-interval are established to enable conveyance of the multi-band transmission signal on the signaling link. | 02-10-2011 |
20120306568 | REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTS - Embodiments reduce crosstalk between multiple interconnects in a printed circuit board environment. Further, embodiments perform frequency-dependent modal decomposition of characteristics of two or more interconnects spanning one or more integrated circuits on an interconnect substrate. In addition, each interconnect includes one or more cascaded coupled traces, where the cascaded coupled traces have one or more discontinuities in a heterogeneous medium. | 12-06-2012 |
20130051162 | CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION - Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links. | 02-28-2013 |
20130114363 | MULTI-MODAL MEMORY INTERFACE - A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques. | 05-09-2013 |
20150108656 | STACKED DIE PACKAGE - Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack. | 04-23-2015 |