| Patent application number | Description | Published |
|---|
| 20120025507 | MOBILE UNIT FOR ROAD-SIDE ACTIVITIES - A scaffold includes a central platform with a top surface defining a central area, a bottom, a first lateral side, a second lateral side, and a front side. The scaffold also includes a plurality of supports connected to and supporting the platform and at least one extendible platform connected adjacent to the central platform. The extendible platform has a top surface defining an extendible area. The extendible platform is adjustable between an opened position and a closed position, the opened position presenting the extendible area for use, the closed position stowing the extendible area from use. A vehicle incorporating the scaffold, and methods of use of the same, also are provided. | 02-02-2012 |
| 20140021708 | MOBILE UNIT FOR ROAD-SIDE ACTIVITIES - A scaffold includes a central platform with a top surface defining a central area, a bottom, a first lateral side, a second lateral side, and a front side. The scaffold also includes a plurality of supports connected to and supporting the platform and at least one extendible platform connected adjacent to the central platform. The extendible platform has a top surface defining an extendible area. The extendible platform is adjustable between an opened position and a closed position, the opened position presenting the extendible area for use, the closed position stowing the extendible area from use. A vehicle incorporating the scaffold, and methods of use of the same, also are provided. | 01-23-2014 |
| Patent application number | Description | Published |
|---|
| 20100217406 | UNIVERSAL REMOTE MACHINERY CONTROLLER AND MONITOR - A system is provided herein for remotely controlling and monitoring machinery, the machinery having a control network for control thereof, one or more switches coupled to the control network for controlling the machinery via the control network. The system includes a controller hardwired coupled to the control network of the machinery. The controller is configured to control the machinery via the control network separately from the switches, and the controller is configured to monitor operation of the machinery. In addition, the system includes an arrangement for receiving signals for controlling the controller from a remote location and an arrangement for transmitting, to a remote location, information collected by the controller resulting from the controller monitoring operation of the machinery. Advantageously, with the subject invention, the system can control and monitor machinery from remote locations directly. In the event of faults or failures, corrective action may be taken using the subject invention. | 08-26-2010 |
| 20140163699 | UNIVERSAL REMOTE MACHINERY MONITOR - A system is provided herein for remotely monitoring machinery, the machinery having a control network for control thereof, one or more switches coupled to the control network for controlling the machinery via the control network. The system includes a controller hardwired coupled to the control network of the machinery. The controller is configured to monitor operation of the machinery. In addition, the system includes an arrangement for receiving signals for controlling the controller from a remote location and an arrangement for transmitting, to a remote location, information collected by the controller resulting from the controller monitoring operation of the machinery. Advantageously, with the subject invention, the system can monitor machinery from remote locations directly. In the event of faults or failures, corrective action may be taken using the subject invention. | 06-12-2014 |
| Patent application number | Description | Published |
|---|
| 20080312863 | SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER - A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor. | 12-18-2008 |
| 20100161921 | FLASH ROM PROGRAMMING - A method comprises providing a golden ROM unit comprising known good ROM code. The golden ROM is coupled to a ROM socket of a target system. The target system is booted, wherein booting comprises providing power to the target system and independently providing power to the ROM socket. The known good ROM code is loaded from the golden ROM to a system memory of the target system. Power is removed from the ROM socket and the golden ROM is decoupled from the ROM socket. A first subject ROM is coupled to the ROM socket. Power is provided to the ROM socket and the first subject ROM is programmed with the known good ROM code. | 06-24-2010 |
| 20100250943 | METHOD FOR SECURITY IN ELECTRONICALLY FUSED ENCRYPTION KEYS - A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made. | 09-30-2010 |
| 20130103354 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 04-25-2013 |
| 20130103927 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 04-25-2013 |
| 20130318364 | PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRITICAL PATH MONITORING - An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided. | 11-28-2013 |
| 20140059327 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 02-27-2014 |
| 20140082335 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 03-20-2014 |
| 20140143596 | PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRICTICAL PATH MONITORING - An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided. | 05-22-2014 |
| 20140237302 | CHARACTERIZATION AND FUNCTIONAL TEST IN A PROCESSOR OR SYSTEM UTILIZING CRITICAL PATH MONITOR TO DYNAMICALLY MANAGE OPERATIONAL TIMING MARGIN - Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller. | 08-21-2014 |
| 20140379288 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 12-25-2014 |
| 20150057975 | FREQUENCY GUARD BAND VALIDATION OF PROCESSORS - It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency. | 02-26-2015 |
