Patent application number | Description | Published |
20110101423 | JUNCTION FIELD EFFECT TRANSISTOR - A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced. | 05-05-2011 |
20110101424 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 05-05-2011 |
20110101444 | ELECTROSTATIC PROTECTION DEVICE - An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device. | 05-05-2011 |
20110101486 | BIPOLAR TRANSISTOR - A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation. | 05-05-2011 |
20110101500 | JUNCTION FIELD EFFECT TRANSISTOR - A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor. | 05-05-2011 |
20120028432 | METHODS OF FORMING A BIPOLAR TRANSISTOR - A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor. | 02-02-2012 |
20120112307 | BIPOLAR TRANSISTOR WITH GUARD REGION - A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation. | 05-10-2012 |
20120217551 | JUNCTION FIELD EFFECT TRANSISTOR WITH REGION OF REDUCED DOPING - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 08-30-2012 |
20130241021 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTING VIA; AN INTEGRATED CIRCUIT INCLUDING A SENSOR, SUCH AS A PHOTOSENSITIVE DEVICE, AND A METHOD OF MAKING SAID INTEGRATED CIRCUIT - An integrated circuit having an insulated conductor or within a semiconductor substrate and extending perpendicular to a plane of a semiconductor wafer or substrate on which the integrated circuit is fabricated, the conductor comprising a first region of doped semiconductor extending between a first device or a first contact and a second device or a second contact. | 09-19-2013 |
20140097081 | METHODS OF FORMING A THIN FILM RESISTOR - Methods of forming a thin film are disclosed. One such method can include sputtering a target material to form a first thin film resistor and adjusting a parameter of deposition to modulate a property of a subsequently formed second thin film resistor. For instance, a substrate bias and/or a substrate temperature can be adjusted to modulate a property of the second thin film resistor. A temperature coefficient of resistance (TCR) and/or another property of the second thin film resistor can be modulated by adjusting the parameter of deposition. The target material sputtered onto the substrate can include, for example, a Cr alloy, a Ni alloy, SiCr, NiCr, or the like. A relationship can be established between the substrate bias and/or substrate temperature and the thin film resistor property, and the relationship can be used in selecting deposition conditions for a desired property value. | 04-10-2014 |