Patent application number | Description | Published |
20150046673 | VECTOR PROCESSOR - A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed. | 02-12-2015 |
20150046674 | LOW POWER COMPUTATIONAL IMAGING - The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices. | 02-12-2015 |
20150046675 | APPARATUS, SYSTEMS, AND METHODS FOR LOW POWER COMPUTATIONAL IMAGING - The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices. | 02-12-2015 |
20150046678 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING CONFIGURABLE COMPUTATIONAL IMAGING PIPELINE - The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect. | 02-12-2015 |
Patent application number | Description | Published |
20140348431 | CORNER DETECTION - The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing. | 11-27-2014 |
20150046677 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING COMPUTATIONAL IMAGING PIPELINE - The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect. | 02-12-2015 |
20150138405 | APPARATUS, SYSTEMS, AND METHODS FOR REMOVING NOISE FROM AN IMAGE - The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function. | 05-21-2015 |
Patent application number | Description | Published |
20090060207 | METHOD AND SYSTEM FOR SOUND SOURCE SEPARATION - The present invention relates generally to the field of audio engineering and more particularly to methods of Sound Source Separation, where individual sources are extracted from a multiple source recording. More specifically, the present invention is directed at a method of analysis of stereo recordings to facilitate the separation of individual musical sound sources from stereo music recordings. In particular, the method provides for A method of modifying a stereo recording for subsequent analysis, the stereo recording comprising a first channel signal and a second channel signal, the method comprising the steps of: converting the first channel signal into the frequency domain, converting the second channel signal into the frequency domain, defining a set of scaling factors, producing a frequency azimuth plane by 1) gain scaling the frequency converted first channel by a first scaling factor selected from the set of defined scaling factors, 2) subtracting the gain scaled first signal from the second signal, and 3) repeating steps 1) and 2) individually for the remaining scaling factors in the defined set to produce the frequency azimuth plane which represents magnitudes of different frequencies for each of the scaling factors and which may be used for subsequent analysis. | 03-05-2009 |
20120230501 | AUDITORY TEST AND COMPENSATION METHOD - The present invention provides an auditory test and compensation method for an audio system comprising an audio device coupled to an audio output means and a listener of the audio device. The method comprises the steps of: delivering a series of audio stimuli through the audio output means; capturing a listener's response to the audibility of the stimuli; calculating a compensation print from the frequency response; deriving a filter from the calculated compensation print with respect to the frequencies associated with the frequency response and applying the filter to an audio signal of the audio system. | 09-13-2012 |
20160005437 | METHOD AND SYSTEM FOR MATCHING AUDIO AND VIDEO - The present application relates to the field of media processing and more particularly to audio and video processing. The present application addresses the problem that videos collected by fans at concerts and other events generally have poor sound quality and provides a solution that matches a high quality sound to the video. | 01-07-2016 |
Patent application number | Description | Published |
20100028401 | STEM CELL SOURCE FOR PROMOTING NEOVASCULARISATION - The Eph (erythropoietin-producing hepatocellular carcinoma) receptors and their cell surface anchored ligands, the Ephrins, comprise the largest of the receptor tyrosine kinases families with 14 receptors and 8 ligands. The receptors are subdivided into Eph-A and Eph-B categories and have known actions in the development of the vascular and nervous system. The present invention relates to an isolated mesenchymal stem cell selected from the group consisting of an isolated mesenchymal stem cell that expresses Ephrin-B2, an isolated mesenchymal stem cell that over-expresses Ephrin-B2, and an isolated mesenchymal stem cell that is genetically modified to increase Ephrin-B2 expression. The invention further relates to the various applications of the isolated mesenchymal stem cells of the present invention. | 02-04-2010 |
20100062038 | Markers, Antibodies and Recombinant scFvs for Mesenchymal Stem Cell Sub-populations and Osteoclasts - Abstract Markers, antibodies and recombinant scFvs for Mesenchymal Stem Cell sub-populations and osteoclasts. The present invention relates to specific epitopes of surface membrane bound glycoproteins expressed by mesenchymal stem cells and pre-osteoclasts and relates to antibodies such as monoclonal antibodies and recombinant scFv or fragments thereof, raised to the particular epitope and their use in identifying, isolating, and characterization of mesenchymal stem cell sub-populations such as that termed “Stromal Progenitor Cells” (SPCs) in bone marrow and identifying, isolating, and characterization of pre-osteoclasts in peripheral blood. By binding to a specific epitope on the cell surface, limbin/EVC-2 detection and separation by conventional cell sorting methodologies are facilitated. | 03-11-2010 |
20100150877 | Osteopontin for the Prediction and Treatment of Cardiovascular Diseases - Osteopontin for the prediction and treatment of cardiovascular diseases The present invention relates to the use of endothelial progenitor cells (EPCs) and osteopontin for the treatment of cardiovascular diseases or complications. The invention also relates to the use of EPC osteopontin levels as a marker of the risk of the development of these cardiovascular complications. In particular, the invention provides compositions and methods based on osteopontin and the genes encoding osteopontin. | 06-17-2010 |
Patent application number | Description | Published |
20130209184 | CUTTER ELEMENTS, ROTARY MACHINE TOOLS COMPRISING SAME AND METHOD FOR MAKING SAME - A cutter element ( | 08-15-2013 |
20140026716 | METHOD OF MAKING A BIT FOR A ROTARY DRILL - A method of manufacturing a bit for a rotary drill, the bit including a drill tip ( | 01-30-2014 |
20140037393 | BIT FOR A ROTARY DRILL - A bit for a rotary drill, the bit including a cylindrical body having at least two flutes provided therein, the cylindrical body terminating in a cutting end; and a cylindrical land defined by a peripheral face of the cylindrical body between adjacent flutes, the cylindrical land including a margin that is radially elevated relative to a remainder of the cylindrical land; the margin having a width that varies along the length of the cylindrical land. | 02-06-2014 |
20140186132 | TWIST DRILL TIPS, PRECURSOR CONSTRUCTIONS FOR USE IN MAKING SAME, AND METHODS FOR MAKING AND USING SAME - A tip for twist drill, comprising a super-hard structure joined to a substrate at an interface boundary coterminous with an end of the substrate, the super-hard structure comprising sintered polycrystalline material comprising super-hard grains, the super-hard structure defining a super-hard end surface opposite the interface boundary and a plurality of cutting edges configured for boring into a body in use; the super-hard end surface including a centre point or chisel edge, and comprising a plurality of surface regions configured such that respective planes tangential to each of the surface regions are disposed at substantially different angles from the axis of rotation of the tip in use. Precursor constructions for use in manufacturing the tips as well as methods for making the precursor constructions and the tips are disclosed. | 07-03-2014 |
20140239051 | CUTTER STRUCTURES, INSERTS COMPRISING SAME AND METHOD FOR MAKING SAME - A method of making a cutter structure comprising super-hard material defining a rake face topology is provided. The method includes providing a pre-sinter assembly comprising a substrate body having a formation surface defining a topology complementary to the rake face topology, and an aggregation comprising a plurality of super-hard grains, the aggregation disposed adjacent the formation surface of the substrate body, the substrate body comprising a source of catalyst or binder material capable of promoting the sintering of the super-hard grains at a pressure and temperature at which the super-hard material is thermodynamically stable; subjecting the pre-sinter assembly to the pressure and temperature to provide a sintered polycrystalline super-hard structure joined to the formation surface of the substrate body at a first major boundary of the super-hard structure and having a second major boundary surface opposite the formation surface; removing the substrate body to expose the first major boundary of the super-hard structure defining the rake face topology. Cutter inserts and machine tools are also provided. | 08-28-2014 |
20150097321 | METHOD FOR MAKING SUPER-HARD CONSTRUCTIONS - A method of making a construction comprising a polycrystalline super-hard structure joined to a side surface of an elongate substrate. The method includes: providing a vessel configured for an ultra-high pressure, high temperature furnace, the vessel having an elongate cavity for containing a pre-sinter assembly and defining a longitudinal axis, the cavity having opposite ends connected by a cavity wall. The pre-sinter assembly comprises the substrate, an aggregation comprising a plurality of super-hard grains arranged over at least a part of the side surface of the substrate, and a spacer structure configured for spacing the substrate apart from the cavity wall. The spacer structure comprises material having a Young's modulus of at least 300 GPa. The method further includes inserting the pre-sinter assembly into the cavity, the substrate being substantially longitudinally aligned and the spacer structure arranged between the side surface of the substrate and the cavity wall; applying a force to the pre-sinter assembly and heating it to a temperature, the force being sufficient to generate a pressure within the vessel for sintering the aggregation at the temperature, and providing the construction. | 04-09-2015 |
Patent application number | Description | Published |
20110148672 | TRANSITIONING DIGITAL DATA PROCESSORS BETWEEN POWER SAVINGS AND NON-POWER SAVINGS MODES - A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes. | 06-23-2011 |
20110150215 | FAST SWITCHING BETWEEN DIGITAL VIDEO SOURCES - A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes. | 06-23-2011 |
20110150216 | SELECTIVE SWITCHING BETWEEN DATA SOURCES - A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes. | 06-23-2011 |
Patent application number | Description | Published |
20120156714 | INTEGRATED CYTOMETRIC SENSOR SYSTEM AND METHOD - The invention provides a flow cytometric system comprising a first sensor positioned axially to a light source; a channel comprising means for receiving a sample target and interposed between said first sensor and light source; and a second sensor placed at an angle to said first sensor adapted to sense side scattering and/or fluorescent components and said first sensor is adapted to sense a forward scattering component in response to light illuminating the sample target in said channel. In another embodiment the invention provides for a wide dynamic range sensor comprising a plurality of photodiode pixels; wherein at least one or more of said photodiode pixels are voltage biased in one or more of the following modes: photon counting, normal, linear avalanche or Geiger modes, for wide dynamic sensor range operation. By altering the reverse bias voltage, thus putting each photodiode into one of normal, avalanche or Geiger mode, the dynamic range of incident scattering and fluorescent power to which the filter cell array is sensitive to is greatly increased, thus increasing the operational sensitivity and specificity of the cytometric instrument. | 06-21-2012 |
20140374622 | System and Method for High Resolution, Instantaneous Wide Dynamic Range, Multi-Colour Luminescence Detection of Biological Samples in a Microfluidic System - The invention provides a high resolution, wide dynamic range, multi-colour detection platform for microfluidic analysers/instruments and methods. The detection platform uses multiple high gain semiconductor optical sensors for the detection of luminescence from cellular or biological samples. The digitized outputs from these sensors are combined and weighted in a signal processing unit, using pre-determined algorithms for each colour, which optimise the resolution in each of these high gain semiconductor optical sensors while extending the dynamic range of the detection platform. | 12-25-2014 |
Patent application number | Description | Published |
20120063476 | OPTICAL WAVELENGTH COMB GENERATOR DEVICE - The present application relates to comb frequency generator devices generally and more particularly to the use of comb generators for use in fibre optic communications. More particularly, the application provides a frequency comb generator device. The device comprises a laser ( | 03-15-2012 |
20120294320 | TUNABLE LASER SYSTEM AND METHOD - According to the invention there is provided a tunable laser system for use in an optical communication system, said tunable laser system comprising a multi-section laser separated by at least two slots to define a plurality of sections, each section adapted to provide an optical gain. Each section comprises a separate control means to provide an adjustable optical gain in each section. The tunable laser system and method of the present invention provides a wide tuning range, narrow linewidth and fast switching times. | 11-22-2012 |
20130101290 | METHOD AND APPARATUS TO OVERCOME LINEWIDTH PROBLEMS IN FAST RECONFIGURABLE NETWORKS - In wavelength switching optical networks, the optical data being transmitted may be routed to different end points by switching the operating frequency of the laser. However, the phase noise of the laser source increases following a switching event. This increased phase noise can prevent the successful transmission of phase modulation formats which are sensitive to it. Accordingly, it is generally necessary to wait a short period before transmitting data. However, the period may be as long as the data packet being transmitted (e.g. 3 μS), which is a limiting factor. The present application obviates this problem by including a radio frequency pilot tone with the data prior to modulation onto the optical carrier. | 04-25-2013 |
20130302027 | OPTICAL MEASUREMENT METHOD AND SYSTEM - The present application is directed to the measurement of the intensity and phase of high speed optical signals. The present application uses a tunable optical local oscillator, an optical coupler, a photodiode and RF electronics. The tunable laser enables successive measurements to be taken across the optical spectrum allowing the system to measure extremely high bandwidth signals. The signal generated by the local oscillator comprises a component at a frequency between two adjacent modes of the periodic optical signal to be measured. The local oscillator and said periodic signal are optically mixed and sent to a photodiode, the measurement of the phase being based on isolating the resulting beat frequencies. This approach offers a significant improvement over existing time resolved approaches which are limited to the bandwidth of the photodiode (˜50 GHz). | 11-14-2013 |
Patent application number | Description | Published |
20080215822 | PCI Express Enhancements and Extensions - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-04-2008 |
20090083743 | System method and apparatus for binding device threads to device functions - A system apparatus and method for supporting one or more functions in an IO virtualization environment. One or more threads are dynamically associated with, and executing on behalf of, one or more functions in a device. | 03-26-2009 |
20110072164 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 03-24-2011 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-30-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110208925 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 08-25-2011 |
20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
20120036293 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 02-09-2012 |
20120089750 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-12-2012 |
20120254563 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 10-04-2012 |
Patent application number | Description | Published |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132636 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132683 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20150149683 | PCI EXPRESS TRANSACTION DESCRIPTOR - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-28-2015 |
20150161050 | PCI EXPRESS PREFETCHING - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-11-2015 |
Patent application number | Description | Published |
20110212445 | SWI5 GENE AS A DIAGNOSTIC TARGET FOR THE IDENTIFICATION OF FUNGAL AND YEAST SPECIES - The invention relates to the SWI5 gene, the corresponding RNA, specific probes, primers and oligonucleotides related thereto and their use in diagnostic assays to detect and/or discriminate between fungal and yeast species. | 09-01-2011 |
20110217703 | P2/P2A/P2B GENE SEQUENCES AS DIAGNOSTIC TARGETS FOR THE IDENTIFICATION OF FUNGAL AND YEAST SPECIES - The present invention relates to nucleic acid primers and probes to detect one or more fungal and yeast species. More specifically the invention relates to the P2, P2A and P2B gene sequences (also known as 60S acidic ribosomal protein P2, RLA-2-ASPFU, Allergen ASP f8 or Afp2), the corresponding RNA, specific probes, primers and oligonucleotides related thereto and their use in diagnostic assays to detect and/or discriminate fungal and yeast species. | 09-08-2011 |
20110217704 | LEPA/GUF1 GENE SEQUENCES AS A DIAGNOSTIC TARGET FOR THE IDENTIFICATION OF BACTERIAL SPECIES - The current invention relates to a diagnostic kit for a bacterial species and/or fungal and/or yeast species comprising at least one oligonucleotide probe capable of binding to at least a portion of the LepA and/or Guf1 genes or its corresponding mRNA. | 09-08-2011 |
20110218335 | EIF2GAMMA GENE AS A DIAGNOSTIC TARGET FOR THE IDENTIFICATION OF FUNGAL AND YEAST SPECIES - The current invention relates to a diagnostic kit for a yeast or fungal species comprising at least one oligonucleotide probe capable of binding to at least a portion of the eIF2y gene or its corresponding mRNA. | 09-08-2011 |
20120094283 | ACE2 AS A TARGET GENE FOR THE MOLECULAR IDENTIFICATION OF YEAST AND FUNGAL SPECIES - The present invention relates to nucleic acid primers and probes for use in the identification of one or more yeast species. More specifically the invention relates to the Ace2 gene, the corresponding RNA, specific probes, primers and oligonucleotides related thereto and their use in diagnostic assays to detect and/or discriminate between yeast species. | 04-19-2012 |