Patent application number | Description | Published |
20080237710 | Localized spacer for a multi-gate transistor - In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed. | 10-02-2008 |
20090017589 | TRI-GATE INTEGRATION WITH EMBEDDED FLOATING BODY MEMORY CELL USING A HIGH-K DUAL METAL GATE - Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed. | 01-15-2009 |
20090146208 | Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used. | 06-11-2009 |
20090170279 | METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES - A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate ( | 07-02-2009 |
20090267153 | Localized Spacer For A Multi-Gate Transistor - In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed. | 10-29-2009 |
20100072533 | ASYMMETRIC CHANNEL DOPING FOR IMPROVED MEMORY OPERATION FOR FLOATING BODY CELL (FBC) MEMORY - An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage. | 03-25-2010 |
20100155880 | Back gate doping for SOI substrates - A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×10 | 06-24-2010 |
20120267721 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 10-25-2012 |
20130279845 | FABRICATION OF PLANAR LIGHT-WAVE CIRCUITS (PLCS) FOR OPTICAL I/O - PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region. | 10-24-2013 |
20140003765 | WAVEGUIDE INTEGRATION ON LASER FOR ALIGNMENT-TOLERANT ASSEMBLY | 01-02-2014 |
20140015021 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 01-16-2014 |
20140086527 | VERTICAL LIGHT COUPLER - An optical coupler includes a double-sided planar substrate having a lens manufactured on one side and a mode expander on the other side. The mode expander is coupled to a mirror that redirects light between the mode expander and the lens. The mirror is lithographically aligned with the lens. The substrate is optically transparent to a target wavelength to be used for optical signaling. The lens can be a lens array, in which case there can be a mirror for each lens in the array. The mode expander can couple an optical signal to a planar lightwave circuit (PLC) or other optical circuit. The lens on the optical coupler can interface with a single-mode optical fiber. | 03-27-2014 |
20140177995 | OPTICAL PHOTONIC CIRCUIT COUPLING - Systems and methods may couple on-chip optical circuits to external fibers. An SOI waveguide structure may include mirror structures and tapered waveguides to optically couple optical circuits to fibers in a vertically oriented external connector. The mirror structure(s) may be angularly disposed at the ends of the silicon waveguide structure. An oxide layer may cover a buried oxide layer and the silicon waveguide structure. The tapered waveguide(s) may have a narrow end and a wide end. The narrow end of the tapered waveguide(s) may be disposed above the mirror structures. The tapered waveguide(s) may extend through the oxide layer from the narrow end in a direction perpendicular to the silicon waveguide structure. An external connector may fit over the tapered waveguide(s) and uses a fiber array traveling through a connector body to optically couple to the external fiber. | 06-26-2014 |