Patent application number | Description | Published |
20090319728 | Virtualized SAS Adapter with Logic Unit Partitioning - A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access. | 12-24-2009 |
20090327537 | Virtualized Serial Attached SCSI Adapter - A method, computer program product and computer system for the virtualization of an SAS storage adapter for logical partitions of a computer system, which includes providing a hypervisor, assigning a logical storage adapter to an operating system on one of the logical partitions, configuring the logical storage adapter using the hypervisor, and enabling data storage operations to use the logical storage adapter. | 12-31-2009 |
20120297272 | IMPLEMENTING ENHANCED IO DATA CONVERSION WITH PROTECTION INFORMATION MODEL INCLUDING PARITY FORMAT OF DATA INTEGRITY FIELDS - A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs. | 11-22-2012 |
20120303855 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA - A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations. | 11-29-2012 |
20120303859 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING - A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations. | 11-29-2012 |
20120303883 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING - A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode. | 11-29-2012 |
20120303886 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE CHAINS TO SELECT PERFORMANCE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance. | 11-29-2012 |
20120303909 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE - A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor. | 11-29-2012 |
20120303922 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION - A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance. | 11-29-2012 |
20120304001 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations. | 11-29-2012 |
20120304198 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS - A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor. | 11-29-2012 |
20150052265 | IMPLEMENTING HARDWARE AUTO DEVICE OPERATIONS INITIATOR - A method and controller for implementing hardware auto device op initiator in a data storage system, and a design structure on which a subject controller circuit resides are provided. The controller includes an inline hardware engine receiving host commands, and assessing a received command for starting without firmware involvement. The inline hardware engine builds one or more chains of hardware command blocks to perform the received command and starts executing the chain or chains for the received command. | 02-19-2015 |
Patent application number | Description | Published |
20080243743 | APPARATUS FOR DYNAMICALLY DETERMINING PRIMARY ADAPTER IN A HETEROGENEOUS N-WAY ADAPTER CONFIGURATION - A method and apparatus are provided for dynamically determining a primary adapter in a heterogeneous N-way adapter configuration. Each of the adapters generates information about itself and exchanges the information with all other adapters. First a decision-making adapter is identified. Then the decision-making adapter compares the adapter-generated information of all the adapters and makes a decision determining the primary adapter. The decision-making adapter communicates the decision to all other adapters. The determined primary adapter assumes a role as the primary adapter and the other adapters assume a role as a secondary adapter. | 10-02-2008 |
20090182969 | DYNAMIC ALLOCATION OF DMA BUFFERS IN INPUT/OUTPUT ADAPTORS - A method and apparatus for dynamic allocation of DMA buffers in the DRAM banks of an I/O adaptor. The method and apparatus determine the functional status of the adaptor, allocate critical, volatile DMA buffers in non-critical DRAM banks if the adaptor is fully functional, and allocate critical, volatile DMA buffers in critical DRAM banks if the adaptor is partially functional. | 07-16-2009 |
20090300308 | Partitioning of a Multiple Logic-Unit-Number SCSI Target - A method, computer program product and computer system for assigning logic storage entities of a storage device to multiple partitions of a computer system, which includes associating each logic storage entity to one of the partitions that are allowed to access the logic storage entity; configuring a partition supervisor to control accesses of the partitions to the logic storage entities, so that the partitions can share resources when accessing the logic storage entities; and providing an interceptor in the partition supervisor, so that a request or a response between a select logic storage entity and a select partition is intercepted if the select partition is not allowed to access the select storage entity. | 12-03-2009 |
Patent application number | Description | Published |
20080244747 | Network context triggers for activating virtualized computer applications - A computer system, comprising at least one controlled execution space hosting an operating system and an application program; a vulnerability monitoring agent coupled to the controlled execution space; one or more vulnerability profiles coupled to the vulnerability monitoring agent, wherein each of the vulnerability profiles comprises an application program identifier, an operating system identifier, a vulnerability specification describing a vulnerability of an application program that the application program identifier indicates when executed with an operating system that the operating system identifier indicates, and a remedial action which when executed will remediate the vulnerability; wherein the vulnerability monitoring agent is configured to monitor execution of the operating system and the application program in the controlled execution space, to detect an anomaly associated with the vulnerability, to determine the remedial action for the operating system and application program based on one of the vulnerability profiles, and to cause the remedial action. | 10-02-2008 |
20100290473 | Port grouping for association with virtual interfaces - In one embodiment, an apparatus includes a port channel manager for receiving information identifying switches connected to a group of physical ports at a network device and creating subgroups each comprising the physical ports connected to one of the switches. The apparatus further includes a virtual interface agent for assigning a virtual interface connecting a virtual switch to a virtual machine, to one of the subgroups. Traffic received from the virtual machine on the virtual interface is transmitted to one of the switches on one of the physical ports in the assigned subgroup. A method for grouping ports for association with virtual interfaces is also disclosed. | 11-18-2010 |
20110173295 | OFFLOAD STACK FOR NETWORK, BLOCK AND FILE INPUT AND OUTPUT - An apparatus for offloading network, block and file functions from an operating system comprises a network interface coupled to a network for receiving packet flows; one or more processors each having one or more processor cores; a computer-readable medium carrying one or more operating systems and an input/output networking stack which are hosted in one or more of the processor cores. The networking stack is shared among the operating systems. The networking stack comprises instructions which when executed cause receiving a request for data transfer from one of the operating systems at internal network, block and file system interfaces, and permitting data to be transferred between the internal interfaces and a plurality of external interfaces by preventing the operating systems from performing the data transfer and performing the data transfer on behalf of the operating systems. | 07-14-2011 |
20130125112 | DYNAMIC POLICY BASED INTERFACE CONFIGURATION FOR VIRTUALIZED ENVIRONMENTS - In one embodiment, a method includes receiving static profiles each comprising one or more properties of an operating environment, receiving a dynamic profile for identifying a configuration of an interface based on the static profile associated with said dynamic profile, associating the dynamic profile with one of the static profiles based on the operating environment of the interface, and automatically updating the association upon identifying a change in the operating environment. An apparatus is also disclosed. | 05-16-2013 |
Patent application number | Description | Published |
20090049199 | VIRTUAL MAC ADDRESS SYSTEM AND METHOD - A method for creating a virtual MAC address, the method includes receiving an Internet Protocol address that is to be associated with a virtual MAC address. The method creates a virtual MAC address by setting an OUI portion of the virtual MAC address to an OUI value and setting the non-OUI portion of the virtual MAC address to a subset of the Internet Protocol (IP) address. In one embodiment, the lower three bytes of the IP address are used. Additionally, a method of migrating a virtual MAC address includes detecting a migration event on a first system; creating a virtual MAC address on a second system; and issuing a gratuitous ARP packet containing the virtual MAC address. | 02-19-2009 |
20090285227 | TRANSPARENT MODE - A method, system, apparatus, and signal-bearing media for provided discovering a target device via one port of a plurality of virtual ports, creating a target data structure associated with the target device, and allocating a second port of the plurality of virtual ports to a host if the second port is available. In an embodiment, an initiator identifier for the host may be created based on a port number of the second port and a media access control address and sent to the target device to identify the host. | 11-19-2009 |
20100057908 | CENTRALIZED CONTROL PLANE APPLIANCE FOR VIRTUAL INFRASTRUCTURE - In a virtual infrastructure, a single appliance is provided that hosts a centralized virtual machine monitor (VMM) control plane to effectively establish a single virtual switch across all virtual machines within one or more clusters of servers, thereby reducing the number of management points for the network administrator and facilitating easier VM migration. | 03-04-2010 |
20110274110 | METHOD FOR PREVENTING MAC SPOOFS IN A DISTRIBUTED VIRTUAL SWITCH - Described herein are techniques for preventing MAC address spoofs in a virtualization cluster. When a virtual switch first sees a new MAC address on a port designated as being a secure port, the packet is redirected to a virtual supervisor agent used to manage the distributed virtual switch. Assuming the MAC may be bound to the secure port, the supervisor agent broadcasts a message to both the virtual switch that redirected the packet and to virtual switches on other virtualization servers within the cluster. | 11-10-2011 |