Patent application number | Description | Published |
20090136091 | DATA PROCESSING SYSTEM AND METHOD - A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator. | 05-28-2009 |
20090245617 | System and method for processing image data - Embodiments of the present invention recite a system for providing product consulting using a transmitted image. In one embodiment, the present invention comprises an image capture device for capturing an image of a user and a reference color set. In embodiments of the present invention, the image capture device does not require a provided infrastructure when capturing the image. The system further comprises a categorizing system for determining at least one data category from data comprising the image. A result generator generates a result based upon the determining of the categorizing system. The system further comprises a result reporting system for conveying the product consultation to the user when the result is conveyed. | 10-01-2009 |
20110210851 | Generation of a disparity result with low latency - A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of | 09-01-2011 |
20120019530 | STEREO DISPLAY SYSTEMS - Various embodiments of the present invention are directed to stereo display systems. In one embodiment, the stereo display system includes a display ( | 01-26-2012 |
20120099788 | METHOD AND APPARATUS FOR SELECTING A COLOR PALETTE - A method for selecting a color palette includes receiving a feature from an image of an object and a reference color chart, calculating a transform to correct a color in the imaged reference color chart, correcting a color in the feature using the transform, and selecting a color palette based on the corrected feature color. The reference color chart includes reference colors, and the transform corrects the color in the imaged reference color chart to substantially equal a corresponding reference color. An apparatus for selecting a color palette is also described. | 04-26-2012 |
20120105574 | PANORAMIC STEREOSCOPIC CAMERA - A panoramic stereographic camera includes a first cylindrical array of imagers with adjoining fields of view that cover a panoramic portion of a scene, each imager in the first cylindrical array being oriented at a first skew angle. A second cylindrical array of imagers with adjoining fields of view covers the same panoramic portion of the scene. Each imager in the second cylindrical array is oriented at a second skew angle. The images formed by the first cylindrical array of imagers and images created by the second cylindrical array of imagers are combined to produce a panoramic stereographic image. | 05-03-2012 |
20130044181 | SYSTEM AND METHOD FOR MULTI-VIEWPOINT VIDEO CAPTURE - Embodiments of the present invention disclose a system and method for multi-viewpoint video capture. According to one embodiment, the system includes a camera housing for accommodating both a first multi-imager set and a second multi-imager set, with each multi-imager set including a plurality of optical cameras having different viewpoint directions and configured to produce a source image. Furthermore, each camera in the first multi-imager set and the second multi-imager set include corresponding cameras facing in approximately the same viewpoint direction. The first multi-imager set is positioned laterally adjacent to the second multi-imager set such that lines joining a center of projection of corresponding cameras in the first multi-imager set and second multi-imager set are approximately parallel. | 02-21-2013 |
20130101160 | GENERATION OF A DISPARITY RESULT WITH LOW LATENCY - A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data. | 04-25-2013 |
20130235398 | METHOD AND SYSTEM FOR CREATING A CUSTOMIZED PRINT - A method for producing a customized print includes determining a color of at least one feature of an object, where the object is imaged with a reference color chart. A color palette is selected based on the at least one determined feature color and a print is generated based on the selected color palette. A system for producing a customized print is also described. | 09-12-2013 |
Patent application number | Description | Published |
20090079746 | SWITCHING BETWEEN GRAPHICS SOURCES TO FACILITATE POWER MANAGEMENT AND/OR SECURITY - One embodiment of the present invention provides a system that switches between frame buffers which are used to refresh a display. During operation, the system refreshes the display from a first frame buffer which is located in a first memory. Upon receiving a request to switch frame buffers for the display, the system reconfigures data transfers to the display so that the display is refreshed from a second frame buffer which is located in a second memory. | 03-26-2009 |
20120005496 | POWER DISTRIBUTION INSIDE CABLE - Circuits, methods, and apparatus that provide for the powering of active components in connector inserts at each end of a cable may in various ways. For example, where a host is coupled to a device that is not self-powered, the host may provide power for circuitry at each end of the cable. In various embodiments of the present invention, the device may request higher voltage from the host, such that more power can be delivered. In these cases, the device may regulate the voltage received from the host to a lower voltage, and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a device that is self-powered, the host and the self-powered device may power their respective connector insert circuits. | 01-05-2012 |
20130173936 | POWER DISTRIBUTION INSIDE CABLE - Circuits, methods, and apparatus that provide for the powering of active components in connector inserts at each end of a cable may in various ways. For example, where a host is coupled to a device that is not self-powered, the host may provide power for circuitry at each end of the cable. In various embodiments of the present invention, the device may request higher voltage from the host, such that more power can be delivered. In these cases, the device may regulate the voltage received from the host to a lower voltage, and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a device that is self-powered, the host and the self-powered device may power their respective connector insert circuits. | 07-04-2013 |
20140359319 | POWER DISTRIBUTION INSIDE CABLE - Circuits, methods, and apparatus that provide for the powering of active components in connector inserts at each end of a cable may in various ways. For example, where a host is coupled to a device that is not self-powered, the host may provide power for circuitry at each end of the cable. In various embodiments of the present invention, the device may request higher voltage from the host, such that more power can be delivered. In these cases, the device may regulate the voltage received from the host to a lower voltage, and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a device that is self-powered, the host and the self-powered device may power their respective connector insert circuits. | 12-04-2014 |
20140361671 | COMPUTER INTERNAL ARCHITECTURE - An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (GPU) board, a central processing unit (CPU) board, an input/output (I/O) interface board, an interconnect board, and a power supply unit (PSU). | 12-11-2014 |
20140361893 | COMPUTER INPUT/OUTPUT INTERFACE - An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (GPU) board, a central processing unit (CPU) board, an input/output (I/O) interface board, an interconnect board, and a power supply unit (PSU). | 12-11-2014 |
20140362519 | COMPUTER SYSTEM - A desktop computing system having at least a central core surrounded by housing having a shape that defines a volume in which the central core resides is described. The housing includes a first opening and a second opening axially displaced from the first opening. The first opening having a size and shape in accordance with an amount of airflow used as a heat transfer medium for cooling internal components, the second opening defined by a lip that engages a portion of the airflow in such a way that at least some of the heat transferred to the air flow from the internal components is passed to the housing. | 12-11-2014 |
20140362576 | COMPUTER ARCHITECTURE - An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (GPU) board, a central processing unit (CPU) board, an input/output (I/O) interface board, an interconnect board, and a power supply unit (PSU). | 12-11-2014 |
Patent application number | Description | Published |
20080198745 | Dynamic multi-hop negotiations - Negotiation of RSVP reservations prior to the setup of a call, rather than negotiating reservation parameters during the call. RSVP reservation parameters are negotiated prior to ringing a device, rather than after. In some embodiments, this is achieved by including information in the initial call signaling elements. This added information allows negotiation with each device in the proposed data path to determine, prior to ringing the terminating device in the data path, whether each of the devices can support the proposed data link. | 08-21-2008 |
20080304565 | REDUCING THE NETWORK LOAD OF EVENT-TRIGGERED VIDEO - In one embodiment, a method for reducing the network load of an event-triggered video system comprising transmitting a first ‘play’ indication by a controlling process over a data network, to an appropriately configured video encoding process, transmitting first video data by the encoding process in response to receiving the first ‘play’ indication, the first video data being transmitted over the data network through a communication channel established over the data network between the encoding process and a recording process and receiving the first video data by the recording process. | 12-11-2008 |
20090204812 | MEDIA PROCESSING - In an example embodiment, an apparatus comprising a communication interface configured to be in data communication with another device, and processing logic that is operably coupled to the communication interface. The processing logic is operable to process a packet received via the communication interface, the packet comprising a header and a payload. The processing logic is configured to acquire information about the contents of the payload from the header. For example, the processing logic can determine from the header of the packet whether the payload contains sensitive data; contains analytic, video, and/or audio data; and/or whether the payload is encrypted. | 08-13-2009 |