Patent application number | Description | Published |
20130007415 | METHOD AND APPARATUS FOR SCHEDULING OF INSTRUCTIONS IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR - In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel. | 01-03-2013 |
20130339679 | METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTION WAKEUP LOGIC IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR - A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit. | 12-19-2013 |
20140208074 | INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR - In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed. | 07-24-2014 |
20150277910 | METHOD AND APPARATUS FOR EXECUTING INSTRUCTIONS USING A PREDICATE REGISTER - An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence. | 10-01-2015 |
20160092367 | HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE - Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. | 03-31-2016 |
Patent application number | Description | Published |
20140030836 | Silicon Carbide Lamina - A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer. | 01-30-2014 |
20140048201 | BONDING OF THIN LAMINA - Methods and apparatus are provided for bonding a thin lamina to a carrier. In some embodiments, a first side of the lamina is separably contacted to a support plate. A first carrier having a first side with a layer of adhesive material is contacted to the second side of the thin lamina. The lamina is fixed to the first carrier, where the fixing includes a first application of heat and pressure to a portion of the lamina and the first carrier. The support plate is removed, and a second application of heat and pressure are applied to the lamina and the first carrier. The second application of heat and pressure promotes an adhesive bond between the lamina and the first carrier. The second application of pressure comprises moving the lamina, the first carrier and a cover sheet between a pair of rollers. | 02-20-2014 |
20140261654 | FREE-STANDING METALLIC ARTICLE FOR SEMICONDUCTORS - A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface with a preformed pattern, wherein at least a portion of the metallic article is formed in the preformed pattern. The metallic article is separated from the electrically conductive mandrel, which forms a free-standing metallic article that may be coupled with the surface of a semiconductor material for a photovoltaic cell. | 09-18-2014 |
20140261659 | Free-Standing Metallic Article for Semiconductors - A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface with a preformed pattern, wherein at least a portion of the metallic article is formed in the preformed pattern. The metallic article is separated from the electrically conductive mandrel, which forms a free-standing metallic article that may be coupled with the surface of a semiconductor material for a photovoltaic cell. | 09-18-2014 |
20140261661 | FREE-STANDING METALLIC ARTICLE WITH OVERPLATING - A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface layer having a preformed pattern. The outer surface layer has a dielectric region and an exposed metal region. The metallic article has a plurality of electroformed elements that are formed on the exposed metal region of the outer surface layer of the electrically conductive mandrel. A first electroformed element has an overplated portion formed above the outer surface layer of the mandrel. The metallic article is configured to serve as an electrical conduit for a photovoltaic cell, and forms a unitary, free-standing piece when separated from the electrically conductive mandrel. | 09-18-2014 |
20140262793 | ADAPTABLE FREE-STANDING METALLIC ARTICLE FOR SEMICONDUCTORS - A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The metallic article has a plurality of electroformed elements that are configured to serve as an electrical conduit for a photovoltaic cell. A first electroformed element has at least one of: a) a non-uniform width along a first length of the first element, b) a change in conduit direction along the first length of the first element, c) an expansion segment along the first length of the first element, d) a first width that is different from a second width of a second element in the plurality of electroformed elements, e) a first height that is different from a second height of the second element in the plurality of electroformed elements, and f) a top surface that is textured. | 09-18-2014 |
20160027947 | FREE-STANDING METALLIC ARTICLE FOR SEMICONDUCTORS - A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface with a preformed pattern, wherein at least a portion of the metallic article is formed in the preformed pattern. The metallic article is separated from the electrically conductive mandrel, which forms a free-standing metallic article that may be coupled with the surface of a semiconductor material for a photovoltaic cell. | 01-28-2016 |