| Patent application number | Description | Published |
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| 20130282951 | SYSTEM AND METHOD FOR SECURE BOOTING AND DEBUGGING OF SOC DEVICES - Disclosed are systems, methods and computer program products for secure rebooting and debugging a peripheral subsystem of a system on a chip (SoC) device. According to one aspect of the method, when an application processor of the SoC device detects crash of the peripheral subsystem, the application processor loads a secure boot agent into SoC memory. The secure boot agent is configured to access a secure memory region of the peripheral subsystem containing memory dump data associated with the peripheral subsystem. The secure memory region is inaccessible to the application processor. The Secure boot agent encrypts the memory dump data in the secure memory region and opens the secure memory region for access to the application processor. The application processor accesses the secure memory region and collects the encrypted memory dump data. The application processor then forwards the encrypted memory dump data to a third party for debugging purposes. | 10-24-2013 |
| 20140047251 | METHODS, SYSTEMS AND DEVICES FOR HYBRID MEMORY MANAGEMENT - In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by translating virtual memory addresses into physical addresses on a computing system having hybrid memory. In a first stage of memory translation, an operating system translates virtual addresses to intermediate physical addresses. In a second stage of memory translation, a chip or virtualization software translates the intermediate physical address to physical addresses based on the characteristics of the physical memory and the characteristics of the processes associated with the physical memory. | 02-13-2014 |
| 20140258586 | METHODS AND SYSTEMS FOR REDUCING THE AMOUNT OF TIME AND COMPUTING RESOURCES THAT ARE REQUIRED TO PERFORM A HARDWARE TABLE WALK (HWTW) - A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions. | 09-11-2014 |
| 20140258663 | METHOD AND APPARATUS FOR PREVENTING UNAUTHORIZED ACCESS TO CONTENTS OF A REGISTER UNDER CERTAIN CONDITIONS WHEN PERFORMING A HARDWARE TABLE WALK (HWTW) - A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions. | 09-11-2014 |
| 20140281283 | DUAL HOST EMBEDDED SHARED DEVICE CONTROLLER - Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data. | 09-18-2014 |
| 20140282501 | Algorithm and Apparatus To Deploy Virtual Machine Monitor on Demand - In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations. | 09-18-2014 |
| 20140282580 | METHOD AND APPARATUS TO SAVE AND RESTORE SYSTEM MEMORY MANAGEMENT UNIT (MMU) CONTEXTS - A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources. | 09-18-2014 |
| 20150067287 | DISTRIBUTED DYNAMIC MEMORY MANAGEMENT UNIT (MMU)-BASED SECURE INTER-PROCESSOR COMMUNICATION - A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs. | 03-05-2015 |
| 20150127866 | Secure, Fast and Normal Virtual Interrupt Direct Assignment in a Virtualized Interrupt Controller in a Mobile System-On-Chip - Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful. | 05-07-2015 |
| 20150161057 | SYSTEM AND METHOD FOR PROVIDING CLIENT-SIDE ADDRESS TRANSLATION IN A MEMORY MANAGEMENT SYSTEM - Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect. The application processor comprises test code for testing one or more of a plurality of hardware devices. Each of the hardware devices has a corresponding system memory management unit (SMMU) for processing memory requests associated with the hardware device to the memory device. The system further comprises a client-side address translation system in communication with the system interconnect and the plurality of SMMUs. The client-side address translation system is configured to selectively route stimulus traffic associated with the test code to a client port on one or more of the plurality of SMMUs for testing the corresponding hardware devices. | 06-11-2015 |
| 20150261686 | SYSTEMS AND METHODS FOR SUPPORTING DEMAND PAGING FOR SUBSYSTEMS IN A PORTABLE COMPUTING ENVIRONMENT WITH RESTRICTED MEMORY RESOURCES - A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory. A first area of the primary memory is used for storing time critical code and data. A second area is available for demand pages required by a thread executing in the processor. A secondary memory is accessible to a hypervisor. The processor generates an interrupt when a page fault is detected. The hypervisor, in response to the interrupt, initiates a direct memory transfer of information in the secondary memory to the second area available for demand pages in the primary memory. Upon completion of the transfer, the hypervisor communicates a task complete acknowledgement to the processor. | 09-17-2015 |
| 20150268706 | SYSTEM AND METHOD FOR MEMORY POWER MANAGEMENT IN A SYSTEM ON A CHIP WITH MULTIPLE EXECUTION ENVIRONMENTS - Various embodiments of methods and systems for hardware-based memory power management (“HMPM”) in a portable computing device (“PCD”) running secure and non-secure execution environments are disclosed. Hardware-based state machines are uniquely associated with, and under the control of, the non-secure execution environment, the secure execution environment and a virtual manager, respectively. The states of the state machines constitute votes by each of the execution environments and the virtual manager to control the power supply state to the memory component, such as a cache memory. The votes are monitored by a digital circuit that, based on a combination logic of the votes, generates an output signal to trigger a power management component to maintain, supply or remove power on a rail associated with the memory component. In this way, the power supply state to the memory component cannot be unilaterally changed by an application running in the non-secure execution environment. | 09-24-2015 |
| Patent application number | Description | Published |
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| 20120106357 | VARIABLE STEP-SIZE LEAST MEAN SQUARE METHOD FOR ESTIMATION IN ADAPTIVE NETWORKS - The variable step-size least mean square method for estimation in adaptive networks uses a variable step-size to provide estimation for each node in the adaptive network, where the step-size at each node is determined by the error calculated for each node, as opposed to conventional least mean square algorithms used in adaptive filters and the like, where the choice of step-size reflects a tradeoff between misadjustment and the speed of adaptation. | 05-03-2012 |
| 20120109600 | VARIABLE STEP-SIZE LEAST MEAN SQUARE METHOD FOR ESTIMATION IN ADAPTIVE NETWORKS - The variable step-size least mean square method for estimation in adaptive networks uses a variable step-size to provide estimation for each node in the adaptive network, where the step-size at each node is determined by the error calculated for each node, as opposed to conventional least mean square algorithms used in adaptive filters and the like, where the choice of step-size reflects a tradeoff between misadjustment and the speed of adaptation. | 05-03-2012 |
| 20120135691 | NOISE-CONSTRAINED DIFFUSION LEAST MEAN SQUARE METHOD FOR ESTIMATION IN ADAPTIVE NETWORKS - The noise-constrained diffusion least mean square method for estimation in adaptive networks is based on the Least Mean Squares (LMS) algorithm. The method uses a variable step size in which the step-size variation rule results directly from the noise constraint. | 05-31-2012 |
| 20120257668 | TIME-VARYING LEAST-MEAN-FOURTH-BASED CHANNEL EQUALIZATION METHOD AND SYSTEM - The time-varying least-mean-fourth-based channel equalization method is an automated procedure that provides an adaptive equalizer in a CDMA receiver. Equalizer filter coefficients are estimated using a least-mean-fourth (LMF) error calculation based on a training set of symbols sent by the transmitter. When the LMF error calculation is combined with a power-of-two quantization (PTQ) process, superior receiver performance is achieved in a time-varying CDMA channel operating in non-Gaussian noise environments. | 10-11-2012 |
| 20130110478 | APPARATUS AND METHOD FOR BLIND BLOCK RECURSIVE ESTIMATION IN ADAPTIVE NETWORKS | 05-02-2013 |
| 20130254250 | SYSTEM AND METHOD FOR LEAST MEAN FOURTH ADAPTIVE FILTERING - The system and method for least mean fourth adaptive filtering is a system that uses a general purpose computer or a digital circuit (such as an ASIC, a field-programmable gate array, or a digital signal processor that is programmed to utilize a normalized least mean fourth algorithm. The normalization is performed by dividing a weight vector update term by the fourth power of the norm of the regressor. | 09-26-2013 |
| 20140310326 | ADAPTIVE FILTER FOR SYSTEM IDENTIFICATION - The adaptive filter for system identification is an adaptive filter that uses an algorithm in the feedback loop that is designed to provide better performance when the unknown system model has sparse input, i.e., when the filter has only a few non-zero coefficients, such as digital TV transmission channels and echo paths. In a first embodiment, the algorithm is the Normalized Least Mean Square (NLMS) algorithm in which the filter coefficients are updated at each iteration according to: | 10-16-2014 |
| 20150263701 | ADAPTIVE FILTER FOR SYSTEM IDENTIFICATION - The adaptive filter for sparse system identification is an adaptive filter that uses an algorithm in the feedback loop that is designed to provide better performance when the unknown system model is sparse, i.e., when the filter has only a few non-zero coefficients, such as digital TV transmission channels and echo paths. The algorithm is a least mean square algorithm with filter coefficients updated at each iteration, as well as a step size that is also updated at each iteration. The adaptive filter may be implemented on a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or by field-programmable gate arrays (FPGAs). | 09-17-2015 |
