Patent application number | Description | Published |
20120176630 | IMAGE PROCESSOR AND IMAGE FORMING APPARATUS - Provided is an image processor obtaining image data divided in packing units, comprising: a parallel processing unit performing an image conversion processing in parallel on the pixel data arranged in a sub scan direction in the packing unit, based on the obtained pixel data and the intermediate value for the pixel data, to calculate an output value after the conversion of the pixel data and an index value; an intermediate value calculating unit calculating an intermediate value based on the respective index values calculated by the parallel processing units regarding pixels within a predetermined relative position range; and a first retention unit for delaying the start of the image conversion processing to one pixel data for a delay period set to be equal to or longer than a period required for obtaining the one pixel data and calculating the intermediate value for the one pixel data. | 07-12-2012 |
20140153063 | SIGNAL PROCESSING APPARATUS AND IMAGE FORMING APPARATUS - A signal processing apparatus includes a pulse signal producing section configured to produce image creating signals for image formation in response to image data by using an image processing clock corresponding to each pixel of the image data; a measuring section configured to measure a difference between an actual value and an ideal value of a signal width of the image creating signal at the time of measurement; and a processing section configured to correct the image data so as to cancel the difference at the time of an actual action. | 06-05-2014 |
20150338763 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND IMAGE FORMING APPARATUS - A signal processing device that generates an output signal from image data by using a clock corresponding to the pixels of the image data, the signal processing device includes: a delayed signal group generating unit that generates a group of delayed signals with a delay element group formed with stages of delay elements; a clock adjusting unit that generates a modulation/synchronization clock from the group of delayed signals by referring to phase data matching the clock with a predetermined phase and frequency modulation coefficient data converting the clock to a predetermined frequency; and a PWM processing unit that generates a PWM signal from the group of delayed signals by referring to the phase data, the frequency modulation coefficient data, the modulation/synchronization clock, and the image data, the PWM signal having a pulse width corresponding to the value of the image data. | 11-26-2015 |