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Ashtiani

Babak Nakhayi Ashtiani, Sammamish, WA US

Patent application numberDescriptionPublished
20150161542INTEGRATION BETWEEN PROJECT PLANNING SYSTEM AND BUSINESS SYSTEM - A project management system receives project planning inputs from a user, to create and plan a project. It receives a publication input, publishing the project, to a business system and receives financial and operational reference data from the business system. It also receives resource data from the business system and provides a resource user interface display that allows a user to staff the project with resources received from the business system.06-11-2015

Babak Nakhayi Ashtiani, Redmond, WA US

Patent application numberDescriptionPublished
20120303401FLEXIBLE WORKFLOW TASK ASSIGNMENT SYSTEM AND METHOD - Enterprise systems, methods and computer program products are disclosed for facilitating a flexible assignment of tasks to work item queues according to assignment rules and conditions for a business document. The system comprises associating an application object server response to a client workflow form or control, associating an expression to an assignment rule or condition with the work item queue and creating a default work item queue for an expression or series of ordered expressions that do not evaluate true. During runtime, the flexible workflow task assignment process evaluates the sequence of ordered expressions for a given work item queue until no next expression is to be evaluated and assigning the task to the default work item queue.11-29-2012
20130246110VISUALIZING RESOURCE REQUIREMENTS ALONG A TIMELINE - A work definition is generated. The work definition includes resource requirements needed to perform tasks in the work definition. The resource requirements are displayed along a timeline. Resource availability can also be displayed along the same timeline.09-19-2013
20140343988AUTOMATIC RESOURCE SCHEDULING - An activity is selected. Resource requirement user inputs, indicative of resource requirements for the activity, are received, as are priorities identifying which of the resource requirements are more important than others. Resources are automatically identified based on how well they match the resource requirements, as prioritized, and based on availability. The identified resources are automatically assigned to the activity.11-20-2014

Patent applications by Babak Nakhayi Ashtiani, Redmond, WA US

Kaihan Ashtiani, Cupertino, CA US

Patent application numberDescriptionPublished
20100159694METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.06-24-2010
20110151678NOVEL GAP FILL INTEGRATION - Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.06-23-2011
20110223763METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FOR HIGH ASPECT RATIO AND SMALL FEATURES - The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained.09-15-2011
20120015518METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.01-19-2012
20120040530METHODS FOR FORMING ALL TUNGSTEN CONTACTS AND LINES - Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.02-16-2012
20130230987FLOWABLE OXIDE FILM WITH TUNABLE WET ETCH RATE - Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.09-05-2013
20140302689METHODS AND APPARATUS FOR DIELECTRIC DEPOSITION - Methods for depositing flowable dielectric films are provided. In some embodiments, the methods involve introducing a silicon-containing precursor to a deposition chamber wherein the precursor is characterized by having a partial pressure:vapor pressure ratio between 0.01 and 1. In some embodiments, the methods involve depositing a high density plasma dielectric film on a flowable dielectric film. The high density plasma dielectric film may fill a gap on a substrate. Also provided are apparatuses for performing the methods.10-09-2014
20150044882FLOWABLE OXIDE FILM WITH TUNABLE WET ETCH RATE - Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.02-12-2015
20150118863METHODS AND APPARATUS FOR FORMING FLOWABLE DIELECTRIC FILMS HAVING LOW POROSITY - Provided herein are methods and apparatus for forming flowable dielectric films having low porosity. In some embodiments, the methods involve plasma post-treatments of flowable dielectric films. The treatments can involve exposing a flowable film to a plasma while the film is still in a flowable, reactive state but after deposition of new material has ceased.04-30-2015

Patent applications by Kaihan Ashtiani, Cupertino, CA US

Kaihan Ashtiani, Sunnyvale, CA US

Patent application numberDescriptionPublished
20080254623METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FOR HIGH ASPECT RATIO AND SMALL FEATURES - The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained.10-16-2008
20090163025METHODS FOR FORMING ALL TUNGSTEN CONTACTS AND LINES - Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.06-25-2009

Kaihan Ashtiani, San Jose, CA US

Patent application numberDescriptionPublished
20160118296Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition - A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.04-28-2016

Kaihan Abidi Ashtiani, Cupertino, CA US

Patent application numberDescriptionPublished
20130341433DUAL PLENUM, AXI-SYMMETRIC SHOWERHEAD WITH EDGE-TO-CENTER GAS DELIVERY - A dual-plenum showerhead for semiconductor processing operations is provided. The showerhead may include a faceplate with two sets of gas distribution holes, each set fed by a separate plenum. One set of gas distribution holes may be through-holes in a faceplate of the showerhead and may allow gases trapped between the faceplate and a plasma dome to flow towards a wafer. The other set of gas distribution holes may distribute gas routed through passages or channels in the faceplate towards the wafer. The passages or channels in the faceplate may include radial channels and annular channels and may be fed from an annular gas distribution channel about the periphery of the faceplate.12-26-2013
20150240361APPARATUS AND METHOD FOR IMPROVING WAFER UNIFORMITY - A semiconductor processing gas flow manifold is provided that allows for the gas flow characteristics of the manifold gas flow paths to be individually adjusted outside of a semiconductor processing chamber. The gas flow manifold may be connected to a process gas dispersion device inside the semiconductor processing chamber. The process gas dispersion device may have multiple gas flow channels, each channel separately connected to a manifold gas flow path and targeted at a region on the semiconductor wafer. The adjustment of the individual manifold gas flow paths may vary the amount of process gas dispersed through each process gas dispersion gas flow channel onto the corresponding region of the semiconductor wafer.08-27-2015
20160056071FLOWABLE DIELECTRIC FOR SELECTIVE ULTRA LOW-K PORE SEALING - Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.02-25-2016

Patent applications by Kaihan Abidi Ashtiani, Cupertino, CA US

Mansour Ashtiani, Novi, MI US

Patent application numberDescriptionPublished
20140354755Method For Color Marking Metallic Surfaces - A method of color marking a metal or metal-plated part is described involving setting at least one laser parameter of a laser, such as the power, scan speed, Q-switch, spot size, line separation, and scan repetition, and then energizing a metal containing surface layer of the part using the laser to change the color reflected by the surface layer.12-04-2014

Pouya Ashtiani, Richmond Hill CA

Patent application numberDescriptionPublished
20110068632INTEGRATED CIRCUIT ADAPTED TO BE SELECTIVELY AC OR DC COUPLED - An integrated circuit is adapted to be selectively AC or DC coupled to an external device at a coupling point. The integrated circuit includes a first connector connected to the coupling point by way of a coupling capacitor for AC coupling, a second connector connected to the coupling point for DC coupling, and a switch to selectively short the first and second connectors and thereby the coupling capacitor, when the integrated circuit is DC coupled to the device. The switch may be a MOSFET bridge comprising a switch control MOSFET interconnected between the first and second connectors, with the switch control MOSFET receiving at its gate a mode status signal for turning on the switch control MOSFET and thereby shorting the MOSFET bridge when the integrated circuit is DC coupled to the external device. The MOSFET bridge also includes a number of dynamically biased nMOSFETs connected in series with the switch control MOSFET in order to protect switch control MOSFET from high external supply voltages, and a number of dynamically biased pMOSFETs connected in parallel with the switch control MOSFET.03-24-2011
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