Patent application number | Description | Published |
20090132839 | Method and device to handle denial of service attacks on wake events - A method and device may selectively resume a computing device from a low power state according to a security policy. The security policy may be embedded in the hardware of the computing device and may be enforced even when the device is in a low power state. Such a policy may provide protection from hacker and virus based denial of service attacks using a flood of packets formatted to provide a wake event request. Other embodiments are described and claimed. | 05-21-2009 |
20090172438 | METHOD AND APPARATUS FOR COST AND POWER EFFICIENT, SCALABLE OPERATING SYSTEM INDEPENDENT SERVICES - A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state. | 07-02-2009 |
20090172443 | Methods and apparatuses for processing wake events of communication networks - Methods, apparatuses, and computer program products that respond to wake events of communication networks are disclosed. One or more embodiments comprise setting a wake password of a computing device, such as a notebook computer or a server. Some of the embodiments comprise receiving a wake request from a communications network, establishing a secure communication session, and setting the wake password with the secure communication session. Some embodiments comprise an apparatus having a network controller to allow a platform to communicate via a communications network, non-volatile memory that stores a wake password, and a management controller which may communicate with a management console via a secure communication session to update the wake password. One or more embodiments the network controller may wake management hardware and/or wake the management controller while keeping one or more of the devices in the power conservation mode. | 07-02-2009 |
20100082961 | Apparatus and method to harden computer system - In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed. | 04-01-2010 |
20100083365 | Apparatus and method to harden computer system - In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed. | 04-01-2010 |
20100169968 | PROCESSOR EXTENSIONS FOR EXECUTION OF SECURE EMBEDDED CONTAINERS - Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed. | 07-01-2010 |
20110145598 | Providing Integrity Verification And Attestation In A Hidden Execution Environment - In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed. | 06-16-2011 |
20120159652 | APPARATUS AND METHOD TO HARDEN COMPUTER SYSTEM - In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed. | 06-21-2012 |
20130179693 | Providing Integrity Verification And Attestation In A Hidden Execution Environment - In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed. | 07-11-2013 |
20130271452 | MECHANISM FOR FACILITATING CONTEXT-AWARE MODEL-BASED IMAGE COMPOSITION AND RENDERING AT COMPUTING DEVICES - A mechanism is described for facilitating context-aware composition and rendering of virtual models and/or images of physical objects computationally composited and rendered at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes performing initial calibration of a plurality of computing devices to provide point of view positions of a scene according to a location of each of the plurality of computing devices with respect to the scene, where computing devices of the plurality of computing devices are in communication with each other over a network. The method may further include generating context-aware views of the scene based on the point of view positions of the plurality of computing devices, where each context-aware view corresponds to a computing device. The method may further include generating images of the scene based on the context-aware views of the scene, where each image corresponds to a computing device, and displaying each image at its corresponding computing device. | 10-17-2013 |
20140073302 | Sensor and Context Based Adjustment of the Operation of a Network Controller - A method to adjust operation of a network controller of a device is disclosed. The method may include receiving contextual data from a sensor communicatively coupled to the device. The method may also include analyzing the contextual data to determine the context of the device. The method may also include modifying the network controller operation based on the analyzed contextual data. | 03-13-2014 |
20140075211 | CASCADING POWER CONSUMPTION - A method and system for cascading power consumption is described herein. The method may include providing power to a first sensor and a second sensor, wherein the first sensor consumes more power than the second sensor. The method may also include detecting the first sensor does not capture a sample of data. In addition, the method may include stopping the flow of power to the first sensor. Furthermore, the method may include monitoring an operating environment with the second sensor. The method may also include providing power to the first sensor in response to the second sensor detecting a sample of data. | 03-13-2014 |
20140176572 | Offloading Touch Processing To A Graphics Processor - In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed. | 06-26-2014 |
20140176573 | Offloading Touch Processing To A Graphics Processor - In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed. | 06-26-2014 |
20140344961 | APPARATUS AND METHOD TO HARDEN COMPUTER SYSTEM - In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed. | 11-20-2014 |