Patent application number | Description | Published |
20090006895 | Method for debugging reconfigurable architectures - A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger. | 01-01-2009 |
20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 06-11-2009 |
20100070671 | METHOD AND DEVICE FOR PROCESSING DATA - In a system including a multidimensional field of reconfigurable elements, and a method for operating said field of reconfigurable elements, one or more groups of said elements suitable for processing a predetermined task may be determined, a particular one of the one or more groups is selected, and the selected group is configured in a predetermined manner during runtime for processing the predetermined task, and in manufacturing of said system. | 03-18-2010 |
20100095094 | METHOD FOR PROCESSING DATA - A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor. | 04-15-2010 |
20100228918 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described. | 09-09-2010 |
20100287324 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described. | 11-11-2010 |
20110012640 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described. | 01-20-2011 |
20120311301 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution. | 12-06-2012 |
20140310466 | Multi-processor bus and cache interconnection system - A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method. | 10-16-2014 |
20140325175 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - The present invention includes an integrated module including a plurality of data processing units including a memory device having processing instruction data stored therein. The processing instruction data including subconfiguration data for at least one of the data processing units, the subconfiguration data including a plurality of blocks. The integrated module further includes a barrier disposed between a first block and a second block of the plurality of blocks. Wherein, the data processing units process the processing instruction data from the memory device such that the barrier provides for the data processing units to observe a configuration sequence of the subconfiguration data. | 10-30-2014 |
20140337601 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming. | 11-13-2014 |
20140359254 | Logical cell array and bus system - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 12-04-2014 |
20150026431 | Method of Processing Data with an Array of Data Processors According to Application ID - A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel. | 01-22-2015 |
20150033000 | Parallel Processing Array of Arithmetic Unit having a Barrier Instruction - A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel. | 01-29-2015 |