Patent application number | Description | Published |
20080203495 | INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT - An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction. | 08-28-2008 |
20080213948 | DUAL WIRED INTEGRATED CIRCUIT CHIPS - A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts. | 09-04-2008 |
20080272458 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer. | 11-06-2008 |
20080277759 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer. | 11-13-2008 |
20080290458 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad. | 11-27-2008 |
20080293210 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor. | 11-27-2008 |
20080293233 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor. | 11-27-2008 |
20090004809 | Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material - A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers. | 01-01-2009 |
20090065925 | DUAL-SIDED CHIP ATTACHED MODULES - An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate. | 03-12-2009 |
20090121260 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 05-14-2009 |
20090121287 | DUAL WIRED INTEGRATED CIRCUIT CHIPS - A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts. | 05-14-2009 |
20090142924 | REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF CU WIRES BY SURFACE COATING - The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed. | 06-04-2009 |
20090155541 | FUSE AND PAD STRESS RELIEF - A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate. | 06-18-2009 |
20090164964 | DESIGN STRUCTURES INCLUDING INTEGRATED CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT - A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction. | 06-25-2009 |
20090184423 | LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME - A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via. | 07-23-2009 |
20090206488 | THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer. | 08-20-2009 |
20090278237 | THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE - A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture. | 11-12-2009 |
20100015765 | SHALLOW AND DEEP TRENCH ISOLATION STRUCTURES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion. | 01-21-2010 |
20100032808 | THROUGH WAFER VIA AND METHOD OF MAKING SAME - A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure. | 02-11-2010 |
20100032810 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate. | 02-11-2010 |
20100032811 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate. | 02-11-2010 |
20100044759 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 02-25-2010 |
20110049723 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 03-03-2011 |
20110068477 | THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE - A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture. | 03-24-2011 |
20110129996 | THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer. | 06-02-2011 |
20110241082 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 10-06-2011 |
20110302542 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 12-08-2011 |
20120329219 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate. | 12-27-2012 |
20120329265 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 12-27-2012 |
20130307158 | CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT - A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described. | 11-21-2013 |
20140151851 | TAPERED VIA AND MIM CAPACITOR - A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit. | 06-05-2014 |