Patent application number | Description | Published |
20140101359 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140101404 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101407 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101408 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140281209 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An indication of a virtual address is received. A current page size of a plurality of available page sizes is read from a register. A shift amount is determined based, at least in part, on the current page size. A bit shift of the virtual address is performed in which the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
20140281353 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
20150278084 | SEPARATE MEMORY ADDRESS TRANSLATIONS FOR INSTRUCTION FETCHES AND DATA ACCESSES - An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information. | 10-01-2015 |
20150278085 | SEPARATE MEMORY ADDRESS TRANSLATIONS FOR INSTRUCTION FETCHES AND DATA ACCESSES - An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information. | 10-01-2015 |