Patent application number | Description | Published |
20120219085 | Extremely High Speed Broadband Access Over Copper Pairs - Disclosed is an apparatus that includes a plurality of parallel digital signal transmitters that each receive one of a plurality of digital sub-signals wherein each of the plurality of digital signal transmitters is configured to transmit one of the plurality of digital sub-signals that each have about the same bandwidth. The apparatus also includes a combiner coupled to the transmitters and configured to shift some of the plurality of digital sub-signals and to combine the plurality of shifted digital sub-signals into a combined digital signal that has a total bandwidth of that is approximately equal to the sum of the bandwidths of the plurality of digital sub-signals. The total bandwidth comprises a plurality of shifted bandwidths of the plurality of digital sub-signals at about the same offset with respect to each other. The combined digital signal is transmitted over a digital subscriber loop. | 08-30-2012 |
20130195213 | Methods and Systems for Peak-to-Average Power Reduction Without Reducing Data Rate - A transmitter for performing multicarrier modulation comprising a processing unit configured to generate a multicarrier data signal comprising a plurality of subcarriers, wherein each of the plurality of subcarriers represents at least one data bit of a plurality of data bits, select a subset of the subcarriers based on signal quality information about one or more of the subcarriers, construct a kernel signal comprising the subset of subcarriers, and create a digital signal comprising combining the multicarrier data signal and a peak-to-average ratio (PAR) reduction signal based on the kernel signal, wherein a PAR of the digital signal is less than a PAR of the multicarrier data signal. | 08-01-2013 |
20130294597 | Aligning the Upstream DMT Symbols of Multiple Lines in a TDD DSL System - A method comprising transmitting a delay value to each of a plurality of digital subscriber line (DSL) transceivers, by a distribution point unit (DPU), and receiving a plurality of signals at substantially the same time, wherein each of the plurality of signals is from a different DSL transceiver in the plurality of DSL transceivers and transmitted at different times based on the delay value and a corresponding propagation delay. | 11-07-2013 |
20140105219 | Pre-fill Retransmission Queue - A method of discontinuous transmission data communication in a digital subscriber line (DSL) transceiver unit, the method comprising determining that a number of a plurality of bits available to transmit is enough to fill a data transfer unit (DTU), forming a DTU, by a DTU framer, comprising the plurality of bits, transferring the DTU to a retransmission queue, and determining the DTUs from the retransmission queue to be transmitted over a next time period used for transmitting over the DSL subscriber line by the DSL transceiver unit. | 04-17-2014 |
20140105314 | Initialization and Tracking for Low Power Link States - A method of coordinating a plurality of transceiver units (TUs), the method comprising receiving an initialization intent notification from a first TU in the plurality of TUs, sending a low-power link state (LPLS) transition notification to a second TU in the plurality of TUs, receiving a LPLS transition complete notification from the second TU in response to the second TU transitioning from a first mode to a second mode, wherein in the first mode the second TU is in an LPLS with a long inactivity period (LPLS-L), sending an able to initialize notification to the first TU, and performing a vector training procedure using the first TU and the second TU. | 04-17-2014 |
20140161000 | TIMING OFFSET CORRECTION IN A TDD VECTORED SYSTEM - A method in a time-division duplex (TDD) transceiver coupled to a subscriber line, the method comprising receiving a discrete multitone (DMT) signal from a second transceiver after a period of inactivity on the subscriber line, wherein the DMT signal comprises a plurality of pilot tones, and determining a timing offset between the transceiver and the second transceiver based on the plurality of pilot tones. | 06-12-2014 |
20140328442 | A Self-Synchronizing Probe Sequence - A method comprising modulating a plurality of synchronized signals by an orthogonal probe sequence (OPS) to generate a plurality of modulated synchronized signals, wherein the OPS comprises a zero element (0-element) column that indicates a start or an end of the OPS, and concurrently transmitting, using one or more transmitters, the plurality of modulated synchronized signals over a duration of a number of discrete multi-tone (DMT) symbols, wherein each of the plurality of modulated synchronized signals is intended for one of a plurality of receivers that are remotely coupled to the one or more transmitters via a vectored group of subscriber lines, and wherein the 0-element column causes all of the plurality of modulated synchronized signals to have a zero-amplitude during a first or a last of the DMT symbols. | 11-06-2014 |
20150055449 | Online Reconfiguration Transition Synchronization - An online reconfiguration method comprising communicating data transfer units (DTUs) using a subscriber line, monitoring the subscriber line for a line condition event, detecting the line condition event, wherein detecting the line condition event comprises determining whether the line condition triggers a threshold, sending an online reconfiguration request message that indicates a robust management channel (RMC) frame type in response to detecting the line condition event, wherein the RMC frame type is a normal RMC frame that comprises time marker information when the line condition event does not trigger the threshold, and wherein the RMC frame type is a special RMC frame that comprises time marker information when the line condition event triggers the threshold, receive an online reconfiguration response message that comprises the time marker information, and synchronizing a transition of one or more transmission parameters using the time marker information. | 02-26-2015 |
20150055690 | INITIALIZATION AND TRACKING FOR LOW POWER LINK STATES - A method of coordinating a plurality of transceiver units (TUs), the method comprising receiving an initialization intent notification from a first TU in the plurality of TUs, sending a low-power link state (LPLS) transition notification to a second TU in the plurality of TUs, receiving a LPLS transition complete notification from the second TU in response to the second TU transitioning from a first mode to a second mode, wherein in the first mode the second TU is in an LPLS with a long inactivity period (LPLS-L), sending an able to initialize notification to the first TU, and performing a vector training procedure using the first TU and the second TU. | 02-26-2015 |
20150063476 | Power Saving Idle Data Transmission Units - A method implemented in a multicarrier transmission system, the method comprising generating a plurality of constellation points by using one or more constellation mappers to map a plurality of special data sequences for an idle data transmission unit (IDTU), wherein the plurality of special data sequences are computed prior to the mapping such that the plurality of constellation points are essentially inner constellation points, wherein each of the inner constellation points resides in a constellation diagram that corresponds to one of a plurality of subcarriers used by the IDTU, and wherein the constellation diagram comprises a number of inner constellation points and a number of outer constellation points, with the inner constellation points being closer from an origin of the constellation diagram than the outer constellation points, and transmitting the plurality of constellation points. | 03-05-2015 |
Patent application number | Description | Published |
20110191732 | METHOD AND APPARATUS FOR DETERMINING A ROBUSTNESS METRIC FOR A CIRCUIT DESIGN - Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators. | 08-04-2011 |
20110191740 | ZONE-BASED OPTIMIZATION FRAMEWORK - Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation. | 08-04-2011 |
20110289464 | GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT - Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate. | 11-24-2011 |
20110302546 | METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION - Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of scenarios. The system can then determine a subset of scenarios based at least on the values of the constrained objects, so that if the circuit design meets design constraints in each scenario in the subset of scenarios, the circuit design is expected to meet the design constraints in each scenario in the set of scenarios. | 12-08-2011 |
20110302547 | METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW - Some embodiments of the present invention provide techniques and systems for using scenario reduction in a design flow. The system can use scenario reduction to determine two subsets of scenarios that correspond to two sets of design constraints. Next, the system can optimize the circuit design using one of the sets of design constraints over the associated subset of scenarios. Next, the system can optimize the circuit design using both sets of design constraints over the union of the two subsets of scenarios. In some embodiments, the system can iteratively optimize a circuit design by: performing multiple optimization iterations on the circuit design over progressively larger subsets of scenarios which are determined by performing scenario reduction with relaxation; and performing at least one optimization iteration on the circuit design over a subset of scenarios which is determined by performing scenario reduction without relaxation. | 12-08-2011 |
20120030641 | PERFORMING SCENARIO REDUCTION USING A DOMINANCE RELATION ON A SET OF CORNERS - Some embodiments of the present invention provide techniques and systems for performing scenario reduction using a dominance relation on a set of corners. During operation, the system can receive a design library which specifies gate characteristics at each corner in a set of corners. Next, the system can use the design library to determine a dominance relation on the set of corners for each gate type. The dominance relations can be stored with the design library. The system can then receive a set of scenarios over which a circuit design is to be optimized. Next, the system can determine a subset of the set of scenarios using one or more dominance relations on the set of corners. The system can then optimize the circuit design over the subset of the set of scenarios. | 02-02-2012 |
20120030642 | HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION - Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results. | 02-02-2012 |
20130145331 | SEQUENTIAL SIZING IN PHYSICAL SYNTHESIS - Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell. | 06-06-2013 |
20130145338 | MODELING TRANSITION EFFECTS FOR CIRCUIT OPTIMIZATION - Systems and techniques are described for determining a transition-effect model for a timing arc of a library cell. A transition-effect model can be determined for each library cell that is used during an optimization process. The transition-effect models enable an optimization system to estimate the impact of a change in the transition at an output of a driver gate on the delays of downstream gates without requiring to propagate the change in the transition to the downstream gates. Once determined, the transition-effect models can be used to compute one or more transition-induced penalties during circuit optimization. An optimization system can then use the one or more transition-induced penalties to determine whether or not to accept an optimizing transformation, or to discretize a solution obtained from a numerical solver. | 06-06-2013 |
20130145339 | EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION - Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order. | 06-06-2013 |
20130283222 | NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL AND/OR A TECHNOLOGY LIBRARY CELL TYPE - Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches. | 10-24-2013 |
20130318488 | EXCLUDING LIBRARY CELLS FOR DELAY OPTIMIZATION IN NUMERICAL SYNTHESIS - Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively. | 11-28-2013 |
20130326449 | INCREMENTAL ELMORE DELAY CALCULATION - Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner. | 12-05-2013 |
20140007037 | ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS | 01-02-2014 |
20140033161 | ACCURATE APPROXIMATION OF THE OBJECTIVE FUNCTION FOR SOLVING THE GATE-SIZING PROBLEM USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function. | 01-30-2014 |
20140033162 | DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver. | 01-30-2014 |
20140033163 | MODELING GATE SIZE RANGE IN A NUMERICAL GATE SIZING FRAMEWORK - Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function (which includes the penalty function) can be computed to enable the use of a conjugate-gradient-based numerical solver. | 01-30-2014 |
20140040851 | OPTIMIZING A CIRCUIT DESIGN FOR DELAY USING LOAD-AND-SLEW-INDEPENDENT NUMERICAL DELAY MODELS - Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations. | 02-06-2014 |
20140223400 | NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL TYPE - Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches. | 08-07-2014 |
20150039664 | SOLVING A GATE-SIZING OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER - Systems and techniques are described for solving a gate-sizing optimization problem using a constraints solver. Some embodiments can create a constraints problem based on a gate-sizing optimization problem for a portion of a circuit design. Specifically, the constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. Next, the embodiments can solve the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver. | 02-05-2015 |
20150040089 | NUMERICAL AREA RECOVERY - Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design. | 02-05-2015 |
20150040090 | DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS - Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized. | 02-05-2015 |
20150040093 | ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER - Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization. | 02-05-2015 |
20150040107 | SOLVING AN OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER - Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem. | 02-05-2015 |
Patent application number | Description | Published |
20110239241 | CASSETTE WITH DISK EJECT MECHANISM - An optical disk cassette has a disk eject mechanism that ejects a disk such as a DVD or CD. The disk eject mechanism has pushrod, transfer and kick out portions. The pushrod portion slides relative to a side of the cassette case. Pivotally mounted within the case, the kick out portion pushes a disk to eject it from the case. The transfer portion translates pushrod motion to motion of the kick out portion. In a preferred embodiment, the disk eject mechanism is a unitary body, with pushrod, transfer and kick out portions made homogeneously as a single entity, the pushrod portion being a resilient joining elbow. In another preferred embodiment, the disk eject mechanism has a transfer portion that is a rack and a pinion. The rack extends from the pushrod portion and the pinion is attached to or formed as part of the kick out portion. | 09-29-2011 |
20110258645 | OPTICAL DISK MECHANISM WITH SHAPED ROLLER AND DOUBLE BEAM MOUNT - An optical disk mechanism has a housing with at least one disk entry/exit aperture. A disk guide, such as a plate, is aligned with and guides an optical disk through the disk entry/exit aperture. Two beams rotatably support at least one roller and a drive mechanism. Flexing and biasing the roller towards the disk, the two beams maintain a rotational axis of the roller parallel to the disk and accommodate varying separation between the roller and the disk guide. The two beams are closely spaced and non-coplanar, and may be part of a double-beam mount. The double-beam mount attaches the two beams to the housing and to a frame, which positions the roller near the disk guide and the disk entry/exit aperture. Sliding the disk along the plate or other disk guide, the roller is reversible to drive the disk in or out through the disk entry/exit aperture. | 10-20-2011 |
20110315577 | OPTICAL DISK CASSETTE WITH DISK RETENTION DEVICE - An optical disk cassette has a cassette case with a disk retention device. A free end of the disk retention device acts upon an edge of the optical disk, opposably displacing during insertion and ejection of the optical disk. The device and disk are at equilibrium when the free end is displaced by the full diameter of the disk. When the disk is displaced in the insertion or ejection direction, the free end urges the disk in the insertion or ejection direction, assisting with the optical disk insertion or ejection respectively. Embodiments may have the disk retention device including one or more retainers. Each retainer may have a free end and opposing fixed end, and be flexible or have a flexible region. The free end slides along or otherwise contacts the circumferential edge of the optical disk, exerting a force upon it during optical disk insertion, retention and ejection. | 12-29-2011 |
20120117578 | OPTICAL DISC LIBRARY SYSTEM AND METHODS - A system for optical disc storage, writing and reading including a housing holding at least two optical disc racks and a plurality of read/write drives that may be positioned in line with the storage rack. A track spans the racks, (e.g., a parallel track is positioned between two racks). A shuttle mounted on the track allows transfer of discs from the racks to drives. The shuttle may allow for disc pass through, disc rotation, or have other structures for disc transport. | 05-10-2012 |