Amer
Abdelgelil Amer, Saratoga Springs, NY US
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20100194518 | CAST-COIL INDUCTOR - An inductor device is described. The inductor device includes a core comprising two core sections, at least one gap defined between the two core sections, and at least one cast coil and fringe shield assembly. The at least one cast coil and fringe shield assembly includes a conductor winding and a fringe shield sealed within an insulator. The at least one cast coil and fringe shield assembly is configured to at least partially surround portions of the two core sections. | 08-05-2010 |
Ahmed Amer, College Station, TX US
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20120212199 | Low Drop Out Voltage Regulator - A low dropout voltage regulator (LDO) is presented that takes into consideration short channel effects of the pass transistor in suppressing ripples that are present at the input node of the LDO from appearing at the output node of the LDO. A sum of the input ripple voltage and the input ripple voltage multiplied by a gain equal to the reciprocal of the intrinsic gain provided by the pass transistor is fed to the gate of the pass transistor. In one embodiment an adaptive stage is utilized to provide the sum to the gate of the pass transistor. The adaptive stage gain adapts to change changing load currents such that the gate voltage is maintained substantially equal to the sum. In another embodiment, the LDO is provided stability by using only on-chip capacitors. The LDO provides stable operation even at small load currents. | 08-23-2012 |
20120212200 | Low Drop Out Voltage Regulator - A low dropout voltage regulator (LDO) is presented that takes into consideration short channel effects of the pass transistor in suppressing ripples that are present at the input node of the LDO from appearing at the output node of the LDO. The LDO feeds the input ripple voltage to the gate of the pass transistor in such a way that the ripple currents through the pass transistor associated with both the transconductance and the output resistance of the pass transistor are suppressed. In one embodiment, the LDO is provided stability by using only on-chip capacitors. The size of on-chip capacitors is advantageously reduced by connecting a compensation capacitance to an internal node of an error amplifier. The LDO provides stable operation even at small load currents. The LDO also provides good suppression of ripples for a wide range of frequencies. | 08-23-2012 |
Ahmed Amer, Santa Clara, CA US
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20160132722 | Self-Configuring and Self-Adjusting Distributed Surveillance System - Improved facial recognition tracking of individuals throughout a space is provided, as is identification of unexpected behavior. The system can configure itself upon setup and adjust to changing conditions, and is able to intelligently reduce the workload on the facial recognition system. Cameras are placed throughout a building and learn what typical traffic within the building looks like. Over time, the system can track multiple users throughout the system and can automatically learn the average time between cameras. A probability function for each camera can also be determined that give probabilities for each camera to camera path. This approach provides for both limiting the bandwidth and processing power required for facial recognition and also allows for behavioral analysis. This system could be implemented as a distributed system of cameras, each performing its own facial recognition and tracking, and/or with distributed cameras combined with central processing for facial recognition. | 05-12-2016 |
Aishy Amer, St-Laurent CA
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20130128123 | METHOD FOR REDUCING IMAGE OR VIDEO NOISE - There is described a Minimal Iterativity Anisotropic Diffusion (MIAD) approach that estimates the required number of iterations N as a function of the image structure-under-noise ρ and the bound of the noise η. The time step λ is related to the image structure-under-noise ρ and to the bound of noise λ. The stopping time is calculated using T=λ·N, and the edge strength σ is determined as a function of T, η, and ρ. | 05-23-2013 |
Ame M. Amer, Newmarket CA
Ayman Amer, Thuwal SA
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20150153312 | Modular Mobile Inspection Vehicle - A modular inspection vehicle having at least first and second motion modules is provided. The first and second motion modules are connected to a chassis. The first motion module includes a first wheel mounted to the chassis. The second motion module includes second wheel mounted to the chassis, the second wheel being at an angle to the first wheel. The vehicle further includes a navigation module configured to collect position data related to the position of the vehicle, an inspection module configured to collect inspection data related to the vehicle's environment, and a communication module configured to transmit and receive data. The vehicle can also include a control module configured to receive the inspection data and associate the inspection data with received position data that corresponds to the inspection data collect at a corresponding position for transmission via the communication module. | 06-04-2015 |
Ihab Amer, Stouffville CA
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20150092856 | Exploiting Camera Depth Information for Video Encoding - The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. The method and system of the present disclosure can be further used in other applications where camera and depth information of a rendered or captured video frame is available. | 04-02-2015 |
Ihab M.a. Amer, Stouffville CA
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20160037166 | ADAPTIVE SEARCH WINDOW POSITIONING FOR VIDEO ENCODING - A method, system, and computer program product that exploits motion hints associated with rendered video frames. These motion hints are provided to a video encoder to guide a motion-compensation prediction process performed by the video encoder. Specifically, these motion hints can be used to better position a search window in a reference video frame to better capture the motion of a block of pixels in the reference video frame. Because the search window is better positioned in the reference video frame, the memory required to perform the encoding process can be reduced without sacrificing the level of encoded image quality. | 02-04-2016 |
20160119619 | METHOD AND APPARATUS FOR ENCODING INSTANTANEOUS DECODER REFRESH UNITS - Method and apparatus for encoding instantaneous decoder refresh (IDR) units are disclosed. The method includes partially encoding an IDR block as a non-IDR block, decoding the partially encoded IDF block to generate a reconstructed IDR block and fully encoding the reconstructed IDF block as an IDR block. In a first pass, an IDR unit is partially encoded (no entropy encoding) using regular encoding parameters of a non-IDR unit in the same picture. The partially-encoded IDR unit is then inverse quantized and inverse transformed to generate a reconstructed video data of the IDR unit. In the second pass, the reconstructed video data of the IDR unit is passed as an input to the prediction module and fully encoded using the IDR settings. The reconstructed IDR unit may be encoded with very high fidelity. | 04-28-2016 |
20160134865 | CONTROLLING POWER CONSUMPTION IN VIDEO ENCODING BASED ON INFORMATION REGARDING STATIC AMOUNT OF AN IMAGE FRAME - An apparatus and methods for controlling power consumption in video encoding obtain, before motion estimation is performed on an image frame to be encoded, information regarding an amount of the image frame to be encoded that is static with respect to a previously encoded image frame. The apparatus and methods adjust power consumption of the video encoder based on the obtained information regarding the amount of the image frame to be encoded that is static. | 05-12-2016 |
Jack Amer, Cerritos, CA US
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20150152648 | Toilet Flange Template Apparatus - A toilet flange template apparatus comprising a first arm having a first head and a first connecting member extending therefrom, the first head defining a first perimeter edge substantially corresponding to and providing circumferential clearance relative to a toilet flange, and a second arm having a second head and a second connecting member extending therefrom, the second arm being pivotally connected to the first arm, the second head formed having a substantially downwardly-extending second center boss configured to be received within the toilet flange. | 06-04-2015 |
20150152649 | TOILET FLANGE TEMPLATE APPARATUS - A method and apparatus can include: a toilet flange template apparatus comprising: a first arm having a first head and a first connecting member extending therefrom, the first head formed with a first centered boss extending therefrom; and a second arm having a second head and a second connecting member extending therefrom, the second arm being pivotally connected to the first arm, and the second arm configured to be parallel to the first arm when a tile is placed therebetween, the second head defining a perimeter edge corresponding to and providing circumferential clearance for an outer circumference of a toilet flange that the first centered boss is configured to mate with. | 06-04-2015 |
Louis J. Amer, Chesterland, OH US
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20160015591 | OVERHEAD STANDING AND AMBULATION ASSISTIVE EXERCISE DEVICE - An exercise apparatus adapted to hang from an overhead structure used for providing walking and ambulation assistance to users in aid of exercise and physical rehabilitation. The device has a pulley assembly adapted for anchoring directly to an overhead structure or indirectly by a track secured thereto, and includes a hoist line permitting manual force to be used to raise and lower a sling assembly that is secured in the underarms of the user for lifting. | 01-21-2016 |
Maher Amer, Napean CA
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20160041917 | SYSTEM AND METHOD FOR MIRRORING A VOLATILE MEMORY OF A COMPUTER SYSTEM - A system and method for mirroring a volatile memory to a CPIO device of a computer system is disclosed. According to one embodiment, a command buffer and a data buffer are provided to store data and a command for mirroring the data. The command specifies metadata associated with the data. The data is mirrored a non-volatile memory of the CPIO device based on the command. | 02-11-2016 |
20160041933 | SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM - A method of implementing a multi-threaded device driver for a computer system is disclosed. According to one embodiment, a polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread. | 02-11-2016 |
Maher Amer, Nepean CA
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20100070690 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM. | 03-18-2010 |
20120204079 | SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 08-09-2012 |
20130238849 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual inline memory module (RDIMM) in which control signals are synchronusly buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM. | 09-12-2013 |
20140223262 | System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 08-07-2014 |
20140237157 | SYSTEM AND METHOD FOR PROVIDING AN ADDRESS CACHE FOR MEMORY MAP LEARNING - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width. | 08-21-2014 |
20140237176 | SYSTEM AND METHOD FOR UNLOCKING ADDITIONAL FUNCTIONS OF A MODULE - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode. The maze unlock sequence involves writing a first data pattern of a plurality of data patterns to a memory address of the memory device, reading a first set of data from the memory address, and storing the first set of data in a validated data array. The maze unlock sequence further involves writing a second data pattern of the plurality of data patterns to the memory address, reading a second set of data from the memory address, and storing the second set of data in the validated data array. A difference vector array is generated from the validate data array and an address map of the memory device is identified based on the difference vector array. | 08-21-2014 |
20140237205 | SYSTEM AND METHOD FOR PROVIDING A COMMAND BUFFER IN A MEMORY SYSTEM - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system is configured to receive a command from a host memory controller of a host system and store the command in a command buffer entry. The system determines that the command is complete using a buffer check logic and provides the command to a command buffer. The command buffer comprises a first field that specifies an entry point of the command within the command buffer entry. | 08-21-2014 |
20140244924 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM). | 08-28-2014 |
20150227324 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM. | 08-13-2015 |
20150294698 | System and Method for Offsetting The Data Buffer Latency of a Device Implementing a JEDEC Standard DDR-4 LRDIMM Chipset - A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM. | 10-15-2015 |
20150309959 | System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 10-29-2015 |
20150310898 | SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM - A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface. | 10-29-2015 |
20150324281 | SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COMPUTER MAIN MEMORY SYSTEM - A system and method for implementing an object storage device is disclosed. According to one embodiment, the system includes a first controller configured to interface with a main memory controller of a computer system to receive a data object and a first request for storing the data object, the first request including a key value. The system also includes a second controller configured to: allocate memory in one or more non-volatile memory storage units for storing the data object, store the data object in the allocated memory, and maintain an association between the key value and allocated memory. | 11-12-2015 |
20150326684 | SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/OR INPUT/OUTPUT DEVICE VIA REMOTE DIRECT MEMORY ACCESS - A method of controlling a remote computer device of a remote computer system over a remote direct memory access (RDMA) is disclosed. According to one embodiment, the method includes establishing a connection for remote direct memory access (RDMA) between a local memory device of a local computer system and a remote memory device of a remote computer system. A local command is sent from a local application that is running on the local computer system to the remote memory device of the remote computer system via the RDMA. The remote computer system executes the local command on the remote computer device. | 11-12-2015 |
20150347151 | SYSTEM AND METHOD FOR BOOTING FROM A NON-VOLATILE MEMORY - A method of booting a computer system using a non-volatile memory of a memory module of the computer system is disclosed. According to one embodiment, a memory controller driver of a memory module of the computer system is stored in a non-volatile memory of the memory module. A memory controller of the memory module has a register that is set to indicate a location of the memory controller driver in the non-volatile memory of the memory module. The memory controller determines the location of the memory controller driver of the memory module using the register. The memory controller driver is transferred from the non-volatile memory to a buffer of the memory controller and subsequently from the buffer of the memory controller to a main memory of the computer system. The computer system initializes the memory module using the memory controller driver. | 12-03-2015 |
Mohamed R. Amer, New York, NY US
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20160071024 | DYNAMIC HYBRID MODELS FOR MULTIMODAL ANALYSIS - Technologies for analyzing temporal components of multimodal data to detect short-term multimodal events, determine relationships between short-term multimodal events, and recognize long-term multimodal events, using a deep learning architecture, are disclosed. | 03-10-2016 |
Moh Samir Amer, Carpinteria, CA US
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20120046318 | METHODS AND COMPOSITIONS FOR TREATING INTERNAL AND EXTERNAL HEMORRHOIDS - The present invention relates to compositions and methods for treatment of internal and/or external hemorrhoids, wherein the treatment includes topically administering to a subject a composition comprising from 0.3% to 0.7% of S-2′-[2-(1-methyl-2-piperidyl)ethyl]cinnamanilide, wherein the S-2′-[2-(1-methyl-2-piperidyl)ethyl]cinnamanilide not only treats the hemorrhoidal symptoms but delays or inhibits the recurrence of hemorrhoids and/or symptoms thereof. | 02-23-2012 |
Moh. Samir Amer, Montecito, CA US
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20100099707 | METHOD FOR TREATING PULMONARY ARTERIAL HYPERTENSION - Pulmonary arterial hypertension in a mammal can be prevented or treated using combined 5-HT2A and 5-HT2B receptor antagonist. The antagonists can be present in a single compound or in two separate compounds | 04-22-2010 |
Peter Robin Amer, Dunedin NZ
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20110184652 | METHODS OF GENERATING GENETIC PREDICTORS EMPLOYING DNA MARKERS AND QUANTITATIVE TRAIT DATA - A genetic trait predictor is generated by blending individual molecular estimates with estimates of at least one genetic value derived from quantitative trait measure. The individual molecular estimates may include molecular trait estimates or molecular trait variance. The individual molecular estimates may be determined by applying individual deoxyribonucleic acid (DNA) markers, DNA marker panels, specific parameter estimates and specific parameter variance thereof, and a genotype of a test sample. Quantitative trait measure may include estimated breeding data, raw trait data, and breed composition data. The genetic predictor is accurate and stable under a wide range of conditions and relatively immune to errors in parameter estimation. | 07-28-2011 |
Sami Abdulkarem Amer, Dhahran SA
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20140332217 | PORTLAND SAUDI CEMENT TYPE-G WITH NANOSILICA ADDITIVE FOR HIGH PRESSURE-HIGH TEMPERATURE APPLICATIONS - The Portland Saudi cement type-G with nanosilica additive for high pressure-high temperature applications comprises a mixture of about 1.0%-2.0% by dry weight of nanoparticles of silica; and type-G Portland Saudi cement forming the balance of the mixture. The cement so formed is suitable for use in deep petroleum wells, which require cement that can be introduced under high temperature (about 290° F.) and high pressure (about 8,000-9,000 psi) conditions. The addition of nanosilica shortened the thickening time for the cement slurry and caused a growth in the average compressive strength of the cement samples. In addition, the nanosilica did not cause any free water separation from the cement slurry column after aging. | 11-13-2014 |
20150260009 | PORTLAND CEMENT TYPE-G WITH NANOSILICA ADDITIVE FOR HIGH PRESSURE-HIGH TEMPERATURE APPLICATIONS - The Portland cement type-G with nanosilica additive for high pressure-high temperature applications is a mixture of about 1.0%-2.0% by dry weight of nanoparticles of hydrophilic silica, with type-G Portland cement (and other admixtures) forming the balance of the mixture. The cement so formed is suitable for use in deep petroleum wells, which require cement that can be introduced under high temperature (about 290° F.) and high pressure (about 8,000-9,000 PSI) conditions. The addition of hydrophilic nanosilica shortens the thickening time for the cement slurry and causes a growth in the average compressive strength of the cement. In addition, the hydrophilic nanosilica does not cause any free water separation from the cement slurry column after aging. | 09-17-2015 |
Waseem Amer, Islamabad PK
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20160072638 | SYSTEM AND METHOD FOR REMOTELY CONTROLLING IR-ENABLED APPLIANCES VIA NETWORKED DEVICE - Systems and methods for remotely controlling infrared (“IR”) enabled appliances via a networked device are described. The technology enables one or multiple users to control, monitor, and manage their appliances (e.g., air conditioners, television sets, multimedia systems, window curtains, etc.) both locally and remotely, irrespective of the users' location or their line of sight. In various embodiments, the technology includes a device with integrated Wi-Fi and IR subsystems connected via a cloud platform to a user application interface that can control appliances, generate analytics, schedule automatic operation, and perform smart learning operation. | 03-10-2016 |