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| 20150351648 | METHODS AND SYSTEMS RELATING TO BIOLOGICAL SYSTEMS WITH EMBEDDED MEMS SENSORS - Small implantable silicon-based devices offer an ability to revolutionize the management of trauma victims. For example, implantable pressure sensors allow the devastating outcomes of compartment syndrome to be minimized through continuous or periodic monitoring whilst being compatible with the ongoing drives to increase out-patient care and reduced hospitalization time. Further, small implantable silicon-based sensor microsystems according to embodiments of the invention whilst being capable of measuring pressures under diverse conditions are easily used by nurses in hospital settings as well as also being easily deployed by paramedical personnel in cases of accidents, natural disasters, war, etc. Beneficially, the implantable sensor microsystem will not interfere with movement of the patient during stabilization, surgery, intensive care stay, outpatient management, etc. | 12-10-2015 |
| 20160002026 | METHODS AND DEVICES FOR MICROELECTROMECHANICAL PRESSURE SENSORS - MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics. | 01-07-2016 |
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| 20100020797 | METHOD AND APPARATUS FOR EXCHANGING ROUTING INFORMATION AND ESTABLISHING CONNECTIVITY ACROSS MULTIPLE NETWORK AREAS - A method ensures that multicast packets follow the same loop-free path followed by unicast packets in a packet communication network. The communication network includes at least one first area interconnected through at least one area border node (“ABN”) to a second area. Each ABN has a first level port connected to each first area and a second level port connected to the second area. Each multicast packet forwarded includes a header having a root-id identifying a root of a multicast tree. A data packet is received at an ABN. Responsive to receiving a multicast packet at a second level port of an area border node, the root-id of the multicast packet is examined and if the multicast packet is to be forwarded over at least one of the first level ports, a different root-id is substituted into the packet before the packet is forwarded over the first level port. | 01-28-2010 |
| 20120057466 | Automated Traffic Engineering for Multi-Protocol Label Switching (MPLS) with Link Utilization as Feedbank into the Tie-Breaking Mechanism - A method implemented in a node of a multi-protocol label switching (MPLS) network for improved load distribution, including determining a first set of one or more shortest paths between each MPLS node pair, selecting at least a first shortest path by applying the common algorithm tie-breaking process, calculating a link utilization value for each link of the MPLS network, determining a second set of one or more shortest paths between each MPLS node pair, generating a path utilization value for each shortest path in the second set of shortest paths based on link utilization values corresponding to each shortest path, and selecting a second shortest path from the second set of shortest paths on the basis of said path utilization value, whereby the selection of the second subsets in light of path utilization minimizes the standard deviation of load distribution across the entire MPLS network. | 03-08-2012 |
| 20120057603 | Automated Traffic Engineering for 802.1AQ Based Upon the Use of Link Utilization as Feedback into the Tie Breaking Mechanism - A method in an Ethernet Bridge for improved load distribution in an Ethernet network that includes the Ethernet Bridge including determining a first set of one or more shortest paths between each Ethernet Bridge pair in the Ethernet network, selecting at least a first shortest path, calculating a link utilization value for each link of the Ethernet network, determining a second set of one or more shortest paths between each Ethernet Bridge pair in the Ethernet network, generating a path utilization value for each shortest path, selecting a second shortest path on the basis of said path utilization value, whereby the selection of the second shortest in light of path utilization minimizes the standard deviation of load distribution across the entire Ethernet network. | 03-08-2012 |
| 20120300774 | METHOD AND APPARATUS FOR EXCHANGING ROUTING INFORMATION AND ESTABLISHING CONNECTIVITY ACROSS MULTIPLE NETWORK AREAS - A method ensures that multicast packets follow the same loop-free path followed by unicast packets in a packet communication network. The communication network includes at least one first area interconnected through at least one area border node (“ABN”) to a second area. Each ABN has a first level port connected to each first area and a second level port connected to the second area. Each multicast packet forwarded includes a header having a root-id identifying a root of a multicast tree. A data packet is received at an ABN. Responsive to receiving a multicast packet at a second level port of an area border node, the root-id of the multicast packet is examined and if the multicast packet is to be forwarded over at least one of the first level ports, a different root-id is substituted into the packet before the packet is forwarded over the first level port. | 11-29-2012 |
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| 20150222273 | APPARATUS AND METHODS FOR PHASE-LOCKED LOOPS WITH SOFT TRANSITION FROM HOLDOVER TO REACQUIRING PHASE LOCK - Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock. | 08-06-2015 |
| 20150222274 | SYSTEM READY IN A CLOCK DISTRIBUTION CHIP - Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready. | 08-06-2015 |
| 20150222280 | APPARATUS AND METHODS FOR FAST CHARGE PUMP HOLDOVER ON SIGNAL INTERRUPTION - Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range. | 08-06-2015 |
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| 20090039927 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 02-12-2009 |
| 20090316514 | Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 12-24-2009 |
| 20110095796 | PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME - A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line. | 04-28-2011 |
| 20110110165 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 05-12-2011 |
| 20130121096 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 05-16-2013 |
| 20130235659 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 09-12-2013 |
| 20140104969 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 04-17-2014 |
| 20140133243 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 05-15-2014 |
| 20150255167 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 09-10-2015 |
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| 20090252148 | Use of DPI to extract and forward application characteristics - Various exemplary embodiments are a method and related device and computer-readable medium including one or more of the following: receiving a packet sent from the source node to the destination node; associating the packet with an active flow by accessing information in the packet; performing deep packet inspection (DPI) to identify an application associated with the active flow; determining a classification for the packet based on characteristics of the identified application; associating, with the packet, information identifying the classification; forwarding the packet including the information identifying the classification towards the destination node; and performing processing on the packet at a downstream device by extracting the classification from the packet. | 10-08-2009 |
| 20100054204 | SYSTEM AND METHOD OF SERVING GATEWAY HAVING MOBILE PACKET PROTOCOL APPLICATION-AWARE PACKET MANAGEMENT - Mobile protocol packets, with a header field and a payload field, are communicated from a user mobile equipment to an application-aware serving gateway. The application-aware mobile protocol serving gateway detects header information in the header field and application information in the payload field to manage the mobile protocol packets based on a policy. | 03-04-2010 |
| 20100067400 | APPLICATION-LEVEL PROCESSING FOR DEFAULT LTE BEARER IN S-GW - A serving gateway facing a radio access network receives packets, applies deep packet inspect to classify the packet into a predetermined application class, and inserts a marker identifying the class and a QoS associated with the class. The serving gateway assigns the packets to a queue within a default bearer based on the class and the QoS marker. The serving gateway transfers packets through the bearer by processing the queues in accordance with their priority. | 03-18-2010 |
| 20130142123 | System and Method of Serving Gateway Having Mobile Packet Protocol Application-Aware Packet Management - Mobile protocol packets, with a header field and a payload field, are communicated from a user mobile equipment to an application-aware serving gateway. The application-aware mobile protocol serving gateway detects header information in the header field and application information in the payload field to manage the mobile protocol packets based on a policy. | 06-06-2013 |
