Patent application number | Description | Published |
20110254080 | TUNNEL FIELD EFFECT TRANSISTOR - A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack. | 10-20-2011 |
20110263104 | THIN BODY SEMICONDUCTOR DEVICES - A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented. | 10-27-2011 |
20110272762 | EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR - A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region. | 11-10-2011 |
20110284967 | Stressed Fin-FET Devices with Low Contact Resistance - A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 11-24-2011 |
20110303915 | Compressively Stressed FET Device Structures - Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 12-15-2011 |
20110309333 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 12-22-2011 |
20110309446 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 12-22-2011 |
20110316083 | FET with Self-Aligned Back Gate - A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region. | 12-29-2011 |
20120012933 | FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE - A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space. | 01-19-2012 |
20120025282 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-02-2012 |
20120032267 | DEVICE AND METHOD FOR UNIFORM STI RECESS - A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted to a depth in the dielectric material to change an etch rate of the dielectric material down to the depth. The dielectric material having the ion species is etched selective to the dielectric material below the depth such that a substantially uniform depth in the dielectric material is created across the at least two spacings. | 02-09-2012 |
20120040522 | METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS - A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology. | 02-16-2012 |
20120043610 | Controlled Fin-Merging for Fin Type FET Devices - A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins to one another. Next, the continuous fins are cut into segments. The fabricated FET devices are characterized as being non-planar devices. A placement of non-planar FET devices is also disclosed, which includes non- planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures. | 02-23-2012 |
20120043623 | METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. | 02-23-2012 |
20120080802 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 04-05-2012 |
20120112207 | METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer. | 05-10-2012 |
20120153397 | Stressed Fin-FET Devices with Low Contact Resistance - An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 06-21-2012 |
20120187493 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME - An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided. | 07-26-2012 |
20120193713 | FinFET device having reduce capacitance, access resistance, and contact resistance - A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers. | 08-02-2012 |
20120217561 | Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors - A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. | 08-30-2012 |
20120241902 | SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 09-27-2012 |
20120256238 | Junction Field Effect Transistor With An Epitaxially Grown Gate Structure - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 10-11-2012 |
20120256260 | DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE - Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks. | 10-11-2012 |
20120261757 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 10-18-2012 |
20120267722 | Compressively Stressed FET Device Structures - An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 10-25-2012 |
20120280290 | LOCAL INTERCONNECT STRUCTURE SELF-ALIGNED TO GATE STRUCTURE - A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other. | 11-08-2012 |
20120286350 | TUNNEL FIELD EFFECT TRANSISTOR - An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side. | 11-15-2012 |
20120299075 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120302020 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120319232 | Self-Aligned Dual Depth Isolation and Method of Fabrication - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 12-20-2012 |
20120329232 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 12-27-2012 |
20130043520 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-21-2013 |
20130069171 | Controlled Fin-Merging for Fin Type FET Devices - A placement of non-planar FET devices is disclosed, which includes non-planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures. | 03-21-2013 |
20130105818 | MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION | 05-02-2013 |
20130127067 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 05-23-2013 |
20130143371 | DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE - Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks. | 06-06-2013 |
20130153929 | METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. | 06-20-2013 |
20130157423 | MOSFETs WITH REDUCED CONTACT RESISTANCE - A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy. | 06-20-2013 |
20130161693 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20130161694 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20130161706 | JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 06-27-2013 |
20130187129 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 07-25-2013 |
20130200433 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 08-08-2013 |
20130200459 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 08-08-2013 |
20130230949 | EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR - A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region. | 09-05-2013 |
20130270560 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING - A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices. | 10-17-2013 |
20130270561 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING - A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices. | 10-17-2013 |
20130299897 | INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN - After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer. | 11-14-2013 |
20130299902 | FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE - A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space. | 11-14-2013 |
20130302950 | INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN - After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer. | 11-14-2013 |
20130302962 | MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION - A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage. | 11-14-2013 |
20130313643 | Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130316503 | STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130330887 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 12-12-2013 |
20140049315 | Inversion Mode Varactor - In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer. | 02-20-2014 |
20140061820 | BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height. | 03-06-2014 |
20140070333 | SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS - A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor. | 03-13-2014 |
20140091281 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 04-03-2014 |
20140117422 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 05-01-2014 |
20140124840 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 05-08-2014 |
20140124862 | STRUCTURE AND METHOD TO IMPROVE ETSOI MOSFETS WITH BACK GATE - A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole. | 05-08-2014 |
20140145246 | JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 05-29-2014 |
20140145263 | Finfet Semiconductor Device Having Increased Gate Height Control - A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region. | 05-29-2014 |
20140346612 | BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES - A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices. | 11-27-2014 |
20150179548 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 06-25-2015 |
Patent application number | Description | Published |
20120061759 | Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same - A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided. | 03-15-2012 |
20120068264 | FORMING NARROW FINS FOR FINFET DEVICES USING ASYMMETRICALLY SPACED MANDRELS - A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers. | 03-22-2012 |
20120068267 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 03-22-2012 |
20120074494 | STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE - A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress. | 03-29-2012 |
20120210932 | LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION - An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000. | 08-23-2012 |
20120216158 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 08-23-2012 |
20120235239 | HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined. | 09-20-2012 |
20120261754 | MOSFET with Recessed channel FILM and Abrupt Junctions - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 10-18-2012 |
20120261792 | SOI DEVICE WITH DTI AND STI - An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer. | 10-18-2012 |
20120276695 | Strained thin body CMOS with Si:C and SiGe stressor - A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement. | 11-01-2012 |
20120286329 | SOI FET with embedded stressor block - A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body. | 11-15-2012 |
20120286364 | Integrated Circuit Diode - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 11-15-2012 |
20120292700 | Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same - An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric. | 11-22-2012 |
20120292705 | SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES - A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively. | 11-22-2012 |
20120302019 | NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure. | 11-29-2012 |
20120313143 | HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction. | 12-13-2012 |
20120313168 | FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION - An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer. | 12-13-2012 |
20120326230 | SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE - A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions. | 12-27-2012 |
20120326232 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 12-27-2012 |
20130015534 | THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHSAANM Cheng; KangguoAACI SchenectadyAAST NYAACO USAAGP Cheng; Kangguo Schenectady NY USAANM Doris; Bruce B.AACI BrewsterAAST NYAACO USAAGP Doris; Bruce B. Brewster NY USAANM Khakifirooz; AliAACI Mountain ViewAAST CAAACO USAAGP Khakifirooz; Ali Mountain View CA USAANM Kulkarni; PranitaAACI SlingerlandsAAST NYAACO USAAGP Kulkarni; Pranita Slingerlands NY US - A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure. | 01-17-2013 |
20130062702 | CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device. | 03-14-2013 |
20130062704 | CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device. | 03-14-2013 |
20130069159 | Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack. | 03-21-2013 |
20130071979 | Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack. | 03-21-2013 |
20130075817 | JUNCTIONLESS TRANSISTOR - A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type. | 03-28-2013 |
20130078777 | METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR - A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type. | 03-28-2013 |
20130078781 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 03-28-2013 |
20130082306 | ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region. | 04-04-2013 |
20130082308 | SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate. | 04-04-2013 |
20130082311 | SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate. | 04-04-2013 |
20130082328 | ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region. | 04-04-2013 |
20130099318 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130099319 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130112275 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 05-09-2013 |
20130134546 | HIGH DENSITY MULTI-ELECTRODE ARRAY - A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes. | 05-30-2013 |
20130146952 | ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES - A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material. | 06-13-2013 |
20130146953 | Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts - An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch. | 06-13-2013 |
20130146959 | Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors - An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch. | 06-13-2013 |
20130175579 | TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer. | 07-11-2013 |
20130175596 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 07-11-2013 |
20130175606 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 07-11-2013 |
20130175661 | Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same - A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF | 07-11-2013 |
20130178021 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 07-11-2013 |
20130178022 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 07-11-2013 |
20130187205 | EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN - Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article. | 07-25-2013 |
20130187229 | SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME - A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions. | 07-25-2013 |
20130187253 | HIGH DENSITY MULTI-ELECTRODE ARRAY - A high density micro-electrode array includes a transistor layer including a plurality of access transistors and a substrate in operable communication with the transistor layer including, wherein at least a portion of the substrate includes a plurality of trenches. The system includes a plurality of electrodes at least partially located in the plurality of trenches, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein each of the electrodes is separated by a distance less than approximately one microns. | 07-25-2013 |
20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 08-01-2013 |
20130193515 | SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS - An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor. | 08-01-2013 |
20130207189 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 08-15-2013 |
20130207226 | RECESSED DEVICE REGION IN EPITAXIAL INSULATING LAYER - A method for isolating semiconductor devices is described wherein an epitaxial insulating layer is grown on a semiconductor substrate. The epitaxial insulating layer is etched to form a recessed region within the layer. An epitaxial semiconductor material is grown with the recessed region to form a semiconductor device region separated from other potential device regions by non-recessed portions of the epitaxial insulating layer. | 08-15-2013 |
20130214356 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 08-22-2013 |
20130240998 | INTEGRATED CIRCUIT DIODE - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 09-19-2013 |
20130249006 | SELECTIVELY RAISED SOURCE/DRAIN TRANSISTOR - A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted. | 09-26-2013 |
20130270611 | SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS - A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron. | 10-17-2013 |
20130270627 | FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION - A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer. | 10-17-2013 |
20130270655 | SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures. | 10-17-2013 |
20130285123 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 10-31-2013 |
20130285152 | FINFET WITH ENHANCED EMBEDDED STRESSOR - A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region. | 10-31-2013 |
20130288451 | SOI DEVICE WITH DTI AND STI - A method of forming an SOI structure which includes providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate; patterning the SOI layer to form first and second openings in the SOI layer; extending the first openings into the bottom substrate; enlarging the first openings within the bottom substrate; filling the first and second openings with an insulator material to form deep trench isolations (DTIs) from the first openings and shallow trench isolations (STIs) from the second openings; implanting in the bottom substrate between the DTIs to form wells; and forming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI. | 10-31-2013 |
20130299889 | ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES - A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material. | 11-14-2013 |
20130299906 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer. | 11-14-2013 |
20130302949 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric. | 11-14-2013 |
20130307074 | Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate - An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material. | 11-21-2013 |
20130307078 | SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE - A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions. | 11-21-2013 |
20130313651 | INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES - An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer. | 11-28-2013 |
20130337621 | NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure. | 12-19-2013 |
20130337637 | STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) - A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer. | 12-19-2013 |
20130341754 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 12-26-2013 |
20130341770 | RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME - An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact. | 12-26-2013 |
20130344677 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 12-26-2013 |
20140000687 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
20140001554 | SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE | 01-02-2014 |
20140001561 | CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE | 01-02-2014 |
20140004654 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
20140008729 | STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR - A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. | 01-09-2014 |
20140015014 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 01-16-2014 |
20140017859 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 01-16-2014 |
20140024215 | DOUBLE PATTERNING METHOD - Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate. | 01-23-2014 |
20140035010 | INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region. | 02-06-2014 |
20140038369 | METHOD OF FORMING FIN-FIELD EFFECT TRANSISTOR (finFET) STRUCTURE - Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins. | 02-06-2014 |
20140042502 | SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND LOW-K SPACERS - One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride. | 02-13-2014 |
20140042521 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 02-13-2014 |
20140042542 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 02-13-2014 |
20140042543 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 02-13-2014 |
20140048804 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140051190 | METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION - Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce. | 02-20-2014 |
20140051247 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140070332 | SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures. | 03-13-2014 |
20140077274 | INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME - Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess. | 03-20-2014 |
20140097467 | COMPRESSIVELY STRAINED SOI SUBSTRATE - A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer. | 04-10-2014 |
20140099776 | COMPRESSIVELY STRAINED SOI SUBSTRATE - A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer. | 04-10-2014 |
20140103331 | Embedded Source/Drains with Epitaxial Oxide Underlayer - Semiconductor structures having embedded source/drains with oxide underlayers and methods for forming the same. Embodiments include semiconductor structures having a channel in a substrate, and a source/drain region adjacent to the channel including an embedded oxide region and an embedded semiconductor region located above the embedded oxide region. Embodiments further include methods of forming a transistor structure including forming a gate on a substrate, etching a source/drain recess in the substrate, filling a bottom portion of the source/drain recess with an oxide layer, and filling a portion of the source/drain recess not filled by the oxide layer with a semiconductor layer. | 04-17-2014 |
20140103436 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 04-17-2014 |
20140103485 | ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT - The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. | 04-17-2014 |
20140103533 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 04-17-2014 |
20140117368 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 05-01-2014 |
20140117462 | BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION - An improved bulk FinFET with a punchthrough stopper region, and method of fabrication are disclosed. The dopants used to form the punchthrough stopper are supplied from a shallow trench isolation liner. An anneal diffuses the dopants from the shallow trench isolation liner into the bulk substrate and lower portion of the fins, to form the punchthrough stopper region. | 05-01-2014 |
20140120666 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 05-01-2014 |
20140124845 | Method and Structure for Forming On-Chip High Quality Capacitors With ETSOI Transistors - An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch. | 05-08-2014 |
20140124860 | METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET - Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. | 05-08-2014 |
20140124863 | METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET - Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed. | 05-08-2014 |
20140131790 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 05-15-2014 |
20140131803 | ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES - An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions | 05-15-2014 |
20140134826 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 05-15-2014 |
20140138773 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 05-22-2014 |
20140138797 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 05-22-2014 |
20140141575 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 05-22-2014 |
20140145247 | FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS - A method for fabricating a field effect transistor (FET) device includes forming a plurality of semiconductor fins on a substrate, removing a semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, forming an isolation fin that includes a dielectric material on the substrate on the portion of the substrate, and forming a gate stack over the plurality of semiconductor fins and the isolation fin. | 05-29-2014 |
20140145248 | DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM - FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC). | 05-29-2014 |
20140145254 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 05-29-2014 |
20140145270 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 05-29-2014 |
20140145271 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 05-29-2014 |
20140151802 | Semiconductor Device Having SSOI Substrate - A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins. | 06-05-2014 |
20140151803 | Inducing Channel Stress in Semiconductor-on-Insulator Devices by Base Substrate Oxidation - Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region. | 06-05-2014 |
20140151806 | Semiconductor Device Having SSOI Substrate - A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins. | 06-05-2014 |
20140154865 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 06-05-2014 |
20140158187 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 06-12-2014 |
20140159124 | EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION - A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A dummy gate can establish the position of the abrupt interfaces and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel, or to overlap the extension tip. | 06-12-2014 |
20140159171 | METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER - One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin. | 06-12-2014 |
20140162452 | BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS - Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole. | 06-12-2014 |
20140167163 | Multi-Fin FinFETs with Epitaxially-Grown Merged Source/Drains - Embodiments include multi-fin finFET structures with epitaxially-grown merged source/drains and methods of forming the same. Embodiments may include an epitaxial insulator layer above a base substrate, a gate structure above the epitaxial insulator layer, a semiconductor fin below the gate structure, and an epitaxial source/drain region grown on the epitaxial insulator layer adjacent to an end of the semiconductor fin. The epitaxial insulator layer may be made of an epitaxial rare earth oxide material grown on a base semiconductor substrate. Embodiments may further include fin extension regions on the end of the semiconductor fin between the end of the end of the semiconductor fin and the epitaxial source/drain region. In some embodiments, the end of the semiconductor fin may be recessed below the gate structure. | 06-19-2014 |
20140167164 | DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices. | 06-19-2014 |
20140183687 | Integrated Circuit Having Back Gating, Improved Isolation and Reduced Well Resistance and Method to Fabricate Same - A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re- crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF | 07-03-2014 |
20140191286 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140191287 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140191296 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 07-10-2014 |
20140191324 | METHODS OF FORMING BULK FINFET DEVICES BY PERFORMING A RECESSING PROCESS ON LINER MATERIALS TO DEFINE DIFFERENT FIN HEIGHTS AND FINFET DEVICES WITH SUCH RECESSED LINER MATERIALS - One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin. | 07-10-2014 |
20140191330 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 07-10-2014 |
20140203332 | SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY - Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate. | 07-24-2014 |
20140203361 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR FIELD-EFFECT TRANSISTOR WITH AN EPITAXIAL SOURCE AND DRAIN HAVING A LOW EXTERNAL RESISTANCE - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer-on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140203363 | Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140206181 | THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS - A method of manufacturing a three dimensional FET device structure includes: providing a substrate having a semiconductor layer on an insulator layer; forming three dimensional fins in the semiconductor layer; applying a masking material to a first fin while exposing a second fin; applying a hydrogen atmosphere to the substrate and exposed second fin, the hydrogen atmosphere causing the exposed second fin to reflow and change shape; removing the masking material from the first fin; and forming a gate to wrap around each of the first and second fins. The first and second fins are formed having a device width such that the first fin having a first device width and a second fin having a second device width with the first device width being different than the second device width. | 07-24-2014 |
20140217482 | INTEGRATED CIRCUITS HAVING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME - A method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over remaining portions of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material. | 08-07-2014 |
20140217517 | INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer. | 08-07-2014 |
20140239394 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 08-28-2014 |
20140239398 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 08-28-2014 |
20140242797 | SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER - A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal. | 08-28-2014 |
20140252427 | Self-aligned Contacts For Replacement Metal Gate Transistors - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 09-11-2014 |
20140252446 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
20140252448 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
20140264479 | METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE - One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor. | 09-18-2014 |
20140264594 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264595 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 09-18-2014 |
20140264600 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264602 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 09-18-2014 |
20140264612 | GROWTH OF EPITAXIAL SEMICONDUCTOR REGIONS WITH CURVED TOP SURFACES - Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls. To further increase the thickness of the epitaxial semiconductor region, the method may cycle between depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls; and removing the amorphous portions on the sidewalls until the combined thickness of all the crystalline portions reaches a desired thickness. | 09-18-2014 |
20140264746 | SELF ALIGNED CAPACITOR FABRICATION - A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer. | 09-18-2014 |
20140273418 | BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline dielectric layer including an epitaxial oxide; forming a semiconductor layer on the crystalline dielectric layer, the semiconductor layer and the crystalline dielectric layer forming an extremely thin semiconductor-on-insulator (ETSOI) structure; and forming a set of devices on the semiconductor layer, wherein at least one device in the set of devices is formed over a doped region. | 09-18-2014 |
20140284667 | FINFET WITH REDUCED CAPACITANCE - An improved finFET structure, and method forming the same, including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins. | 09-25-2014 |
20140284719 | METHOD AND STRUCTURE FOR FINFET CMOS - According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal. | 09-25-2014 |
20140291734 | Thin Channel MOSFET with Silicide Local Interconnect - A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the second region. The first RSD region and second RSD region is separated laterally by a portion of the isolated area. A continuous silicide interconnect structure is formed overlying the first RSD region, the second RSD region and the portion of the isolated area situated between RSD regions. A contact may be formed on the surface of the silicide interconnect. | 10-02-2014 |
20140291761 | Asymmetric Spacers - A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses. | 10-02-2014 |
20140295674 | ANGLED GAS CLUSTER ION BEAM - An angled gas cluster ion beam (“GCIB”) and methods for using the same are disclosed. Gas clusters are ionized to create a gas cluster beam directed towards a semiconductor wafer. The semiconductor wafer is positioned so that it intercepts the gas cluster beam at an angle that is non-perpendicular to the beam, so that the gas cluster ions in the beam react with structures on the semiconductor wafer asymmetrically, allowing for asymmetrical deposition on or etching of material thereon. According to one embodiment, GCIB is used to form asymmetric spacers having different materials, different thicknesses, or both. | 10-02-2014 |
20140302661 | CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES - A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material. | 10-09-2014 |
20140308808 | Replacement Gate Integration Scheme Employing Multiple Types of Disposable Gate Structures - A plurality of disposable gate materials is employed to form multiple types of disposable gate stack structures. Different types of disposable gate stack structures are sequentially removed and replaced with different types of replacement gate stack structures. Sequential removal of the different types of disposable gate stack structures can be effected by employing etch chemistries that remove one type of disposable gate material while not etching at least another type of disposable gate material. Different types of replacement gate stack structures can employ different work function materials. Lithographic patterning of workfunction materials is avoided, and each replacement gate stack structure can have a workfunction material portion having a uniform thickness. | 10-16-2014 |
20140312423 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 10-23-2014 |
20140312425 | FINFET WITH CRYSTALLINE INSULATOR - FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region. | 10-23-2014 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |
20140315371 | METHODS OF FORMING ISOLATION REGIONS FOR BULK FINFET SEMICONDUCTOR DEVICES - One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches. | 10-23-2014 |
20140327088 | FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE - One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin. | 11-06-2014 |
20140327089 | FINFET DEVICES HAVING RECESSED LINER MATERIALS TO DEFINE DIFFERENT FIN HEIGHTS - One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin. | 11-06-2014 |
20140329380 | FORMATION OF SEMICONDUCTOR STRUCTURES WITH VARIABLE GATE LENGTHS - A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width. | 11-06-2014 |
20140332861 | FIN STRUCTURE WITH VARYING ISOLATION THICKNESS - Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses. | 11-13-2014 |
20140332903 | Integrated Circuit Having Raised Source Drains Devices with Reduced Silicide Contact Resistance and Methods to Fabricate Same - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 11-13-2014 |
20140339638 | INTEGRATING CHANNEL SIGE INTO PFET STRUCTURES - A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer. | 11-20-2014 |
20140339643 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS - A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region. | 11-20-2014 |
20140346573 | SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES, RELATED DESIGN STRUCTURE AND METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines. | 11-27-2014 |
20140346574 | ASYMMETRIC FINFET SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures. | 11-27-2014 |
20140346587 | INTEGRATED CIRCUIT HAVING MOSFET WITH EMBEDDED STRESSOR AND METHOD TO FABRICATE SAME - A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140346600 | Integrated Circuit Having MOSFET with Embedded Stressor and Method to Fabricate Same - A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140346685 | SILICON-BASED ELECTRONICS WITH DISABLING FEATURE - Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits. | 11-27-2014 |
20140349448 | SILICON-BASED ELECTRONICS WITH DISABLING FEATURE - Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits. | 11-27-2014 |
20140349459 | Integrated Circuit Having Raised Source Drains Devices with Reduced Silicide Contact Resistance and Methods to Fabricate Same - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 11-27-2014 |
20140353734 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION WITH REDUCED GATE AND CONTACT RESISTANCES - Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section. | 12-04-2014 |
20140353752 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY BACKGROUND - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140353801 | DEVICE ISOLATION IN FINFET CMOS - Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins. | 12-04-2014 |
20140357034 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140357037 | FINFET WITH ENHANCED EMBEDDED STRESSOR - A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where a portion of the second semiconductor region meets the first semiconductor region. | 12-04-2014 |
20140361377 | RETROGRADE DOPED LAYER FOR DEVICE ISOLATION - Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins. | 12-11-2014 |
20140367752 | TRANSISTOR HAVING ALL-AROUND SOURCE/DRAIN METAL CONTACT CHANNEL STRESSOR AND METHOD TO FABRICATE SAME - An intermediate transistor structure includes a fin structure disposed on a surface of an insulating layer. The fin structure has a gate structure disposed thereon between first and second ends of the fin structure. A first portion of the fin structure is a first doped portion that is disposed over a first recess in the surface of the insulating layer and a second portion of the fin structure is a second doped portion disposed over a second recess in the surface of the insulating layer. The intermediate transistor structure further includes source and drain metal disposed around the first and second doped portions, each inducing one of compression strain or tensile strain in a portion of the fin structure that is disposed within the gate structure and that functions during operation of the transistor as a channel of the transistor. | 12-18-2014 |
20140367781 | LATERAL DIODE COMPATIBLE WITH FINFET AND METHOD TO FABRICATE SAME - A method to fabricate a diode device includes providing a fin structure formed in a SOI layer. The fin structure has a sacrificial gate structure disposed on the fin structure between a first end of the fin structure and a second end of the fin structure. The method further includes depositing first doped semiconductor material on the first and second ends of the fin structure, where the first doped semiconductor material on the first end of the fin structure has one of the same doping polarity or an opposite doping polarity as the first doped semiconductor material on the second end of the fin structure. The method further includes removing the sacrificial gate structure to form a gap between the deposited first doped semiconductor material; depositing a second doped semiconductor material within the gap and forming first and second electrical contacts conductively connected to the first doped semiconductor material. | 12-18-2014 |
20140367782 | Lateral Diode Compatible with FinFET and Method to Fabricate Same - A structure includes a fin having first end and second ends and a substantially intrinsic portion between the first and second ends. The structure further includes a first region of doped semiconductor material disposed on the first end of the fin and a second region of doped semiconductor material disposed on the second end of the fin. The first region has one of the same doping polarity or an opposite doping polarity as the second region. The structure also includes a third region of doped semiconductor material disposed on the intermediate portion of the fin adjacent to the first region and the second region. The third region has a doping polarity that differs from the doping polarity of at least one of the first and second regions and forms a p-n junction with the at least one of the first and second regions. | 12-18-2014 |
20140367795 | METHODS OF FORMING DIFFERENT FINFET DEVICES HAVING DIFFERENT FIN HEIGHTS AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH DEVICES - One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height. | 12-18-2014 |
20140374796 | SEMICONDUCTOR STRUCTURE WITH ASPECT RATIO TRAPPING CAPABILITIES - A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance. | 12-25-2014 |
20140374807 | METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING - Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation. | 12-25-2014 |
20150014773 | Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 01-15-2015 |
20150021683 | METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess. | 01-22-2015 |
20150028398 | DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL - An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed. | 01-29-2015 |
20150028419 | FIN FIELD EFFECT TRANSISTOR WITH DIELECTRIC ISOLATION AND ANCHORED STRESSOR ELEMENTS - A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor. | 01-29-2015 |
20150028454 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 01-29-2015 |
20150035064 | INVERSE SIDE-WALL IMAGE TRANSFER - Methods forming structures on a chip. The methods include etching a mandrel layer that is disposed over a bottom layer to be patterned to form gaps between plateaus of mandrel material; forming spacers on sidewalls of the plateaus; forming a hardmask material in gaps between the spacers; removing the spacers to define a pattern around the hardmask material; and etching the bottom layer according to the pattern around the hardmask material. | 02-05-2015 |
20150035081 | INVERSE SIDE-WALL IMAGE TRANSFER - Semiconductor devices include a set of fin field effect transistors (FETs), each having a fin structure formed from a monocrystalline substrate. A trench between fin structures of respective fin FETs is formed by a cut in the monocrystalline substrate that has a width smaller than a width of the fin structures and that penetrates less than a full depth of the monocrystalline substrate. The trenches have a width smaller than a minimum pitch of a lithographic technology employed. | 02-05-2015 |
20150041812 | INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES - Semiconductor devices include a first set of fins having a uniform fin pitch that is less than half a minimum fin pitch for an associated lithography process; and a second set of fins having a variable fin pitch that is less the minimum fin pitch for the associated lithography process but greater than half the minimum fin pitch for the associated lithography process. | 02-12-2015 |
20150041824 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041826 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041853 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material. Following implantation of a cleavage layer and wafer bonding to a handle wafer, the layer of desired compound semiconductor material is fractured along the cleavage layer and the residual portion thereof removed. A layer of the desired compound semiconductor material is then regrown on the epitaxial oxide layer. | 02-12-2015 |
20150041856 | Compound Semiconductor Integrated Circuit and Method to Fabricate Same - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. | 02-12-2015 |
20150041908 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 02-12-2015 |
20150041958 | INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES - Semiconductor devices and method for forming the same. Methods for forming fin structures include forming a protective layer over a set of mandrels in a variable fin pitch region; forming first sidewalls around a set of mandrels in a uniform fin pitch region; removing the set of mandrels in the uniform fin pitch region; removing the protective layer; forming second sidewalls around the first sidewalls in the uniform fin pitch region and the mandrels in the variable fin pitch region; removing the first sidewalls and the mandrels; and etching an underlying layer around the second sidewalls. | 02-12-2015 |
20150044859 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. Methods to form the structure are also disclosed. | 02-12-2015 |
20150048455 | SELF-ALIGNED GATE CONTACT STRUCTURE - Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided. | 02-19-2015 |
20150056809 | DOUBLE PATTERNING METHOD - Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate. | 02-26-2015 |
20150059841 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 03-05-2015 |
20150060944 | DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices. | 03-05-2015 |
20150060981 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150061010 | STRUCTURE FOR IMPROVED CONTACT RESISTANCE AND EXTENSION DIFFUSION CONTROL - Semiconductor structures are provided including a raised source region comprising, from bottom to top, a source-side phosphorus doped epitaxial semiconductor material portion and a source-side arsenic doped epitaxial semiconductor material portion and located on one side of a gate structure, and a raised drain region comprising from bottom to top, a drain-side phosphorus doped epitaxial semiconductor material portion and a drain-side arsenic doped epitaxial semiconductor material portion and located on another side of the gate structure. | 03-05-2015 |
20150061040 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 03-05-2015 |
20150061076 | HIGH DENSITY RESISTOR - At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin. A polysilicon resistor is formed on exposed surfaces of the dielectric material and surrounding the at least one semiconductor fin. An interconnect dielectric material is formed above the polysilicon resistor. The interconnect dielectric material has at least one contact structure that extends through the interconnect dielectric to an upper surface of the polysilicon resistor. | 03-05-2015 |
20150061077 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 03-05-2015 |
20150064884 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 03-05-2015 |
20150064891 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150069327 | FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS - FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin. | 03-12-2015 |
20150069465 | HIGH PERCENTAGE SILICON GERMANIUM ALLOY FIN FORMATION - A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided. | 03-12-2015 |
20150069521 | NANOWIRE COMPATIBLE E-FUSE - An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion. | 03-12-2015 |
20150069526 | FIN FIELD EFFECT TRANSISTOR INCLUDING ASYMMETRIC RAISED ACTIVE REGIONS - Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged. | 03-12-2015 |
20150076561 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer. | 03-19-2015 |
20150076604 | FIELD EFFECT TRANSISTOR INCLUDING A RECESSED AND REGROWN CHANNEL - At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer. | 03-19-2015 |
20150076606 | SEMICONDUCTOR DEVICE WITH LOW-K SPACER - A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner. | 03-19-2015 |
20150076608 | DUAL EPITAXY REGION INTEGRATION - A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region | 03-19-2015 |
20150083999 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084001 | GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084101 | MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES - A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate. | 03-26-2015 |
20150091100 | METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure. | 04-02-2015 |
20150097217 | SEMICONDUCTOR ATTENUATED FINS - A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. FinFET fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the first and second materials. The attenuation portion may be formed by diffusing the first material into a plurality of fins made of the second material. The attenuated composite attenuates from a first composite to a second composite, the first composite comprising a majority of the first material, the second composite comprising a majority of the second material. The outer portion may be located on the fin perimeter and the inner portion may be located central to the fin. The first material may be Germanium, the second material may be Silicon, and the attenuated composite may be attenuated Silicon Germanium. | 04-09-2015 |
20150102422 | INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer. | 04-16-2015 |
20150102454 | FORMING FINS OF DIFFERENT MATERIALS ON THE SAME SUBSTRATE - A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer. | 04-16-2015 |
20150108589 | EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS - A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate. | 04-23-2015 |
20150123205 | FIELD EFFECT TRANSISTOR INCLUDING A REGROWN CONTOURED CHANNEL - At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region. | 05-07-2015 |
20150126009 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material. | 05-07-2015 |
20150137181 | STRESS INDUCING CONTACT METAL IN FINFET CMOS - A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer. | 05-21-2015 |
20150137193 | FINFET STRUCTURES WITH FINS RECESSED BENEATH THE GATE - A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region. | 05-21-2015 |
20150137308 | SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET - A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. | 05-21-2015 |
20150145048 | STRUCTURE AND METHOD FOR FORMING CMOS WITH NFET AND PFET HAVING DIFFERENT CHANNEL MATERIALS - Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium. | 05-28-2015 |
20150194562 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 07-09-2015 |
20150200107 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 07-16-2015 |
20150200205 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 07-16-2015 |
20150206744 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS - A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region. | 07-23-2015 |
20150206884 | DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP - After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers. | 07-23-2015 |
20150206885 | DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM - Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions. | 07-23-2015 |
20150206904 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS - A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region. | 07-23-2015 |
20150214117 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 07-30-2015 |
20150214219 | GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS - A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed. | 07-30-2015 |
20150214338 | FINFET WITH SILICON GERMANIUM STRESSOR AND METHOD OF FORMING - The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin. | 07-30-2015 |
20150228652 | SEMICONDUCTOR DEVICE INCLUDING NANOWIRE TRANSISTORS WITH HYBRID CHANNELS - A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor. | 08-13-2015 |
20150228671 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 08-13-2015 |
20150228783 | FIELD EFFECT TRANSISTORS EMPLOYING A THIN CHANNEL REGION ON A CRYSTALLINE INSULATOR STRUCTURE - A single crystalline dielectric layer is provided on an insulator layer including an amorphous dielectric material. The single crystalline dielectric layer can be patterned into various crystalline dielectric portions including dielectric fins, dielectric nanowires, and a dielectric fin-plate assembly. A semiconductor material can be deposited on the single crystalline surfaces of the various crystalline dielectric portions by a selective epitaxial deposition process while not growing on the surfaces of the insulator layer. Single crystalline semiconductor material portions can be formed on the surfaces of the dielectric fins, around the dielectric nanowires, and on horizontal and vertical surfaces of the dielectric fin-plate assembly. Source and drain regions can be formed in the single crystalline semiconductor material portions, and gate electrodes can be formed to provide various field effect transistors. | 08-13-2015 |
20150230720 | FLEXIBLE ACTIVE MATRIX CIRCUITS FOR INTERFACING WITH BIOLOGICAL TISSUE - High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors. | 08-20-2015 |
20150236019 | CMOS TRANSISTORS INCLUDING GATE SPACERS OF THE SAME THICKNESS - A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion. After formation of first raised active regions on the first semiconductor material portion, a dielectric stack of a dielectric oxide liner and a dielectric nitride liner is formed. The dielectric stack is removed over the second semiconductor material portion and a second gate spacer is formed on the second semiconductor material portion, while the dielectric stack protects the first raised active regions. A second gate spacer is formed by anisotropically etching the dielectric material layer over the second semiconductor material portion. The first and second gate spacers have the same composition and thickness. Second raised active regions can be formed on the second semiconductor material portion. | 08-20-2015 |
20150236120 | NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS - A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. | 08-20-2015 |
20150243497 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 08-27-2015 |
20150243755 | DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE - A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain. | 08-27-2015 |
20150249036 | METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS - One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure. | 09-03-2015 |
20150249125 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric. | 09-03-2015 |
20150249139 | METHODS OF FORMING GERMANIUM-CONTAINING AND/OR III-V NANOWIRE GATE-ALL-AROUND TRANSISTORS - Methods of forming gate-all-around transistors which include a germanium-containing nanowire and/or an III-V compound semiconductor nanowire. Each method includes the growth of a germanium-containing material or an III-V compound semiconductor material that includes an upper portion and a lower portion within a nano-trench and on an exposed surface of a semiconductor layer. In some instances, the upper portion of the grown semiconductor material is used as the semiconductor nanowire. In other instances, the upper portion is removed and then a semiconductor etch stop layer and a nanowire template semiconductor material of a Ge-containing material or an III-V compound semiconductor material can be formed atop the lower portion. Upon subsequent processing, each nanowire template semiconductor material provides a semiconductor nanowire. | 09-03-2015 |
20150255459 | CMOS TRANSISTORS WITH IDENTICAL ACTIVE SEMICONDUCTOR REGION SHAPES - A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein. | 09-10-2015 |
20150255538 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 09-10-2015 |
20150255541 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 09-10-2015 |
20150255542 | METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material. | 09-10-2015 |
20150255574 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 09-10-2015 |
20150255608 | METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material. | 09-10-2015 |
20150262998 | INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES - An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer. | 09-17-2015 |
20150263046 | FINFET SEMICONDUCTOR DEVICE HAVING INCREASED GATE HEIGHT CONTROL - A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region. | 09-17-2015 |
20150263097 | INTEGRATED CIRCUIT HAVING HETEROSTRUCTURE FINFET WITH TUNABLE DEVICE PARAMETERS AND METHOD TO FABRICATE SAME - A field effect transistor (FET) device has a fin disposed over a substrate. The fin has opposing ends defining a source and a drain and intermediate the source and the drain a channel underlying a gate. The fin is formed as a heterostructure having at least one first layer of material and at least one second layer of material that is adjacent to the first layer of material. A thickness of at least one of the first layer of material and the second layer of material is selected to obtain a particular effective device width W. Methods to fabricate the FET device are also described. | 09-17-2015 |
20150263128 | METHOD OF PREVENTING EPITAXY CREEPING UNDER THE SPACER - After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is intentionally etched and undercut regions that are formed are filled and pinched off with a dielectric material of a conformal dielectric liner. Portions of the conformal dielectric liner in the undercut regions are not subject to the undercut during an epitaxial pre-clean process performed prior to forming an epitaxial source region and an epitaxial drain region on opposite sides of the sacrificial gate structure and remain in the undercut regions after forming the epitaxial source region and the epitaxial drain region. | 09-17-2015 |
20150263160 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS - One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess. | 09-17-2015 |
20150270171 | DIELECTRIC LINER FOR A SELF-ALIGNED CONTACT VIA STRUCTURE - At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer. | 09-24-2015 |
20150270267 | ABRUPT SOURCE/DRAIN JUNCTION FORMATION USING A DIFFUSION FACILITATION LAYER - A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate. | 09-24-2015 |
20150270285 | THIN CHANNEL-ON-INSULATOR MOSFET DEVICE WITH N+ EPITAXY SUBSTRATE AND EMBEDDED STRESSOR - A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe. | 09-24-2015 |
20150270340 | STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures. | 09-24-2015 |
20150270395 | THIN CHANNEL-ON-INSULATOR MOSFET DEVICE WITH N+EPITAXY SUBSTRATE AND EMBEDDED STRESSOR - A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe. | 09-24-2015 |
20150276653 | SWITCHED-CAPACITOR BIOSENSOR DEVICE - A sensing apparatus includes a device containing microwells and a switched capacitor circuit in which at least one of the sensing/storage capacitors is a capacitor that extends perpendicularly with respect to a semiconductor device layer containing field effect transistors. Capacitor structures extend into microwells or within a doped layer on a handle substrate. Ion generation within the microwells is sensed using the circuit. | 10-01-2015 |
20150279742 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES USING A GATE HEIGHT REGISTER PROCESS TO IMPROVE GATE HEIGHT UNIFORMITY AND THE RESULTING INTEGRATED CIRCUIT PRODUCTS - One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process. | 10-01-2015 |
20150279963 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE SO AS TO REDUCE PUNCH-THROUGH LEAKAGE CURRENTS AND THE RESULTING DEVICE - One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity. | 10-01-2015 |
20150287614 | FINFET SEMICONDUCTOR DEVICE HAVING INTEGRATED SiGe FIN - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough. | 10-08-2015 |
20150295037 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150295038 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150295039 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150303251 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure includes a handle substrate and an epitaxial oxide layer. The epitaxial oxide layer is bonded directly or indirectly to the handle substrate. Also included is a compound semiconductor layer adjoining and lattice matched to the epitaxial oxide layer. | 10-22-2015 |
20150303257 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-22-2015 |
20150318216 | FORMATION OF GERMANIUM-CONTAINING CHANNEL REGION BY THERMAL CONDENSATION UTILIZING AN OXYGEN PERMEABLE MATERIAL - A structure including a first semiconductor material portion and a second semiconductor material portion is provided. An oxygen impermeable hard mask is then formed directly on a surface of the first semiconductor material portion. Next, a silicon germanium layer is epitaxially formed on the second semiconductor material portion, but not the first semiconductor material portion. An oxygen permeable hard mask is then formed over the first and second semiconductor material portions. A thermal condensation process is then performed which converts the second semiconductor material portion into a germanium-containing semiconductor material portion. The oxygen permeable hard mask and the oxygen impermeable hard mask are then removed. A functional gate structure can be formed atop the remaining first semiconductor material portion and the thus formed germanium-containing semiconductor material portion. | 11-05-2015 |
20150318416 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD - A method for forming a multi-junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface. | 11-05-2015 |
20150325664 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 11-12-2015 |
20150349083 | METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material. | 12-03-2015 |
20150357423 | FLEXIBLE ACTIVE MATRIX CIRCUITS FOR INTERFACING WITH BIOLOGICAL TISSUE - High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors. | 12-10-2015 |
Patent application number | Description | Published |
20140141587 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 05-22-2014 |
20140231920 | INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME - Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate. The replacement metal gate structure includes a first metal and a second metal and has a recess surface formed by the first metal and the second metal. The first metal and the second metal include a first species of diffused foreign ions. The integrated circuit further includes a metal fill material overlying the recess surface formed by the first metal and the second metal. | 08-21-2014 |
20140256106 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 09-11-2014 |
20140264387 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 09-18-2014 |
20140302658 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 10-09-2014 |
20140312428 | EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN - Disclosed is a semiconductor article which includes a semiconductor substrate; a plurality of gate structures having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to each of the gate structures, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET. | 10-23-2014 |
20140327058 | SELF-ALIGNED CONTACTS FOR REPLACEMENT METAL GATE TRANSISTORS - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 11-06-2014 |
20140353721 | BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height. | 12-04-2014 |
20140361314 | SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR - Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins. | 12-11-2014 |
20140362638 | STRUCTURE AND METHOD FOR ADJUSTING THRESHOLD VOLTAGE OF THE ARRAY OF TRANSISTORS - A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. | 12-11-2014 |
20150041868 | SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS - A semiconductor device is provided that includes a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region. The gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to the at least one gate conductor. An upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer. A multi-layered cap is present on the upper surface of the gate conductor. The multi-layered cap includes a high-k dielectric material and a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer. | 02-12-2015 |
20150054081 | EPITAXIAL SEMICONDUCTOR RESISTOR WITH SEMICONDUCTOR STRUCTURES ON SAME SUBSTRATE - An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material. | 02-26-2015 |
20150056792 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 02-26-2015 |
20150061021 | SEMI-CONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE - A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region. | 03-05-2015 |
20150064874 | DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM - FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC). | 03-05-2015 |
20150132896 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 05-14-2015 |
20150137147 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 05-21-2015 |
20150137240 | SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME - A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions. | 05-21-2015 |
20150140743 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 05-21-2015 |
20150140744 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 05-21-2015 |
20150140799 | ASYMMETRIC SPACERS - A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses. | 05-21-2015 |
20150145063 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 05-28-2015 |
20150147853 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 05-28-2015 |
20150155301 | SEMICONDUCTOR SUBSTRATE WITH MULTIPLE SiGe REGIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS BY A SINGLE EPITAXY PROCESS - A substrate with two SiGe regions having different Germanium concentrations and a method for making the same. The structure includes an extremely-thin-silicon-germanium-on-insulator (ETSGOI) substrate with at least two active regions, wherein each of the at least two active regions has a SiGe layer with uniform Germanium concentration, and the Germanium concentration of the SiGe layer of one of the at least two active regions is different than the Germanium concentration of the SiGe layer of the other of at least two active regions. | 06-04-2015 |
20150155306 | STRUCTURE AND METHOD TO REDUCE CRYSTAL DEFECTS IN EPITAXIAL FIN MERGE USING NITRIDE DEPOSITION - FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride. | 06-04-2015 |
20150155307 | STRUCTURE AND METHOD TO REDUCE CRYSTAL DEFECTS IN EPITAXIAL FIN MERGE USING NITRIDE DEPOSITION - FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins. | 06-04-2015 |
20150179453 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 06-25-2015 |
20150187815 | MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES - A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate. | 07-02-2015 |
20150187816 | FINFET WITH REDUCED CAPACITANCE - An finFET structure including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins. | 07-02-2015 |
20150194507 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material. | 07-09-2015 |
20150228489 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 08-13-2015 |
20150228653 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 08-13-2015 |
20150228654 | METHOD AND STRUCTURE FOR FINFET CMOS - According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal. | 08-13-2015 |
20150228761 | DIAMOND SHAPED EPITAXY - In a first embodiment of the present invention, a semiconductor device manufacturing process includes forming a plurality of fins on a semiconductor substrate, forming diamond shaped epitaxy on fin sidewalls, merging the diamond shaped epitaxy, and removing the merged epitaxy. In another embodiment of the present invention, a semiconductor device includes a semiconductor substrate including a plurality of fins formed thereupon and unmerged diamond shaped epitaxy formed upon the sidewalls of each fin. The unmerged diamond shaped epitaxy is formed independent from neighboring fin geometry deficiencies. In yet another embodiment, the semiconductor device is included in a design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit. | 08-13-2015 |
20150228780 | FinFET DEVICE WITH ABRUPT JUNCTIONS - A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers. | 08-13-2015 |
20150235908 | ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUTOR DEVICES - An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions | 08-20-2015 |
20150236020 | CMOS TRANSISTORS INCLUDING GATE SPACERS OF THE SAME THICKNESS - A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion. After formation of first raised active regions on the first semiconductor material portion, a dielectric stack of a dielectric oxide liner and a dielectric nitride liner is formed. The dielectric stack is removed over the second semiconductor material portion and a second gate spacer is formed on the second semiconductor material portion, while the dielectric stack protects the first raised active regions. A second gate spacer is formed by anisotropically etching the dielectric material layer over the second semiconductor material portion. The first and second gate spacers have the same composition and thickness. Second raised active regions can be formed on the second semiconductor material portion. | 08-20-2015 |
20150247259 | LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION - An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000. | 09-03-2015 |
20150255543 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device fabrication process includes forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 09-10-2015 |
20150255556 | SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT - A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption. | 09-10-2015 |
20150255603 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 09-10-2015 |
20150255605 | METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES - Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET. | 09-10-2015 |
20150255606 | STRUCTURE AND METHOD TO MAKE STRAINED FINFET WITH IMPROVED JUNCTION CAPACITANCE AND LOW LEAKAGE - A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type. | 09-10-2015 |
20150263041 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 09-17-2015 |
20150263088 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin. | 09-17-2015 |
20150263091 | LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING GRADED SiGe BASE - A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip. | 09-17-2015 |
20150270344 | P-FET WITH GRADED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile. | 09-24-2015 |
20150270349 | P-FET WITH STRAINED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region. | 09-24-2015 |
20150270359 | DIELECTRIC LINER FOR A SELF-ALIGNED CONTACT VIA STRUCTURE - At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer. | 09-24-2015 |
20150279723 | BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES - A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices. | 10-01-2015 |
20150279861 | DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES - Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. | 10-01-2015 |
20150279936 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 10-01-2015 |
20150294973 | INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET - The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer. | 10-15-2015 |
20150294984 | HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR INTEGRATED INTO EXTREMELY THIN SEMICONDUCTOR ON INSULATOR PROCESS - An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region. | 10-15-2015 |
20150295046 | FINFET WITH DIELECTRIC ISOLATED CHANNEL - Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution. | 10-15-2015 |
20150295087 | FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS - A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. | 10-15-2015 |
20150311320 | FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS - A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure. | 10-29-2015 |
20150318281 | RECESSED SOURCE DRAIN CONTACT REGIONS INDEPENDENT OF DEVICE PITCH BY UNMERGED EPITAXY ON FIN PORTIONS - A semiconductor device fabrication process includes forming a plurality of fins upon a semiconductor substrate and forming a plurality of gate stacks upon the semiconductor substrate orthogonal to the plurality of fins, forming fin portions by recessing the plurality of fins and semiconductor substrate adjacent to the plurality of gate stacks, and forming uniform unmerged epitaxy upon the fin portions. A semiconductor device includes the plurality of fins, the plurality of gate stacks, a first semiconductor substrate recess between a first gate stack pair and a second semiconductor recess between a second gate stack pair, and unmerged epitaxy. The plurality of fins each include fin portions and the unmerged epitaxy including a first epitaxy pair contacting fin portions associated with the first gate stack pair and a second epitaxy pair contacting fin portions associated with the second gate stack pair. | 11-05-2015 |
20150318284 | SELF ALIGNED STRUCTURE AND METHOD FOR HIGH-K METAL GATE WORK FUNCTION TUNING - A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer. | 11-05-2015 |
20150318377 | FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION - A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure. | 11-05-2015 |
20150325572 | FINFET AND FIN-PASSIVE DEVICES - A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins. | 11-12-2015 |
20150332964 | SELF-LIMITING SILICIDE IN HIGHLY SCALED FIN TECHNOLOGY - A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then be intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure. A core of the fin structure of the single crystal semiconductor material is substantially free of the metal elements from the metal including layer. | 11-19-2015 |
20150333156 | DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL - An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed. | 11-19-2015 |
20150333172 | METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS - A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure. | 11-19-2015 |
20150340291 | COMPLEX CIRCUITS UTILIZING FIN STRUCTURES - A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material. | 11-26-2015 |
20150340364 | COMPLEX CIRCUITS UTILIZING FIN STRUCTURES - A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material. | 11-26-2015 |
20150348995 | STRUCTURE AND METHOD TO REDUCE CRYSTAL DEFECTS IN EPITAXIAL FIN MERGE USING NITRIDE DEPOSITION - A FinFET device includes a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins. At least one sidewall of each of the plurality of fins remain uncovered by the nitride material. The nitride material may also not contact the bottom of the plurality of fins. | 12-03-2015 |
20150349123 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device is fabricated by forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 12-03-2015 |
20150357331 | FINFET AND FIN-PASSIVE DEVICES - A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins. | 12-10-2015 |
20150357411 | P-FET WITH STRAINED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region. | 12-10-2015 |
20150357470 | FINFET WITH OXIDATION-INDUCED STRESS - A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided. | 12-10-2015 |
20150357471 | STRESS INDUCING CONTACT METAL IN FINFET CMOS - A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer. | 12-10-2015 |
20150364555 | P-FET WITH GRADED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile. | 12-17-2015 |