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| 20090057920 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 03-05-2009 |
| 20120106094 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 05-03-2012 |
| 20120187579 | LOW NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A flip chip comprises first and second circuitry portions formed in a substrate. The first and second circuitry portions are spaced apart from one another in a separation direction. A substrate-contact boundary is formed in the substrate between the first and second circuitry portions. | 07-26-2012 |
| 20120326335 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 12-27-2012 |
| 20140124930 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 05-08-2014 |
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| 20090085660 | AGC MODULE AND METHOD FOR CONTROLLING NOISE FIGURE AND INTERMODULATION CHARACTERISTICS THEREIN - An Automatic Gain Control (AGC) module for controlling Noise Figure (NF) and IM characteristics therein is disclosed. The AGC module comprises a plurality of AGC stages. Each AGC stage comprises a differential amplifier circuit, an input signal transistor and a current-steering circuit. Differential amplifier circuits of the plurality of AGC stages receive control signals at their differential inputs and their output is connected to a common load. The input signal transistors of the plurality of AGC stages receive a common input signal and is further coupled to the differential amplifier circuit and the current-steering circuit. The current-steering circuits and the control signals at the differential amplifier circuits control gain of the each AGC stage of the plurality of AGC stage, which is used to control the NF and the IM characteristics. | 04-02-2009 |
| 20100323636 | Apparatus and methods for implementing multi-channel tuners - Embodiments of systems and methods for implementing multi-channel tuners are generally described herein. Other embodiments may be described and claimed. | 12-23-2010 |
| 20100330932 | Apparatus and methods for efficient implementation of tuners - Embodiments of systems and methods for the efficient implementation of tuners are generally described herein. Other embodiments may be described and claimed. | 12-30-2010 |
| 20110019785 | Alignment of channel filters for multiple-tuner apparatuses - Apparatuses, systems, and methods that align channel filters for dual tuners are disclosed. An embodiment may comprise an IC having two tuners. Each tuner may have a low-noise amplifier, a mixer with a local oscillator, and channel filter. To perform a channel filter alignment, a bandwidth controller may cross-couple the local oscillator of each tuner to the input of the mixer of the opposite tuner. The bandwidth controller may adjust the frequencies of the local oscillators to produce different configuration tone frequencies at the outputs of the mixers, which are inputs to the channel filters. The bandwidth controller may then determine an amplitude difference between two separate measurements of a channel filter output and, based on a comparison of the measurements with predicted values, increment or decrement the filter bandwidth for each tuner and store parameters for the channel filters which create the largest signal amplitudes. | 01-27-2011 |
| 20110069744 | METHODS AND SYSTEMS TO COMPENSATE IQ IMBALANCE IN WIDEBAND ZERO-IF TUNERS - Methods and systems to compensate IQ imbalances in a tuner system, including relatively wideband ZIF tuner systems and tuner systems having substantially linear frequency dependent phase imbalance, where a one-tap compensation element may be utilized to compensate frequency dependent phase imbalance. A two tone probe may be applied in controlled loop-back modes, and resultant baseband components may be used to determine a straight line from which to determine compensation. The probe may include a Multi-Media over Coax Alliance (MoCA) Type 2 probe. Compensation parameters may be determined as fixed or non-adaptive compensation parameters in a digital domain and may be applied at baseband. One or more compensation values may be determined in a fixed point circuit. | 03-24-2011 |
| 20110075034 | METHOD AND APPARATUS TO SUPPORT MULTI-CHANNEL RECEPTION - In accordance with various aspects of the disclosure, a method and apparatus for receiving multiple channels from a broadcast source and interfacing to multiple demodulators within a common silicon implementation is disclosed. A receiver apparatus is disclosed that may aggregate multiple channels output by multiple tuners into at least one composite signal. The at least one composite signal may be passed to a single ADC. The channels may then be extracted from the at least one composite signal in the digital domain prior to demodulation in separate demodulators. | 03-31-2011 |
| 20110149171 | Efficient tuning and demodulation techniques - Techniques for the reception and processing of wireless signals are disclosed. For instance, an apparatus may include multiple receiving paths, a content stream generation module, and a distribution module. The multiple receiving paths include a first receiving path that generates a first decoded signal from an input RF signal in accordance with a first tuning setting. The content stream generation module has first and second inputs. Based on decoded signals received at the first and second inputs, the content stream generation module may generate first and second content streams, respectively. In situations where both the first and second content streams correspond to the first tuning setting, the distribution module provides the first decoded signal to both the first and second inputs of the content stream generation module. Also, a control module may remove operational power from any of the plurality of receiving paths that are currently being unused. | 06-23-2011 |
| 20110151818 | CORRECTING QUADRATURE CROSSTALK CONTAMINATION IN RECEIVERS - An apparatus, a method and a system for correcting a phase imbalance are described. Embodiments may measure the phase imbalance inherent in a tuner and use the imbalance measure to correct the output of the tuner. Embodiments may include a tone generator to produce a single frequency tone and a tuner to receive the single frequency tone and output an intermediate frequency. The intermediate frequency may be corrected by a correction loop. Other embodiments are described and claimed. | 06-23-2011 |
| 20110293043 | DC OFFSET CORRECTION TECHNIQUES - Techniques are disclosed that involve the reduction of DC offsets. For instance, embodiments may receive a baseband signal, and determine a DC characteristic of the baseband signal. When the DC characteristic has a value that is outside of a predetermined range, a correction signal is adjusted. The correction signal is injected into the baseband signal. | 12-01-2011 |
| 20110293048 | Quadrature gain and phase imbalance correction - Generally speaking, methods and apparatuses which correct errors related to phase and gain imbalances in quadrature tuners are disclosed. The quadrature tuner may be online and operating, receiving data. An embodiment may generate a squared signal from the IF frequency signal of the tuner. In generating the squared signal, the embodiment may enable the extraction of phase error and gain error information of the IF signal. The embodiment may determine a phase error component, a gain error component, or both, by frequency translation. The frequency translation may involve down-converting the signal associated with the error component to direct current (DC) signals and enable the determination of the associated phase error and/or gain error. The embodiments may generate an adjusted signal via the IF signal by applying a phase correction signal or gain correction signal to components used to correct the IF signal. | 12-01-2011 |
| 20120076191 | Apparatus and method to process signals from one or more transmission sources - A receiver and a method to process signals from one or more transmission sources. The receives includes a front-end having: an input coupling path to route an analog input signal received from one or more transmission sources; an equalizer to generate an equalized signal from the analog input signal; and an ADC to generate a digitized signal from the equalized signal. The method includes routing the analog input signal through an input coupling path; equalizing the analog input signal to generate an equalized signal therefrom; and digitizing the equalized signal to generate a digitized signal therefrom. | 03-29-2012 |
| 20120249107 | COUPLED INDUCTOR TO FACILITATE INTEGRATED POWER DELIVERY - An embodiment of the present invention provides an apparatus, comprising a surface mounted device (SMD) inductor, the SMD inductor including at least two counter wound aircoils formed on a same SMD former; wherein the at least two counter wound aircoils are connected to three terminals on the SMD former, wherein a single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node. | 10-04-2012 |
| 20130154732 | POWER MANAGEMENT IN TRANSCEIVERS - Various embodiments are directed to apparatuses and methods to reduce average power dissipation in transceiver stages such as power amplifiers and low noise amplifiers (LNAs) that process signals of varying output amplitudes. Power dissipation may be reduced by varying the supply voltage in sympathy with the amplitude of the signal and/or the stage current density which may also be varied in sympathy with the signal amplitude. | 06-20-2013 |
| 20130157482 | DECOUPLING ARRANGEMENT - In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component. | 06-20-2013 |
| 20140091958 | METHODS AND ARRANGEMENTS FOR HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION - Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output. | 04-03-2014 |
| 20140091960 | METHODS AND ARRANGEMENTS FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION - Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes. | 04-03-2014 |
| 20150035507 | DUAL MODE VOLTAGE REGULATOR WITH DYNAMIC RECONFIGURATION CAPABILITY - A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal. | 02-05-2015 |
| 20150131190 | DECOUPLING ARRANGEMENT - In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component. | 05-14-2015 |
| 20150295550 | POWER MANAGEMENT IN TRANSCEIVERS - Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data. | 10-15-2015 |
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| 20090082250 | Control of gene expression using a complex of an oligonucleotide and a regulatory peptide - A method for suppressing the expression of a selected gene in a cell the method comprising introducing into the cell a molecule comprising (1) a nucleic acid binding portion which binds to a site or associated with the selected gene which site is present in a genome and (2) an expression repressor portion, wherein the nucleic acid binding portion comprises an oligonucleotide or oligonucleotide mimic or analogue, and wherein the repressor portion comprises a polypeptide or peptidomimetic. Molecules for use in the methods of the invention are provided. The repressor may be a portion of a histone deacetylase or DNA methylase or polypeptide capable of recruiting a histone deacetylase or DNA methylase. | 03-26-2009 |
| 20100261683 | Selective Inhibitors for Cyclin-Dependent Kinases - This invention provides a class of compounds which are useful for specifically inhibiting cyclin-dependent kinases. This class of compounds finds use in treating diseases resulting from inappropriate activity of cyclin-dependent kinases, including cancer, viral infections (e.g., HIV) neurodegenerative disorders (e.g. Alzheimer's disease), and cardiovascular disorders (e.g. atherosclerosis). Moreover, certain members of this class are particularly useful for inhibiting cyclin-dependent kinase 7 and are especially useful for the treatment of breast cancer. | 10-14-2010 |
| 20110189669 | METHODS OF AIDING IN THE DIAGNOSIS OF PROSTATE CANCER - The current invention provides a method for aiding in the assessment of prostate cancer (including metastatic prostate cancer) and/or benign prostate hyperplasia in a patient, wherein the method comprises the step of determining the level of Glycine N-methyltransferase (GNMT) nucleic acid and/or protein in a sample from the patient. The invention also provides compounds that target Glycine N-methyltransferase (GNMT) protein and/or nucleic acid for use in treating prostate cancer. Also provided are screening methods for selecting a compound considered to be useful in treating prostate cancer, comprising the steps of determining the ability of a test compound to reduce GNMT activity and selecting a compound that reduces GNMT activity. The invention also provides methods for aiding in the diagnosis of prostate cancer in a patient comprising obtaining a sample from the patient and assessing said sample for a marker of GNMT activity. | 08-04-2011 |
| 20120077270 | Control of Gene Expression Using a Complex of an Oligonucleotide and a Regulatory Peptide - A method for suppressing the expression of a selected gene in a cell, the method comprising introducing into the cell a molecule comprising (1) a nucleic acid binding portion which binds to a site or associated with the selected gene which site is present in a genome and (2) an expression repressor portion, wherein the nucleic acid binding portion comprises an oligonucleotide or oligonucleotide mimic or analogue, and wherein the repressor portion comprises a polypeptide or peptidomimetic. Molecules for use in the methods of the invention are provided. The repressor may be a portion of a histone deacetylase or DNA methylase or polypeptide capable of recruiting a histone deacetylase or DNA methylase. | 03-29-2012 |
