Patent application number | Description | Published |
20140164880 | ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY - An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. | 06-12-2014 |
20140281767 | RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE - A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window. | 09-18-2014 |
20150077277 | REDUCED POLAR CODES - A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword after the bits are removed. | 03-19-2015 |
Patent application number | Description | Published |
20130145235 | DETECTION AND DECODING IN FLASH MEMORIES WITH SELECTIVE BINARY AND NON-BINARY DECODING - Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently. | 06-06-2013 |
20130145238 | ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES - Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline. | 06-06-2013 |
20130185598 | MULTI-TIER DETECTION AND DECODING IN FLASH MEMORIES - Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page. | 07-18-2013 |
20130185599 | DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGHBORING BITS - Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a given page of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value for a bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the bit in the page using the reliability value. The probability that the data pattern was written to the plurality of bits given that the particular pattern was read from the plurality of bits is obtained from one or more tables. | 07-18-2013 |
20140219028 | Compensation Loop for Read Voltage Adaptation - The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads. The N bit digital pattern generated by the N reads is mapped to a signed representation. A voltage adjustment based upon the signed representation is applied to at least partially compensate for a variation of the nominal read voltage to reduce bit error rate of the flash device. | 08-07-2014 |
20140298131 | Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders - A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping. | 10-02-2014 |