| Patent application number | Description | Published |
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| 20080246545 | DIGITAL PHASE AND FREQUENCY DETECTOR - Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles. | 10-09-2008 |
| 20090195275 | TECHNIQUE FOR EFFICIENTLY MANAGING BOTH SHORT-TERM AND LONG-TERM FREQUENCY ADJUSTMENTS OF AN ELECTRONIC CIRCUIT CLOCK SIGNAL - A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control. | 08-06-2009 |
| 20090195278 | METHOD AND CIRCUIT FOR CONTROLLING CLOCK FREQUENCY OF AN ELECTRONIC CIRCUIT WITH NOISE MITIGATION - A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal. | 08-06-2009 |
| 20090252215 | SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD - A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer. | 10-08-2009 |
| 20100013531 | PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING PULSEWIDTH MODULATION FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS - PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied. | 01-21-2010 |
| 20100013532 | PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING MULTIPLEXER CIRCUIT FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS - Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control. | 01-21-2010 |
| 20100017690 | METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM - A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO). | 01-21-2010 |
| 20100188158 | OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL - A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL. | 07-29-2010 |
| 20110063003 | PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE - Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals. | 03-17-2011 |
| 20110298561 | LOW DISTORTION HIGH BANDWIDTH ADAPTIVE TRANSMISSION LINE FOR INTEGRATED PHOTONICS APPLICATIONS - A transmission line and method for implementing includes a plurality of segments forming an electrical path and a continuous optical path passing through the segments. Discrete inductors are formed between and connect adjacent segments. The inductors are formed in a plurality of metal layers of an integrated circuit to balance capacitance of an optical modulator which includes the transmission line to achieve a characteristic impedance for the transmission line. | 12-08-2011 |
| 20120001166 | PARELLEL OPTICAL TRANSCEIVER MODULE - A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer. | 01-05-2012 |
| 20120001697 | DIFFERENTIAL AMPLIFIER STAGE WITH INTEGRATED OFFSET CANCELLATION CIRCUIT - A differential amplifier stage and method for offset cancellation include an amplifier having an input and an output. An internal offset cancellation circuit has an input for receiving a control signal to control offset cancellation in the amplifier. The offset cancellation circuit is integrated with the amplifier but isolated from the input and the output of the amplifier, and, in accordance with its isolation, an impedance of the stage is unaffected by the offset cancellation circuit. | 01-05-2012 |
| 20120155864 | ADAPTIVE POWER EFFICIENT RECEIVER ARCHITECTURE - Systems and methods for processing an optical signal are disclosed. The optical signal is converted to a voltage signal and the voltage signal is amplified. In addition, a signal strength and/or a signal quality parameter is monitored and an indication of the signal strength and/or a signal quality parameter is generated. Further, a gain and/or an operating bandwidth on the conversion or the amplification can be adjusted based on the indication to reduce power consumption of an optical receiver. | 06-21-2012 |
| 20120224849 | OPTICAL INTERCONNECT USING OPTICAL TRANSMITTER PRE-DISTORTION - In one embodiment, the invention provides an optical interconnect comprising a transmitter for generating and transmitting an optical signal, a receiver for receiving the optical signal from the transmitter and for converting the received optical signal to an electrical signal, and a pre-transmitter distort circuit for applying a pre-transmitter distort signal to the transmitter to adjust the shape of the optical signal generated by the transmitter. Distortions are introduced into the optical signal when the optical signal is generated, transmitted to the receiver, and converted to the electrical signal. As a result of the signal applied to the transmitter by the pre-transmitter distort circuit, the optical signal generated by the transmitter has distortions to compensate for the distortions introduced into the optical signal, wherein the electrical signal, into which the optical signal is converted, has a desired shape. | 09-06-2012 |
| 20120224868 | OPTICAL RECEIVER BASED ON A DECISION FEEDBACK EQUALIZER - An optical receiver, a method of operating an optical receiver, a correction based transimpedance amplifier circuit, and a method of adjusting an output of a transimpedance amplifier. In one embodiment, the optical receiver comprises an optical-to-electrical converter, a transimpedance amplifier, and a correction circuit. The optical-to-electrical converter is provided for receiving an optical signal and converting the optical signal to an electrical signal. The transimpedance amplifier is provided for receiving the electrical signal from the optical-to-electrical converter and for generating from the electrical signal an amplified electrical signal. The amplified electrical signal has inter symbol interference resulting from a reduced bandwidth of the transimpedance amplifier. The correction circuit is provided for receiving the amplified electrical signal from the transimpedance amplifier and for generating, from the amplified electrical signal, an output signal including corrections for the inter symbol interference in the amplified electrical signal effectively increasing a bandwidth of the optical receiver. | 09-06-2012 |
| 20120242383 | PHASE PROFILE GENERATOR - Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile. | 09-27-2012 |
| 20120262149 | LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS - A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL. | 10-18-2012 |
| 20120313704 | DIFFERENTIAL AMPLIFIER STAGE WITH INTEGRATED OFFSET CANCELLATION CIRCUIT - A differential amplifier stage and method for offset cancellation include an amplifier having an input and an output. An internal offset cancellation circuit has an input for receiving a control signal to control offset cancellation in the amplifier. The offset cancellation circuit is integrated with the amplifier but isolated from the input and the output of the amplifier, and, in accordance with its isolation, an impedance of the stage is unaffected by the offset cancellation circuit. | 12-13-2012 |
| 20120319805 | LOW DISTORTION HIGH BANDWIDTH ADAPTIVE TRANSMISSION LINE FOR INTEGRATED PHOTONIC APPLICATIONS - A transmission line and method for implementing includes a plurality of segments forming an electrical path and a continuous optical path passing through the segments. Discrete inductors are formed between and connect adjacent segments. The inductors are formed in a plurality of metal layers of an integrated circuit to balance capacitance of an optical modulator which includes the transmission line to achieve a characteristic impedance for the transmission line. | 12-20-2012 |
| 20130057327 | REDUCING PHASE LOCKED LOOP PHASE LOCK TIME - There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected. | 03-07-2013 |
| 20130057348 | Transimpedance Amplifier - A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal. | 03-07-2013 |
| 20130063218 | FULLY DECOUPLED LC-TANK BASED OSCILLATOR TOPOLOGY FOR LOW PHASE NOISE AND HIGH OSCILLATION AMPLITUDE APPLICATIONS - There is provided a tank based oscillator. The oscillator includes one or more active devices, one or more passive devices, and a tank circuit decoupled from the active devices using at least one of the one or more passive devices. A coupling ratio between the tank circuit and the one or more active devices is set such that a maximum value of an oscillation amplitude of the tank circuit is limited based upon a breakdown of only the one or more passive devices. | 03-14-2013 |
| 20130076449 | VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING - Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering. | 03-28-2013 |
| 20130142211 | PARALLEL OPTICAL TRANSCEIVER MODULE - A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer. | 06-06-2013 |
| 20130181233 | SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER - Processing for a silicon photonics wafer is provided. A silicon photonics wafer that includes an active silicon photonics layer, a thin buried oxide layer, and a silicon substrate is received. The thin buried oxide layer is located between the active silicon photonics layer and the silicon substrate. An electrical CMOS wafer that includes an active electrical layer is also received. The active silicon photonics layer of the silicon photonics wafer is flip chip bonded to the active electrical layer of the electrical CMOS wafer. The silicon substrate is removed exposing a backside surface of the thin buried oxide layer. A low-optical refractive index backing wafer is added to the exposed backside surface of the thin buried oxide layer. The low-optical refractive index backing wafer is a glass substrate or silicon substrate wafer. The silicon substrate wafer includes a thick oxide layer that is attached to the thin buried oxide layer. | 07-18-2013 |
| 20130214135 | OPTICAL RECEIVER USING INFINITE IMPULSE RESPONSE DECISION FEEDBACK EQUALIZATION - A technique is provided for configuring an optical receiver. A photo detector is connected to a load resistor, and the photo detector includes an internal capacitance. A current source is connected through a switching circuit to the load resistor and to the photo detector. The current source is configured to discharge the internal capacitance of the photo detector. The switching circuit is configured to connect the current source to the internal capacitance based on a previous data bit. | 08-22-2013 |
| 20130216241 | OPTICAL RECEIVER USING INFINITE IMPULSE RESPONSE DECISION FEEDBACK EQUALIZATION - A technique is provided for configuring an optical receiver. A photo detector is connected to a load resistor, and the photo detector includes an internal capacitance. A current source is connected through a switching circuit to the load resistor and to the photo detector. The current source is configured to discharge the internal capacitance of the photo detector. The switching circuit is configured to connect the current source to the internal capacitance based on a previous data bit. | 08-22-2013 |
| 20130229236 | OPTICAL RECEIVER BASED ON A DECISION FEEDBACK EQUALIZER - An optical receiver, a method of operating an optical receiver, a correction based transimpedance amplifier circuit, and a method of adjusting an output of a transimpedance amplifier. In one embodiment, the optical receiver comprises an optical-to-electrical converter, a transimpedance amplifier, and a correction circuit. The optical-to-electrical converter is provided for receiving an optical signal and converting the optical signal to an electrical signal. The transimpedance amplifier is provided for receiving the electrical signal from the converter and for generating from the electrical signal an amplified electrical signal. The amplified electrical signal has inter symbol interference resulting from a reduced bandwidth of the transimpedance amplifier. The correction circuit is provided for receiving the electrical signal from the amplifier and for generating, from the electrical signal, an output signal including corrections for the inter symbol interference in the amplified electrical signal effectively increasing a bandwidth of the optical receiver. | 09-05-2013 |
| 20130271217 | DIFFERENTIAL AMPLIFIER STAGE WITH INTEGRATED OFFSET CANCELLATION CIRCUIT - A differential amplifier stage and method for offset cancellation include an amplifier having an input and an output. An internal offset cancellation circuit has an input for receiving a control signal to control offset cancellation in the amplifier. The offset cancellation circuit is integrated with the amplifier but isolated from the input and the output of the amplifier, and, in accordance with its isolation, an impedance of the stage is unaffected by the offset cancellation circuit. | 10-17-2013 |
| 20130308900 | PARALLEL OPTICAL TRANSCEIVER MODULE - A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer. | 11-21-2013 |
| 20140007030 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20140007032 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20140029949 | OPTICAL DE-MULTIPLEXING DEVICE - An electro-optical device includes an optical de-multiplexing portion operative to output a first optical signal having a first wavelength and a second optical signal having a second wavelength, an array of photodetectors, and a switching logic portion communicatively connected to the array of photodetectors, the switching logic portion operative to determine which photodetector of the array of photodetectors is converting the first optical signal into a first electrical signal and output the first electrical signal from a first output node associated with the first optical signal. | 01-30-2014 |
| 20140029950 | OPTICAL DE-MULTIPLEXING DEVICE - A method for controlling an output of an electro-optical de-multiplexing device, the method including identifying which photodetector of a first array of photodetectors is converting a first channel of an optical signal into a first electrical channel signal, and affecting a communicative connection between the identified photodetector of the first array of photodetectors that is converting the first channel of the optical signal into the first electrical channel signal and a first output node associated with the first electrical channel signal. | 01-30-2014 |
| 20140049323 | TRANSIMPEDANCE AMPLIFIER - A method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal. | 02-20-2014 |
| 20140050436 | PHOTONIC MODULATOR WITH FORWARD-AND REVERSE-BIASED DIODES FOR SEPARATE TUNING AND MODULATING ELEMENTS - A method and structure for a modulator which includes a forward-biased diode optimized for power and area to perform a tuning function, and a reverse-biased diode optimized for speed to perform a modulation function. | 02-20-2014 |
| 20140068534 | Designing Photonic Switching Systems Utilizing Equalized Drivers - Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected from a plurality of switch driver circuits for the photonic switching system. It is determined whether each performance metric associated with the photonic switching system meets or exceeds a threshold value corresponding to each of the plurality of performance metrics based on the photonic switch diode designed and the switch driver circuit selected. In response to determining that each performance metric associated with the photonic switching system meets or exceeds the threshold value corresponding to each of the performance metrics, the photonic switching system is designed using the photonic switch diode designed and the switch driver circuit selected. | 03-06-2014 |
| 20140070855 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
| 20140070856 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
