Patent application number | Description | Published |
20120003819 | Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material - The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions. | 01-05-2012 |
20120305940 | Defect Free Si:C Epitaxial Growth - A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain. | 12-06-2012 |
20130069159 | Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack. | 03-21-2013 |
20130071979 | Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack. | 03-21-2013 |
20130207226 | RECESSED DEVICE REGION IN EPITAXIAL INSULATING LAYER - A method for isolating semiconductor devices is described wherein an epitaxial insulating layer is grown on a semiconductor substrate. The epitaxial insulating layer is etched to form a recessed region within the layer. An epitaxial semiconductor material is grown with the recessed region to form a semiconductor device region separated from other potential device regions by non-recessed portions of the epitaxial insulating layer. | 08-15-2013 |
20130270655 | SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures. | 10-17-2013 |
20130285123 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 10-31-2013 |
20130307076 | METHOD AND STRUCTURE FOR FORMING FIN RESISTORS - A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits. | 11-21-2013 |
20130334571 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 12-19-2013 |
20140001554 | SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE | 01-02-2014 |
20140001561 | CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE | 01-02-2014 |
20140015014 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 01-16-2014 |
20140027863 | MERGED FIN FINFET WITH (100) SIDEWALL SURFACES AND METHOD OF MAKING SAME - A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate. | 01-30-2014 |
20140038369 | METHOD OF FORMING FIN-FIELD EFFECT TRANSISTOR (finFET) STRUCTURE - Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins. | 02-06-2014 |
20140042547 | HIGH DENSITY BULK FIN CAPACITOR - A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors. | 02-13-2014 |
20140061820 | BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height. | 03-06-2014 |
20140070277 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350 C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 03-13-2014 |
20140080275 | Multigate FinFETs with Epitaxially-Grown Merged Source/Drains - Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region. | 03-20-2014 |
20140097518 | SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR - Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins. | 04-10-2014 |
20140103331 | Embedded Source/Drains with Epitaxial Oxide Underlayer - Semiconductor structures having embedded source/drains with oxide underlayers and methods for forming the same. Embodiments include semiconductor structures having a channel in a substrate, and a source/drain region adjacent to the channel including an embedded oxide region and an embedded semiconductor region located above the embedded oxide region. Embodiments further include methods of forming a transistor structure including forming a gate on a substrate, etching a source/drain recess in the substrate, filling a bottom portion of the source/drain recess with an oxide layer, and filling a portion of the source/drain recess not filled by the oxide layer with a semiconductor layer. | 04-17-2014 |
20140103451 | FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS - A fin field-effect transistor (finFET) assembly includes a first finFET device having fins of a first height and a second finFET device having fins of a second height. Each of the first and second finFET devices includes an epitaxial fill material covering source and drain regions of the first and second finFET devices. The epitaxial fill material of the first finFET device has a same height as the epitaxial fill material of the second finFET device. | 04-17-2014 |
20140106528 | FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS - A method of forming a fin field effect transistor (finFET) includes forming a plurality of fins of varying heights on a substrate and forming a first gate structure on one or more fins of a first height to form a first finFET structure and a second gate structure on one or more fins of a second height to form a second finFET structure. The method includes epitaxially forming an epitaxial fill material on the one or more fins of the first finFET structure and the second finFET structure. The epitaxial fill material of the first finFET structure has a same height as the epitaxial fill material of the second finFET structure. | 04-17-2014 |
20140117422 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 05-01-2014 |
20140124840 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 05-08-2014 |
20140141587 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 05-22-2014 |
20140145270 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 05-29-2014 |
20140145271 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 05-29-2014 |
20140159124 | EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION - A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A dummy gate can establish the position of the abrupt interfaces and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel, or to overlap the extension tip. | 06-12-2014 |
20140162452 | BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS - Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole. | 06-12-2014 |
20140167163 | Multi-Fin FinFETs with Epitaxially-Grown Merged Source/Drains - Embodiments include multi-fin finFET structures with epitaxially-grown merged source/drains and methods of forming the same. Embodiments may include an epitaxial insulator layer above a base substrate, a gate structure above the epitaxial insulator layer, a semiconductor fin below the gate structure, and an epitaxial source/drain region grown on the epitaxial insulator layer adjacent to an end of the semiconductor fin. The epitaxial insulator layer may be made of an epitaxial rare earth oxide material grown on a base semiconductor substrate. Embodiments may further include fin extension regions on the end of the semiconductor fin between the end of the end of the semiconductor fin and the epitaxial source/drain region. In some embodiments, the end of the semiconductor fin may be recessed below the gate structure. | 06-19-2014 |
20140167164 | DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices. | 06-19-2014 |
20140191286 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140191287 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140191330 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 07-10-2014 |
20140203361 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR FIELD-EFFECT TRANSISTOR WITH AN EPITAXIAL SOURCE AND DRAIN HAVING A LOW EXTERNAL RESISTANCE - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer-on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140203363 | Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance - An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis. | 07-24-2014 |
20140242797 | SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER - A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal. | 08-28-2014 |
20140252427 | Self-aligned Contacts For Replacement Metal Gate Transistors - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 09-11-2014 |
20140256106 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 09-11-2014 |
20140264387 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 09-18-2014 |
20140264594 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264600 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264612 | GROWTH OF EPITAXIAL SEMICONDUCTOR REGIONS WITH CURVED TOP SURFACES - Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls. To further increase the thickness of the epitaxial semiconductor region, the method may cycle between depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls; and removing the amorphous portions on the sidewalls until the combined thickness of all the crystalline portions reaches a desired thickness. | 09-18-2014 |
20140264746 | SELF ALIGNED CAPACITOR FABRICATION - A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer. | 09-18-2014 |
20140273418 | BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline dielectric layer including an epitaxial oxide; forming a semiconductor layer on the crystalline dielectric layer, the semiconductor layer and the crystalline dielectric layer forming an extremely thin semiconductor-on-insulator (ETSOI) structure; and forming a set of devices on the semiconductor layer, wherein at least one device in the set of devices is formed over a doped region. | 09-18-2014 |
20140284719 | METHOD AND STRUCTURE FOR FINFET CMOS - According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal. | 09-25-2014 |
20140302658 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 10-09-2014 |
20140308808 | Replacement Gate Integration Scheme Employing Multiple Types of Disposable Gate Structures - A plurality of disposable gate materials is employed to form multiple types of disposable gate stack structures. Different types of disposable gate stack structures are sequentially removed and replaced with different types of replacement gate stack structures. Sequential removal of the different types of disposable gate stack structures can be effected by employing etch chemistries that remove one type of disposable gate material while not etching at least another type of disposable gate material. Different types of replacement gate stack structures can employ different work function materials. Lithographic patterning of workfunction materials is avoided, and each replacement gate stack structure can have a workfunction material portion having a uniform thickness. | 10-16-2014 |
20140312419 | FINFET DEVICES CONTAINING MERGED EPITAXIAL FIN-CONTAINING CONTACT REGIONS - A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers. | 10-23-2014 |
20140312425 | FINFET WITH CRYSTALLINE INSULATOR - FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region. | 10-23-2014 |
20140327054 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 11-06-2014 |
20140327058 | SELF-ALIGNED CONTACTS FOR REPLACEMENT METAL GATE TRANSISTORS - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 11-06-2014 |
20140329380 | FORMATION OF SEMICONDUCTOR STRUCTURES WITH VARIABLE GATE LENGTHS - A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width. | 11-06-2014 |
20140339638 | INTEGRATING CHANNEL SIGE INTO PFET STRUCTURES - A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer. | 11-20-2014 |
20140339643 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS - A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region. | 11-20-2014 |
20140346573 | SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES, RELATED DESIGN STRUCTURE AND METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines. | 11-27-2014 |
20140346587 | INTEGRATED CIRCUIT HAVING MOSFET WITH EMBEDDED STRESSOR AND METHOD TO FABRICATE SAME - A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140346600 | Integrated Circuit Having MOSFET with Embedded Stressor and Method to Fabricate Same - A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140346612 | BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES - A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices. | 11-27-2014 |
20140353714 | METHODS FOR MAKING A SEMICONDUCTOR DEVICE WITH SHAPED SOURCE AND DRAIN RECESSES AND RELATED DEVICES - A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack. | 12-04-2014 |
20140353721 | BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height. | 12-04-2014 |
20140353732 | HALO REGION FORMATION BY EPITAXIAL GROWTH - A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device. | 12-04-2014 |
20140353752 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY BACKGROUND - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140357034 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140361314 | SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR - Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins. | 12-11-2014 |
20140361338 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20140361368 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20140367752 | TRANSISTOR HAVING ALL-AROUND SOURCE/DRAIN METAL CONTACT CHANNEL STRESSOR AND METHOD TO FABRICATE SAME - An intermediate transistor structure includes a fin structure disposed on a surface of an insulating layer. The fin structure has a gate structure disposed thereon between first and second ends of the fin structure. A first portion of the fin structure is a first doped portion that is disposed over a first recess in the surface of the insulating layer and a second portion of the fin structure is a second doped portion disposed over a second recess in the surface of the insulating layer. The intermediate transistor structure further includes source and drain metal disposed around the first and second doped portions, each inducing one of compression strain or tensile strain in a portion of the fin structure that is disposed within the gate structure and that functions during operation of the transistor as a channel of the transistor. | 12-18-2014 |
20140367781 | LATERAL DIODE COMPATIBLE WITH FINFET AND METHOD TO FABRICATE SAME - A method to fabricate a diode device includes providing a fin structure formed in a SOI layer. The fin structure has a sacrificial gate structure disposed on the fin structure between a first end of the fin structure and a second end of the fin structure. The method further includes depositing first doped semiconductor material on the first and second ends of the fin structure, where the first doped semiconductor material on the first end of the fin structure has one of the same doping polarity or an opposite doping polarity as the first doped semiconductor material on the second end of the fin structure. The method further includes removing the sacrificial gate structure to form a gap between the deposited first doped semiconductor material; depositing a second doped semiconductor material within the gap and forming first and second electrical contacts conductively connected to the first doped semiconductor material. | 12-18-2014 |
20140367782 | Lateral Diode Compatible with FinFET and Method to Fabricate Same - A structure includes a fin having first end and second ends and a substantially intrinsic portion between the first and second ends. The structure further includes a first region of doped semiconductor material disposed on the first end of the fin and a second region of doped semiconductor material disposed on the second end of the fin. The first region has one of the same doping polarity or an opposite doping polarity as the second region. The structure also includes a third region of doped semiconductor material disposed on the intermediate portion of the fin adjacent to the first region and the second region. The third region has a doping polarity that differs from the doping polarity of at least one of the first and second regions and forms a p-n junction with the at least one of the first and second regions. | 12-18-2014 |
20140374796 | SEMICONDUCTOR STRUCTURE WITH ASPECT RATIO TRAPPING CAPABILITIES - A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance. | 12-25-2014 |
20140377927 | SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE - A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. | 12-25-2014 |
20150028454 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 01-29-2015 |
20150035064 | INVERSE SIDE-WALL IMAGE TRANSFER - Methods forming structures on a chip. The methods include etching a mandrel layer that is disposed over a bottom layer to be patterned to form gaps between plateaus of mandrel material; forming spacers on sidewalls of the plateaus; forming a hardmask material in gaps between the spacers; removing the spacers to define a pattern around the hardmask material; and etching the bottom layer according to the pattern around the hardmask material. | 02-05-2015 |
20150035081 | INVERSE SIDE-WALL IMAGE TRANSFER - Semiconductor devices include a set of fin field effect transistors (FETs), each having a fin structure formed from a monocrystalline substrate. A trench between fin structures of respective fin FETs is formed by a cut in the monocrystalline substrate that has a width smaller than a width of the fin structures and that penetrates less than a full depth of the monocrystalline substrate. The trenches have a width smaller than a minimum pitch of a lithographic technology employed. | 02-05-2015 |
20150041853 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material. Following implantation of a cleavage layer and wafer bonding to a handle wafer, the layer of desired compound semiconductor material is fractured along the cleavage layer and the residual portion thereof removed. A layer of the desired compound semiconductor material is then regrown on the epitaxial oxide layer. | 02-12-2015 |
20150041856 | Compound Semiconductor Integrated Circuit and Method to Fabricate Same - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. | 02-12-2015 |
20150041908 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 02-12-2015 |
20150044859 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. Methods to form the structure are also disclosed. | 02-12-2015 |
20150054032 | METHODS FOR MAKING A SEMICONDUCTOR DEVICE WITH SHAPED SOURCE AND DRAIN RECESSES AND RELATED DEVICES - A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack. | 02-26-2015 |
20150056792 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 02-26-2015 |
20150060944 | DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices. | 03-05-2015 |
20150060981 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150061010 | STRUCTURE FOR IMPROVED CONTACT RESISTANCE AND EXTENSION DIFFUSION CONTROL - Semiconductor structures are provided including a raised source region comprising, from bottom to top, a source-side phosphorus doped epitaxial semiconductor material portion and a source-side arsenic doped epitaxial semiconductor material portion and located on one side of a gate structure, and a raised drain region comprising from bottom to top, a drain-side phosphorus doped epitaxial semiconductor material portion and a drain-side arsenic doped epitaxial semiconductor material portion and located on another side of the gate structure. | 03-05-2015 |
20150061021 | SEMI-CONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE - A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region. | 03-05-2015 |
20150061076 | HIGH DENSITY RESISTOR - At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin. A polysilicon resistor is formed on exposed surfaces of the dielectric material and surrounding the at least one semiconductor fin. An interconnect dielectric material is formed above the polysilicon resistor. The interconnect dielectric material has at least one contact structure that extends through the interconnect dielectric to an upper surface of the polysilicon resistor. | 03-05-2015 |
20150064891 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150069327 | FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS - FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin. | 03-12-2015 |
20150069465 | HIGH PERCENTAGE SILICON GERMANIUM ALLOY FIN FORMATION - A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided. | 03-12-2015 |
20150069521 | NANOWIRE COMPATIBLE E-FUSE - An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion. | 03-12-2015 |
20150069527 | FINFET DEVICE HAVING A MERGED SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other. | 03-12-2015 |
20150069531 | LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS - A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region. | 03-12-2015 |
20150076561 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer. | 03-19-2015 |
20150076606 | SEMICONDUCTOR DEVICE WITH LOW-K SPACER - A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner. | 03-19-2015 |
20150083999 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084001 | GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084101 | MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES - A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate. | 03-26-2015 |
20150087120 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 03-26-2015 |