Patent application number | Description | Published |
20090111228 | SELF ALIGNED RING ELECTRODES - The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed. | 04-30-2009 |
20090189139 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 07-30-2009 |
20090194757 | PHASE CHANGE ELEMENT EXTENSION EMBEDDED IN AN ELECTRODE - The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening. | 08-06-2009 |
20090230377 | Phase Change Materials for Applications that Require Fast Switching and High Endurance - A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material. | 09-17-2009 |
20090239334 | ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK - A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material. | 09-24-2009 |
20090268507 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURE - A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode. | 10-29-2009 |
20090275168 | PHASE CHANGE MATERIAL WITH FILAMENT ELECTRODE - The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode. | 11-05-2009 |
20090298223 | SELF-ALIGNED IN-CONTACT PHASE CHANGE MEMORY DEVICE - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode. | 12-03-2009 |
20090305492 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 12-10-2009 |
20100009164 | PROCESS FOR CHEMICAL VAPOR DEPOSITION OF MATERIALS WITH VIA FILLING CAPABILITY AND STRUCTURE FORMED THEREBY - A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials. | 01-14-2010 |
20100048020 | Nanoscale Electrodes for Phase Change Memory Devices - A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions. | 02-25-2010 |
20100054029 | CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device. | 03-04-2010 |
20100078617 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 04-01-2010 |
20100078621 | METHOD TO REDUCE RESET CURRENT OF PCM USING STRESS LINER LAYERS - A memory cell structure and method for forming the same. The method includes forming a via within a dielectric layer. The via is formed over the center of an electrically conducting bottom electrode. The method includes depositing a stress liner along at least one sidewall of the via. The stress liner imparting stress on material proximate the stress liner. In one embodiment, the stress liner provides a stress in the range of 500 to 5000 MPa on the material enclosed within its volume. The method includes depositing phase change material within the via and the volume enclosed by the stress liner. The method also includes forming an electrically conducting top electrode above the phase change material. | 04-01-2010 |
20100301409 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 12-02-2010 |
20110001111 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 01-06-2011 |
20110037042 | PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell. | 02-17-2011 |
20110049462 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 03-03-2011 |
20110057162 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 03-10-2011 |
20110186800 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 08-04-2011 |
20110193045 | POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material. | 08-11-2011 |
20110227021 | POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example apparatus includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer, including phase change material, is disposed over the bottom electrode. A thermal insulating layer is disposed above the phase change layer. A heater is configured to temporarily melt the phase change material such that the phase change material crystallizes without voids within a switching region after melting. | 09-22-2011 |
20110240944 | PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell. | 10-06-2011 |
20110275209 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 11-10-2011 |
20120112154 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 05-10-2012 |
20120115302 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 05-10-2012 |
20120126194 | THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120129313 | THERMALLY INSULATED PHASE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120134204 | CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device. | 05-31-2012 |
20120147666 | PHASE CHANGE MATERIAL CELL WITH STRESS INDUCER LINER - An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material. | 06-14-2012 |
20120202333 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 08-09-2012 |
20120267601 | PHASE CHANGE MEMORY CELLS WITH SURFACTANT LAYERS - An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. | 10-25-2012 |
20120276688 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 11-01-2012 |
20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 11-08-2012 |
20120309159 | METHOD TO SELECTIVELY GROW PHASE CHANGE MATERIAL INSIDE A VIA HOLE - An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode. | 12-06-2012 |
20130001500 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 01-03-2013 |
20130087756 | HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner. | 04-11-2013 |
20130119339 | MEMORY CELL WITH POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - A phase change memory cell with substantially void free crystalline phase change material. An example memory cell includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer includes phase change material. The phase change layer is void free within a switching region when the phase change material is in a crystalline phase. A top electrode is positioned over the phase change layer. | 05-16-2013 |
20130299768 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material. | 11-14-2013 |
20130309782 | PHASE CHANGE MATERIAL CELL WITH PIEZOELECTRIC OR FERROELECTRIC STRESS INDUCER LINER - An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD). | 11-21-2013 |
20140154862 | UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material. | 06-05-2014 |
20140158971 | PHASE CHANGE MEMORY CELLS WITH SURFACTANT LAYERS - An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. | 06-12-2014 |
20140166962 | PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA - A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. | 06-19-2014 |
20140170831 | PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA - A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. | 06-19-2014 |
20140252117 | CONTROLLABLE EMITTER - A controllable emitter of an irrigation apparatus including a drip line having pressurized fluid therein is provided. The controllable emitter includes a container coupled to the drip line, the container being formed to define an interior and including an inlet through which the pressurized fluid is receivable in the interior from the drip line and an outlet through which the pressurized fluid is exhaustible from the interior, a magnetic stopper, which is normally disposable in a first position such that the magnetic stopper prevents a flow of the pressurized fluid through the outlet and which is actively disposable in a second position such that the magnetic stopper permits the flow and a controllable actuator configured to generate a magnetic field operable to urge the magnetic stopper to move from the first position to the second position. | 09-11-2014 |
20140252133 | CONTROLLABLE EMITTER - A controllable emitter of an irrigation apparatus including a drip line and a control station configured to control a pressure of pressurized fluid in the drip line is provided. The controllable emitter is disposable along the drip line and includes a container coupled to the drip line, the container being formed to define an interior and including an inlet through which the pressurized fluid is receivable in the interior from the drip line and an outlet through which the pressurized fluid is exhaustible from the interior, a piston, including a magnetic element, disposed at least partially in the container to occupy a position in accordance with the pressure of the pressurized fluid and a sensor configured to sense a position of the magnetic element and to communicate a sensed position to the control station. | 09-11-2014 |
20140252294 | PHASE CHANGE MEMORY CELL WITH HEAT SHIELD - A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode. | 09-11-2014 |
20150044426 | CATALYTIC ETCH WITH MAGNETIC DIRECTION CONTROL - A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction. | 02-12-2015 |