Patent application number | Description | Published |
20100328826 | Field Effect Resistor for ESD Protection - An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers ( | 12-30-2010 |
20120003818 | Field Effect Resistor for ESD Protection - An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers ( | 01-05-2012 |
20130193491 | Field Controlled Diode with Positively Biased Gate - An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described. | 08-01-2013 |
20130214616 | TRANSMISSION LINE PULSING - A circuit and method for electrostatic discharge testing using transmission line pulsing. A plurality of transmission line networks may be connected to a device under test, and each transmission line network may have different connected terminations. Switches may be used to select which transmission line networks are connected to the device under test, and which terminations, if any, are connected to transmission line networks. | 08-22-2013 |
20130264640 | DRAIN EXTENDED MOS TRANSISTOR HAVING SELECTIVELY SILICIDED DRAIN - A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free. | 10-10-2013 |
20130285113 | BIDIRECTIONAL ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains. | 10-31-2013 |
20130320396 | MUTUAL BALLASTING MULTI-FINGER BIDIRECTIONAL ESD DEVICE - An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node. | 12-05-2013 |
20140054642 | ESD PROTECTION DEVICE WITH IMPROVED BIPOLAR GAIN USING CUTOUT IN THE BODY WELL - An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor. | 02-27-2014 |
20140087530 | Field Controlled Diode With Positively Biased Gate - An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described. | 03-27-2014 |
20140106524 | DIODE ISOLATED DRAIN EXTENDED NMOS ESD CELL - An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed. | 04-17-2014 |
20140124828 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 05-08-2014 |