Aik
Ang Boon Aik, Santa Clara, CA US
Patent application number | Description | Published |
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20090109742 | CONTROL OF TEMPERATURE SLOPE FOR BAND GAP REFERENCE VOLTAGE IN A MEMORY DEVICE - Systems and/or methods are presented that can facilitate regulating performance of operations in a memory device based on controlling an operating temperature slope associated with the memory device. A regulator component can facilitate controlling the operating temperature slope level and controlling a reference voltage(s) associated with a word-line(s) and/or bit-line(s) to facilitate execution of operations in a memory, while also controlling a respective current level(s) associated with the reference voltage to minimize errors in the memory or harm to the memory. The reference voltage can be controlled based on a first resistance and the current level can be controlled based on a second resistance that can be based on the first resistance. An analyzer component can facilitate determining a desired operating temperature slope level. Trim bits can be employed to facilitate setting the first resistance and/or the second resistance. | 04-30-2009 |
Ooi Ooi Aik, Santa Clara, CA US
Patent application number | Description | Published |
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20130246644 | WIRELESS ENHANCED PROJECTOR - Described herein are techniques related to a wireless enhanced projector (WEP) that is utilized by one or more devices, such as a mobile phone, a cellular phone, a Smartphone, a personal digital assistant, a tablet computer, and the like. In an implementation, the one or more devices may connect to the WEP through a server device that may be connected and/or integrated with the WEP. In this implementation, at least one of the one or more devices may be configured to be a super-user device (i.e., moderator or administrator device), while the rest of the one or more devices may be regular client devices. | 09-19-2013 |
Weng Shyan Aik, Tampin MY
Patent application number | Description | Published |
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20090250797 | Multi-Chip Package - A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area. | 10-08-2009 |