Patent application number | Description | Published |
20130036295 | GPU ASSISTED GARBAGE COLLECTION - A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. | 02-07-2013 |
20130042096 | DISTRIBUTED MULTI-CORE MEMORY INITIALIZATION - In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks. | 02-14-2013 |
20130058440 | METHOD TO REDUCE PEAK TO AVERAGE POWER RATIO IN MULTI-CARRIER MODULATION RECEIVERS - A method for performing channel estimation in an orthogonal frequency division multiplexing (OFDM) signal includes choosing reserved tones to be part of a pilot pattern, and using the reserved tones in the pilot pattern to perform the channel estimation. An apparatus for use in performing channel estimation in an OFDM system includes a receiver configured to receive a transmitted OFDM signal; a pilot symbol extractor configured to extract pilot symbols from the OFDM signal; and a channel estimator configured to perform the channel estimation, including using reserved tones as pilot tones. | 03-07-2013 |
20130069964 | METHOD AND APPARATUS FOR PROVIDING COMPLIMENTARY STATE RETENTION - A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory. | 03-21-2013 |
20130071097 | EFFICIENT VIDEO DECODING MIGRATION FOR MULTIPLE GRAPHICS PROCESSOR SYSTEMS - A method for switching decoding and rendering of a digital video stream from a first graphics processing unit (GPU) to a second GPU. The digital video stream is evaluated to determine an amount of time until a next intra-coded frame (I-frame) in the digital video stream. If the amount of time is below a threshold, decoding and rendering of the digital video stream is switched to the second GPU on the next I-frame in the digital video stream and decoding the digital video stream by the first GPU is stopped. If the amount of time is above the threshold, the digital video stream is decoded on both the first GPU and the second GPU, the rendering of the digital video stream is switched to the second GPU, and decoding the digital video stream by the first GPU is stopped. | 03-21-2013 |
20130072014 | Method for Forming Contact in an Integrated Circuit - A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and forming a cap over the nanotubes. | 03-21-2013 |
20130083048 | INTEGRATED CIRCUIT WITH ACTIVE MEMORY AND PASSIVE VARIABLE RESISTIVE MEMORY WITH SHARED MEMORY CONTROL LOGIC AND METHOD OF MAKING SAME - An integrated circuit includes, in one example, an active memory cell array and a passive variable resistance memory cell array positioned above the active memory cell array, such as in upper layers of the integrated circuit. The active memory cell array and the passive variable resistance memory cell array share one or more components of memory control logic such as address decode logic, data read logic and/or data write logic. As such, a type of active memory and passive variable resistance memory hybrid structure shares memory control logic such as word line drivers, bit line drivers and read logic. The active memory cell array and passive variable resistance memory cell array overlap reducing integrated circuit die size, improving power reduction and reducing costs by sharing peripheral circuits. | 04-04-2013 |
20130094775 | REGION-BASED IMAGE COMPRESSION - A method for compressing an image includes decomposing the image into one or more regions. A region of the image is selected to be evaluated. The selected region is transformed and quantized if the region does not meet a predetermined compression acceptability criteria. The predetermined compression acceptability criteria may include a specific bit rate, a specific image quality, or combinations thereof. If the region does not meet the predetermined compression acceptability criteria after the region has been transformed and quantized, then the transformation and quantization settings are adjusted and the region is transformed and quantized using the adjusted settings. The region is then encoded when the predetermined compression acceptability criteria has been reached. The encoding may include additional compression stages. | 04-18-2013 |
20130103908 | PREVENTING UNINTENDED LOSS OF TRANSACTIONAL DATA IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction. | 04-25-2013 |
20130113818 | IMAGE QUALITY CONFIGURATION APPARATUS, SYSTEM AND METHOD - A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed. | 05-09-2013 |
20130114711 | SYSTEM FOR PARALLEL INTRA-PREDICTION DECODING OF VIDEO DATA - A system for decoding video data includes a processing unit. The processing unit includes a plurality of processing pipelines and a driver. The driver includes a decoder configured to generate a plurality of intermediate control maps containing control information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the plurality of processing pipelines. | 05-09-2013 |
20130124806 | DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers. | 05-16-2013 |
20130130487 | Integrated Circuit with Metal and Semi-Conducting Gate - A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess. | 05-23-2013 |
20130138568 | FINANCIAL TRANSACTION SYSTEM - A system and method for conducting a financial transaction is disclosed. The system includes a first memory location embedded in a personal portable device. The first memory location stores a plurality of personal financial data files associated with a user. The system also includes a second memory location to store biometric information and a first input interface to receive authentication information after initiation of a purchase transaction session. The system also includes a security module including an input coupled to the first interface to authenticate the authentication information based on the biometric information and an output interface comprising an input coupled to the first memory location and an output to provide personal financial data file information to a host device. | 05-30-2013 |
20130140720 | VOID FREE INTERLAYER DIELECTRIC - A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids. | 06-06-2013 |
20130155065 | SYSTEM AND METHOD FOR CREATING MOTION BLUR - An embedded, programmable motion blur system and method is described. Embodiments include receiving a plurality of vertices in a graphics processing unit (GPU), displacing at least one vertex, receiving a primitive defined by at least one of the displaced vertices, and generating a plurality of primitive samples from the primitive. The receiving of a plurality of vertices, the displacing, the receiving a primitive, and the generating are all performed prior to rendering of the scene. The system includes a central processing unit (CPU), a memory unit coupled to the CPU, and at least one programmable GPU. The GPU includes a vertex shader and a geometry shader programmable to perform geometry amplification and generate a plurality of primitive samples, both of these performed before the scene is rendered. | 06-20-2013 |
20130157432 | ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE - Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided. | 06-20-2013 |
20130161695 | REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability. | 06-27-2013 |
20130163131 | ELECTRONIC COMPONENT PROTECTION POWER SUPPLY CLAMP CIRCUIT - Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering. This also lengthens the time that the clamp circuit remains in the ESD-triggered state during human body model (HBM) or other long duration detected ESD events. | 06-27-2013 |
20130169636 | Accelerated Compute Tessellation by Compact Topological Data Structure - A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation. | 07-04-2013 |
20130179884 | Saving, Transferring and Recreating GPU Context Information Across Heterogeneous GPUs During Hot Migration of a Virtual Machine - A system and method are disclosed for recreating graphics processing unit (GPU) state information associated with a migrated virtual machine (VM). A VM running on a first VM host coupled to a first graphics device, comprising a first GPU, is migrated to a second VM host coupled to a second graphics device, in turn comprising a second GPU. A context module coupled to the first GPU reads its GPU state information in its native GPU state representation format and then converts the GPU state information into an intermediary GPU state representation format. The GPU state information is conveyed in the intermediary GPU state representation format to the second VM host, where it is received by a context module coupled to the second GPU. The context module converts the GPU state information related to the first GPU from the intermediary GPU state representation format to the native GPU state representation format of the second GPU. Once converted, the GPU state information of the first GPU is restored to the second GPU in its native GPU state representation format. | 07-11-2013 |
20130182069 | 3D VIDEO PROCESSING - A method, an apparatus, and a non-transitory computer readable medium for performing 2D to 3D conversion are presented. A 2D input source is extracted into left and right 3D images. Motion vectors are calculated for the left and right 3D images. Frame rate conversion is performed on the left 3D image and the right 3D image, using the respective calculated motion vectors, to produce motion compensated left and right 3D images. The left and right 3D images and the motion compensated left and right 3D images are reordered for display. | 07-18-2013 |
20130205179 | INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. | 08-08-2013 |