Patent application number | Description | Published |
20080217645 | Thick nitride semiconductor structures with interlayer structures and methods of fabricating thick nitride semiconductor structures - A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 μm. | 09-11-2008 |
20080220555 | Nitride semiconductor structures with interlayer structures and methods of fabricating nitride semiconductor structures with interlayer structures - A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 μm. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer. | 09-11-2008 |
20080302298 | Highly Uniform Group III Nitride Epitaxial Layers on 100 Millimeter Diameter Silicon Carbide Substrates - A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent. | 12-11-2008 |
20090042345 | Methods of Fabricating Transistors Having Buried N-Type and P-Type Regions Beneath the Source Region - High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided. | 02-12-2009 |
20090101939 | Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V | 04-23-2009 |
20090272984 | Silicon Carbide on Diamond Substrates and Related Devices and Methods - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. | 11-05-2009 |
20100012952 | Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same - High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer. | 01-21-2010 |
20100068855 | Group III nitride semiconductor devices with silicon nitride layers and methods of manufacturing such devices - Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer. | 03-18-2010 |
20100187570 | Heterojunction Transistors Having Barrier Layer Bandgaps Greater Than Channel Layer Bandgaps and Related Methods - A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed. | 07-29-2010 |
20110064105 | SILICON CARBIDE ON DIAMOND SUBSTRATES AND RELATED DEVICES AND METHODS - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. | 03-17-2011 |
20110114968 | Integrated Nitride and Silicon Carbide-Based Devices - A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed. | 05-19-2011 |
20110136305 | Group III Nitride Semiconductor Devices with Silicon Nitride Layers and Methods of Manufacturing Such Devices - Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer. | 06-09-2011 |
20110140083 | Semiconductor Device Structures with Modulated Doping and Related Methods - A semiconductor device may include a doped semiconductor region having a modulated dopant concentration. The doped semiconductor region may be a silicon doped Group III nitride semiconductor region with a dopant concentration of silicon being modulated in the Group III nitride semiconductor region. In addition, a semiconductor active region may be configured to generate light responsive to an electrical signal therethrough. Related methods, devices, and structures are also discussed. | 06-16-2011 |
20110233521 | SEMICONDUCTOR WITH CONTOURED STRUCTURE - The present disclosure relates to a semiconductor device that has a first semiconductor structure that is grown to form a non-planar growth surface. The non-planar growth surface is formed from multiple facets and provides a defined contour. The defined contour may include, but is not limited to a corrugated contour or a pyramidal contour. A second semiconductor structure is grown over the non-planar growth surface of the first semiconductor structure, and as such, the second semiconductor structure is non-planar and follows the defined contour of the non-planar growth surface of the first semiconductor structure. The first and second semiconductor structures may form the foundation for various types of electrical and optoelectrical semiconductor devices, such as diodes, transistors, thyristors, and the like. | 09-29-2011 |
20110312159 | Methods of Fabricating Nitride Semiconductor Structures with Interlayer Structures - A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 μm. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer. | 12-22-2011 |
20120235159 | Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V | 09-20-2012 |
20130306990 | WAFER PRECURSOR PREPARED FOR GROUP III NITRIDE EPITAXIAL GROWTH ON A COMPOSITE SUBSTRATE HAVING DIAMOND AND SILICON CARBIDE LAYERS, AND SEMICONDUCTOR LASER FORMED THEREON - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. | 11-21-2013 |