Patent application number | Description | Published |
20080285435 | INTELLIGENT FAILBACK IN A LOAD-BALANCED NETWORKING ENVIRONMENT - One embodiment of the present invention sets forth a method for failing back network connections to a network interface card (NIC) within a computing device. The method includes the steps of monitoring a failed or unreliable NIC within the computing device, determining that the failed or unreliable NIC has recovered, determining that a functional NIC within the computing device is overloaded, selecting a first connection set communicating through the overloaded NIC, and transferring the first connection set to the recovered NIC. With this approach, intelligent decisions can be advantageously made regarding whether to fail back a network connection set to a recovered NIC based on the traffic loads on the overloaded NIC and the recovered NIC. Such an approach to balancing network traffic across the functional NICs within a computing device may substantially improve overall performance relative to prior art techniques. | 11-20-2008 |
20080285441 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
20080285448 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
20080285472 | INTELLIGENT FAILOVER IN A LOAD-BALANCED NETWORK ENVIRONMENT - A hash table in the network device driver maintains data on the traffic characteristics for each network interface (“NIC”) within a computing device. If one of the NICs in the computing device becomes unreliable, the cost function in the hash engine allows the software driver to initiate network traffic redistribution among the remaining reliable NICs in the computing device. Using this hash engine, the software driver is able to intelligently redirect each of the network connections on an unreliable NIC to a reliable NIC within the computing device, in a way that optimizes the distribution of network traffic across the remaining reliable NICs. Alternatively, if a connection is moved from an old NIC to a new NIC, the software driver can detect the moved connection and offload the moved connection to a hardware offload engine on the new NIC. With this approach, issues such as network interface overloading and computing device performance degradation may be more easily avoided when failing over network connections, thereby improving overall system performance relative to prior art techniques. | 11-20-2008 |
20080285552 | INTELLIGENT FAILOVER IN A LOAD-BALANCED NETWORKING ENVIRONMENT - A hash table in the network device driver maintains data on the traffic characteristics for each network interface (“NIC”) within a computing device. If one of the NICs in the computing device becomes unreliable, the cost function in the hash engine allows the software driver to initiate network traffic redistribution among the remaining reliable NICs in the computing device. Using this hash engine, the software driver is able to intelligently redirect each of the network connections on an unreliable NIC to a reliable NIC within the computing device, in a way that optimizes the distribution of network traffic across the remaining reliable NICs. Alternatively, if a connection is moved from an old NIC to a new NIC, the software driver can detect the moved connection and offload the moved connection to a hardware offload engine on the new NIC. With this approach, issues such as network interface overloading and computing device performance degradation may be more easily avoided when failing over network connections, thereby improving overall system performance relative to prior art techniques. | 11-20-2008 |
20080285553 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
20120155249 | TECHNIQUE FOR IDENTIFYING A FAILED NETWORK INTERFACE CARD WITHIN A TEAM OF NETWORK INTERFACE CARDS - A method for identifying a failed network interface card in a system having two NICs configured as a team includes the steps of transmitting a first data packet from the first NIC to a third NIC, wherein the third NIC is not a member of the team, and transmitting a second data packet from the first NIC to the second NIC or from the second NIC to the third NIC, depending on whether the third NIC responds to the transmission of the first data packet. One advantage of the disclosed method is that it specifically identifies which NIC within the team has failed, which is something that cannot be determined by simply exchanging packets between the two NICs. | 06-21-2012 |
Patent application number | Description | Published |
20080316662 | Reducing input capacitance for high speed integrated circuits - An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed. | 12-25-2008 |
20100149858 | Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 06-17-2010 |
20100291867 | WIRELESS INTERFACE TO PROGRAM PHASE-CHANGE MEMORIES - A Phase-Change Memory (PCM) coupled to receive power provided by near-field coupling to operate the PCM and receive factory programming data entered through the antenna for storage in the PCM. | 11-18-2010 |
20110040909 | HIGH-SPEED WIRELESS SERIAL COMMUNICATION LINK FOR A STACKED DEVICE CONFIGURATION USING NEAR FIELD COUPLING - A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on a memory device substrate or molded into a plastic mold to create near-field magnetic coupling with the stacked memory devices and the memory controller. | 02-17-2011 |
20110307653 | CACHE COHERENCE PROTOCOL FOR PERSISTENT MEMORIES - Subject matter disclosed herein relates to cache coherence of a processor system that includes persistent memory. | 12-15-2011 |
20110307665 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory. | 12-15-2011 |
20120039118 | Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 02-16-2012 |
20130003474 | PROVIDING A READY-BUSY SIGNAL FROM A NON-VOLATILE MEMORY DEVICE TO A MEMORY CONTROLLER - A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 01-03-2013 |
20130031315 | MULTI-DEVICE MEMORY SERIAL ARCHITECTURE - Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller. | 01-31-2013 |
20140009218 | SUPPLY VOLTAGE OR GROUND CONNECTIONS INCLUDING BOND PAD INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICE - Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects. | 01-09-2014 |
20140015133 | SUPPLY VOLTAGE OR GROUND CONNECTIONS FOR INTEGRATED CIRCUIT DEVICE - Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects. | 01-16-2014 |
20140223103 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory. | 08-07-2014 |