| Patent application number | Description | Published |
|---|
| 20110235501 | DEVICE FOR EXCHANGING DATA BETWEEN COMPONENTS OF AN INTEGRATED CIRCUIT - A method for transmitting messages from first units of an integrated circuit to at least one second unit of the integrated circuit. The first units generate first digital messages and transform them into second digital messages obtained by application of an orthogonal or quasi-orthogonal transformation to the first messages. The second messages of the first units are added up and transmitted to the second unit. | 09-29-2011 |
| 20110292784 | Data Exchange Device Using Orthogonal Vectors - An integrated circuit and a method for transmitting messages from initiator units of an integrated circuit to at least one target unit of the integrated circuit. The initiator units transform first digital messages into second digital messages, the second messages being added, then transmitted to the target unit. The transformation of the first messages into second messages comprises the application of an orthogonal transformation by means of vectors obtained from rows or columns of an identity matrix. | 12-01-2011 |
| 20140201406 | METHOD FOR CONTROLLING TRANSACTION EXCHANGES BETWEEN TWO INTEGRATED CIRCUITS - Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed. | 07-17-2014 |
| 20140223211 | Regulating the Activity of a Core - It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S | 08-07-2014 |
| 20140369447 | Resynchronization Method of a Received Stream of Groups of Bits - This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S | 12-18-2014 |
| 20150139420 | Serial transmission having a low level EMI - A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal from the scrambled signal. After each sequence of N consecutive bits at the same state in the scrambled signal, a dummy bit of reverse state is inserted in the outgoing signal. | 05-21-2015 |
| 20150312006 | METHOD FOR MANAGING COMMUNICATIONS BETWEEN TWO DEVICES MUTUALLY CONNECTED VIA A SERIAL LINK, FOR EXAMPLE A POINT-TO-POINT SERIAL INTERFACE PROTOCOL - A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device. | 10-29-2015 |
| 20160072610 | METHODS FOR TRANSMISSION AND RECEPTION OF A SERIAL SIGNAL AND CORRESPONDING DEVICES - A device for transmitting a signal over a serial link includes a transmission processor to carry out, before transmission over the serial link, a scrambling process on successive initial packets of the signal to form a scrambled packet for each initial packet. The transmission processor includes an encoding circuit to carry out an encoding process on each initial packet to deliver an encoded packet. The encoding process includes, for each current initial packet starting from the second, encoding of the current initial packet with the preceding scrambled packet. Calculation circuitry determines, for each initial packet, a bit disparity of the encoded packet and determination of a cumulative bit disparity. Comparison circuitry carries out a comparison process involving the bit disparity of the encoded packet and the cumulative disparity, with the scrambled packet being the encoded packet or the inverted encoded packet, depending on the result of the comparison process. | 03-10-2016 |
