Patent application number | Description | Published |
20090168525 | Flash memory controller having reduced pinout - Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller. | 07-02-2009 |
20090172257 | System and method for performing host initiated mass storage commands using a hierarchy of data structures - Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism. | 07-02-2009 |
20090172258 | Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 07-02-2009 |
20090172259 | Mass storage controller volatile memory containing metadata related to flash memory storage - A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata. | 07-02-2009 |
20090172260 | Flash memory controller and system including data pipelines incorporating multiple buffers - A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts. | 07-02-2009 |
20090172261 | Multiprocessor storage controller - A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously. | 07-02-2009 |
20090172262 | Metadata rebuild in a flash memory controller following a loss of power - A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid. | 07-02-2009 |
20090172263 | Flash storage controller execute loop - In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed. | 07-02-2009 |
20090172308 | Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories - A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors. | 07-02-2009 |
20090172499 | Patrol function used in flash storage controller to detect data errors - A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors. | 07-02-2009 |
20110228601 | MLC SELF-RAID FLASH DATA PROTECTION SCHEME - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 09-22-2011 |
20120072654 | Flash Memory Controller Garbage Collection Operations Performed Independently In Multiple Flash Memory Groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 03-22-2012 |
20120266032 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-18-2012 |
20120266052 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-18-2012 |
20130132804 | Systems, Methods and Devices for Decoding Codewords Having Multiple Parity Segments - An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module. | 05-23-2013 |
20130145229 | Systems, Methods and Devices for Multi-Tiered Error Correction - An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding. | 06-06-2013 |
20130145231 | Data Encoder and Decoder Using Memory-Specific Parity-Check Matrix - An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit. | 06-06-2013 |
20130262753 | Multiprocessor Storage Controller - A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline. | 10-03-2013 |
20130339581 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 12-19-2013 |
20130339582 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 12-19-2013 |
20140101378 | Metadata Rebuild in a Flash Memory Controller Following a Loss of Power - A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid. | 04-10-2014 |
20140108715 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 04-17-2014 |
20140237168 | Mass Storage Controller Volatile Memory Containing Metadata Related to Flash Memory Storage - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 08-21-2014 |
20140281044 | Performance Optimization of Data Transfer for Soft Information Generation - A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values. | 09-18-2014 |