53rd week of 2020 patent applcation highlights part 69 |
Patent application number | Title | Published |
20200411641 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern. | 2020-12-31 |
20200411642 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a nitride semiconductor layer, channel cells in the nitride semiconductor layer, a source lead region of a second conductivity type in the nitride semiconductor layer, and a source electrode on a side where a first main surface of the nitride semiconductor layer is located. The channel cells each include a well region of a first conductivity type and a source region of the second conductivity type in contact with the well region. The source lead region is connected to the source region. The channel cells extend in a first direction in a planar view from a normal direction of the first main surface, and arranged in a second direction intersecting with the first direction in the planar view. The source electrode is in contact with the source lead region away from a line of the channel cells arranged in the second direction. | 2020-12-31 |
20200411643 | SEMICONDUCTOR DEVICE - In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner. | 2020-12-31 |
20200411644 | AMORPHIZATION AND REGROWTH OF SOURCE-DRAIN REGIONS FROM THE BOTTOM-SIDE OF A SEMICONDUCTOR ASSEMBLY - A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel. | 2020-12-31 |
20200411645 | METHOD FOR MAKING SUPERLATTICE STRUCTURES WITH REDUCED DEFECT DENSITIES - A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion. | 2020-12-31 |
20200411646 | SENSOR ELEMENT, MEASURING DEVICE, METHOD FOR MANUFACTURING SENSOR ELEMENT, ELECTRONIC CIRCUIT ELEMENT, AND QUANTUM INFORMATION ELEMENT - A sensor element including a diamond in which nitrogen-vacancy centers in a diamond crystal structure stabilize in a negative charge state. By ensuring that the diamond of the sensor element is n-type phosphorus-doped and contains nitrogen-vacancy centers in the crystal structure, the probability that nitrogen-vacancy centers in the diamond lattice are in a neutral state decreases, and the nitrogen-vacancy centers stabilize in a negative charge state. | 2020-12-31 |
20200411647 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a transistor having a channel region in a gallium nitride-based semiconductor layer. The transistor includes: a gate insulating film provided above the gallium nitride-based semiconductor layer; an intermediate layer arranged between the gallium nitride-based semiconductor layer and the gate insulating film, having a band gap smaller than that of the gate insulating film, and having a band offset with the gallium nitride-based semiconductor layer; a gate electrode provided on the gate insulating film; a first conductivity type source region provided in the gallium nitride-based semiconductor layer; and a source electrode provided on the gallium nitride-based semiconductor layer and being in contact with the source region. The intermediate layer is arranged at a position opposed to the gate electrode through the gate insulating film and avoids a source contact region in which the source electrode is in contact with the source region. | 2020-12-31 |
20200411648 | METAL OXIDE AND TRANSISTOR INCLUDING METAL OXIDE - A novel metal oxide is provided. One embodiment of the present invention is a crystalline metal oxide. The metal oxide includes a first layer and a second layer; the first layer has a wider bandgap than the second layer; the first layer and the second layer form a crystal lattice; and in the case where a carrier is excited in the metal oxide, the carrier is transferred through the second layer. Furthermore, the first layer contains an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and the second layer contains In. | 2020-12-31 |
20200411649 | HEMT AND METHOD OF ADJUSTING ELECTRON DENSITY OF 2DEG - A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer. | 2020-12-31 |
20200411650 | ELECTROSTATIC CATALYSIS - An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer. | 2020-12-31 |
20200411651 | STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH - A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end. | 2020-12-31 |
20200411652 | SEMICONDUCTOR STRUCTURE AND METHOD FORMATION METHOD THEREOF - A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region. Under the action of a first dielectric layer, the effective area between a conductive plug and a gate structure is reduced, and the parasitic capacitance between a conductive plug and a device gate structure is reduced accordingly. | 2020-12-31 |
20200411653 | SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate, an upper electrode provided on an upper surface of the semiconductor substrate, a lower electrode provided on a lower surface of the semiconductor substrate, and a terminal connected to the upper electrode. The semiconductor substrate may include an active region in which switching elements are provided. The switching elements may be configured to pass a current between the upper electrode and the lower electrode. The active region may include a main region located under the terminal and an external region located outside the main region. The external region may include a low current region. A current density in the low current region may be lower than a current density in the main region in a case where the switching elements in the low current region and the main region are turned on. | 2020-12-31 |
20200411654 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, and a gate electrode. The source region and the drain region are in the substrate, and the gate electrode is partly buried in the substrate and between the source region and the drain region. | 2020-12-31 |
20200411655 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 2020-12-31 |
20200411656 | HORIZONTAL GATE ALL AROUND DEVICE NANOWIRE AIR GAP SPACER FORMATION - Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1. | 2020-12-31 |
20200411657 | INTERMETALLIC COMPOUND - A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms. | 2020-12-31 |
20200411658 | STACK AND SEMICONDUCTOR DEVICE - A stack with excellent electrical characteristics and reliability is provided. The stack includes an insulator, a conductor, and a first oxide between the insulator and the conductor; the first oxide includes a first c-axis-aligned crystal region; and a c-axis of the first crystal region is substantially perpendicular to a plane of the first oxide on the insulator side. Alternatively, the stack includes an insulator, a conductor, a first oxide between the insulator and the conductor, and a second oxide facing the first oxide with the insulator therebetween; the first oxide includes a first c-axis-aligned crystal region; a c-axis of the first crystal region is substantially perpendicular to a plane of the first oxide on the insulator side; the second oxide includes a second c-axis-aligned crystal region; and a c-axis of the second crystal region is substantially perpendicular to a plane of the second oxide on the insulator side. | 2020-12-31 |
20200411659 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first conductive member, a first semiconductor layer, a second semiconductor layer, and an insulating member. The third electrode is between the first electrode and the second electrode. The first conductive member is electrically connected to the first electrode. The first conductive member is between the third electrode and the second electrode. The first semiconductor layer includes Al | 2020-12-31 |
20200411660 | DEVICE INCLUDING AIR GAPPING OF GATE SPACERS AND OTHER DIELECTRICS AND PROCESS FOR PROVIDING SUCH - A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask. | 2020-12-31 |
20200411661 | DEPOP USING CYCLIC SELECTIVE SPACER ETCH - An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires. | 2020-12-31 |
20200411662 | Fabrication of Field Effect Transistors With Ferroelectric Materials - A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers. | 2020-12-31 |
20200411663 | Composite-Channel High Electron Mobility Transistor - A HEMT comprises a composite channel, made up of a plurality of channel/barrier layer heterojunctions. That is, two or more channel/barrier layer pairs are deposited on a substrate, under a gate contact. A separate 2DEG is formed in each channel layer at the heterojunction with the barrier layer. The HEMT channel is effectively divided among a plurality of parallel 2DEGs. A high total charge density—required for high power operation—is divided among the plurality of 2DEGs. Since each 2DEG does not have a large charge density, it can sustain the high saturated electron velocity required for very high frequency operation. The composite-channel HEMT thus operates with high gain, at high power levels, and at high frequencies. | 2020-12-31 |
20200411664 | MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE - A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer. | 2020-12-31 |
20200411665 | SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING VERTICAL TRANSISTOR WITH SAGE GATE STRUCTURE - Self-aligned gate endcap (SAGE) architectures having vertical transistors with SAGE gate structures, and methods of fabricating SAGE architectures having vertical transistors with SAGE gate structures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having first fin sidewall spacers, and a second semiconductor fin having second fin sidewall spacers. A gate endcap structure is between the first and second semiconductor fins and laterally between and in contact with adjacent ones of the first and second fin sidewall spacers, the gate endcap structure including a gate electrode and a gate dielectric. A first source or drain contact is electrically coupled to the first semiconductor fin. A second source or drain contact is electrically coupled to the second semiconductor fin. | 2020-12-31 |
20200411666 | DIFFERENTIAL SILICIDE STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region. | 2020-12-31 |
20200411667 | Dielectric Inner Spacers in Multi-Gate Field-Effect Transistors - A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air. | 2020-12-31 |
20200411668 | GATE-ALL-AROUND FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME - This application discloses a gate-all-around field effect transistor and a method for manufacturing same. In some implementations the method may include: forming a first fin structure on a substrate, where each first fin structure includes one first laminated structure, where the first laminated structure sequentially includes a sacrificial layer, a support layer, and a channel layer from bottom to top; forming a dummy gate structure across the first fin structure, where the dummy gate structure includes a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate; removing parts of the first fin structure located on two sides of the dummy gate structure, to form a second fin structure; performing first etching on a side surface of the sacrificial layer in the second fin structure, to form a first space; forming a second spacer in the first space; performing second etching on a side surface of the channel layer in the second fin structure, to form a second space; and performing selective epitaxy on the side surface of the channel layer in the second fin structure, to form a source region and a drain region, where along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer | 2020-12-31 |
20200411669 | CHANNEL FORMATION FOR THREE DIMENSIONAL TRANSISTORS - Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed. | 2020-12-31 |
20200411670 | SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF - A method of forming a method of forming a semiconductor device includes providing a semiconductor structure, etching back each gate structure of a plurality of gate structures to form an opening, forming a barrier layer over the dielectric layer, forming a sacrificial layer over the barrier layer, planarizing the sacrificial layer till a surface of the sacrificial layer is substantially flat, and using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer, and to remove the sacrificial layer and to provide a planarized barrier layer. The semiconductor structure includes a semiconductor substrate, a fin, the plurality of gate structures, and a dielectric layer over the semiconductor substrate between adjacent gate structures. A top of the dielectric layer is coplanar with a top of each of the plurality of gate structures. | 2020-12-31 |
20200411671 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure. | 2020-12-31 |
20200411672 | FinFET Device and Methods of Forming - A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin. | 2020-12-31 |
20200411673 | METHOD OF FORMING PAIRS OF THREE-GATE NON-VOLATILE FLASH MEMORY CELLS USING TWO POLYSILICON DEPOSITION STEPS - A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block). | 2020-12-31 |
20200411674 | Bidirectional Phase Controlled Thyristor (BiPCT) - A New Semiconductor Device Concept - A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer. | 2020-12-31 |
20200411675 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Al | 2020-12-31 |
20200411676 | ENHANCEMENT MODE SADDLE GATE DEVICE - An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further incudes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET. | 2020-12-31 |
20200411677 | COMPLEMENTARY GROUP III-NITRIDE TRANSISTORS WITH COMPLEMENTARY POLARIZATION JUNCTIONS - Group III-N transistors of complementary conductivity type employing two polarization junctions of complementary type. Each III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. A III-N heterostructure may include two III-N polarization junctions. A 2D electron gas (2DEG) is induced at a first polarization junction and a 2D hole gas (2DHG) is induced at the second polarization junction. Transistors of complementary type may utilize a separate one of the polarization junctions, enabling III-N transistors to implement CMOS circuitry. | 2020-12-31 |
20200411678 | GROUP III-NITRIDE DEVICES ON SOI SUBSTRATES HAVING A COMPLIANT LAYER - A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing. | 2020-12-31 |
20200411679 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a substrate having a first main surface and a second main surface; a first nitride semiconductor layer of a first conductivity type provided above the first main surface; a second nitride semiconductor layer of a second conductivity type provided above the first nitride semiconductor layer; a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer provided above the second nitride semiconductor layer and on an inner surface of the first opening; a gate electrode provided above the electron transport layer and covering the first opening; a source electrode connected to the second nitride semiconductor layer; a drain electrode provided on a second main surface-side of the substrate; and a high-resistance layer provided between the second nitride semiconductor layer and the electron transport layer in the first opening, the high-resistance layer including a nitride semiconductor. | 2020-12-31 |
20200411680 | WIDE GAP SEMICONDUCTOR DEVICE - A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode | 2020-12-31 |
20200411681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench. | 2020-12-31 |
20200411682 | SELECTIVE SOURCE/DRAIN RECESS FOR IMPROVED PERFORMANCE, ISOLATION, AND SCALING - Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain. | 2020-12-31 |
20200411683 | SEMICONDUCTOR DEVICE - To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region. | 2020-12-31 |
20200411684 | METHODS OF FORMING AN LDMOS DEVICE AND THE RESULTING INTEGRATED CIRCUIT PRODUCT - One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which comprise an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure comprises a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region. | 2020-12-31 |
20200411685 | SOURCE CONTACT FORMATION OF MOSFET WITH GATE SHIELD BUFFER FOR PITCH REDUCTION - A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced. | 2020-12-31 |
20200411686 | VERTICAL TRANSISTORS FOR ULTRA-DENSE LOGIC AND MEMORY APPLICATIONS - A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material. | 2020-12-31 |
20200411687 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film. | 2020-12-31 |
20200411688 | SEMICONDUCTOR DEVICE WITH ANTI-HOT ELECTRON EFFECT CAPABILITY - A semiconductor device includes a substrate, a control structure positioned in the substrate, a plurality of first spacers positioned on two sidewalls of the control structure, a plurality of second spacers positioned on sidewalls of the plurality of first spacers, and a first doped region positioned in the substrate. The first doped region includes a lightly-doped area, a medium-doped area, and a heavily-doped area. The lightly-doped area of the first doped region abuts against one edge of the control structure. The medium-doped area of the first doped region abuts against the lightly-doped area of the first doped region. The heavily-doped area of the first doped region is enclosed by the medium-doped area of the first doped region. | 2020-12-31 |
20200411689 | EPITAXIAL STRUCTURES OF A SEMICONDUCTOR DEVICE HAVING A WIDE GATE PITCH - A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack. | 2020-12-31 |
20200411690 | IMPROVED CONTACTS TO N-TYPE TRANSISTORS WITH L-VALLEY CHANNELS - An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed. | 2020-12-31 |
20200411691 | DIVERSE TRANSISTOR CHANNEL MATERIALS ENABLED BY THIN, INVERSE-GRADED, GERMANIUM-BASED LAYER - Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer. | 2020-12-31 |
20200411692 | TRANSISTOR STRUCTURES WITH A METAL OXIDE CONTACT BUFFER - Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition. | 2020-12-31 |
20200411693 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device having favorable electrical characteristics can be provided. The semiconductor device having favorable electrical characteristics is provided. The semiconductor device has a structure including a first metal oxide layer including a first region, and a second region and a third region in which phosphorus, boron, aluminum, or magnesium is added and between which the first region is sandwiched; a conductive layer which overlaps with the first region; a first insulating layer which covers a side surface and a bottom surface of the conductive layer; a second metal oxide layer which covers a side surface and a bottom surface of the first insulating layer and is in contact with a top surface of the first region; a second insulating layer in contact with a top surface of the second region and a top surface of the third region and in contact with a side surface of the second metal oxide layer; a third insulating layer positioned over the second insulating layer and in contact with a side surface of the second metal oxide layer; a fourth insulating layer positioned over the third insulating layer and in contact with a side surface of the second metal oxide layer; a fifth insulating layer in contact with a top surface of the conductive layer, a top surface of the first insulating layer, a top surface of the second metal oxide layer, and a top surface of the fourth insulating layer. | 2020-12-31 |
20200411694 | SEMICONDUCTOR DEVICE - A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon. | 2020-12-31 |
20200411695 | TRANSISTORS WITH FERROELECTRIC SPACER AND METHODS OF FABRICATION - A transistor includes a semiconductor body including a material such as an amorphous or polycrystalline material, for example and a gate stack on a first portion of the body. The gate stack includes a gate dielectric on the body, and a gate electrode on the gate dielectric. The transistor further includes a first metallization structure on a second portion of the body and a third metallization structure on a third portion of the body, opposite to the second portion. The transistor further includes a ferroelectric material on at least a fourth portion of the body, where the ferroelectric material is between the gate stack and the first or second metallization structure. | 2020-12-31 |
20200411696 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - The disclosure provides a thin film transistor, a method of manufacturing the thin film transistor, an array substrate and a display device, belongs to the field of display technology, and can solve the problem that an existing thin film transistor is prone to cracking or breaking due to bending. The thin film transistor of the present disclosure includes a substrate and an active layer arranged on the substrate, and at least one groove is arranged on a surface of the active layer distal to the substrate. | 2020-12-31 |
20200411697 | CHANNEL FORMATION FOR THREE DIMENSIONAL TRANSISTORS - Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed. | 2020-12-31 |
20200411698 | SEMICONDUCTOR DEVICES - A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region. | 2020-12-31 |
20200411699 | GROUP III-NITRIDE SCHOTTKY DIODE - A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed. | 2020-12-31 |
20200411700 | SEMICONDUCTOR DEVICE AND RADIO RECEIVER USING THE SAME - A semiconductor device includes: a first conductivity type semiconductor of a nanostructure; a first electrode that is in ohmic junction with an end part of the first conductivity type semiconductor; a second electrode that is coupled to the first electrode and is provided over a side surface of the first conductivity type semiconductor; and a depletion constituent that controls expansion of a depletion layer inside the nanostructure, wherein the depletion layer is expanded inside the first conductivity type semiconductor by the depletion constituent in a direction intersecting a movement direction of a carrier. | 2020-12-31 |
20200411701 | IMAGING DEVICE AND IMAGING SYSTEM - An imaging device includes a plurality of pixels each including a plurality of avalanche photodiodes, a setting unit configured to set the plurality of avalanche photodiodes to an active state or an inactive state separately, and a counter circuit that counts and outputs number of photons determined by the avalanche photodiode(s) set to the active state out of the plurality of avalanche photodiodes, wherein the imaging device is configured to change the number of avalanche photodiodes set to the active state out of the plurality of avalanche photodiodes in accordance with brightness of an object. | 2020-12-31 |
20200411702 | SEMICONDUCTOR WAFER MANUFACTURING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR ENERGY BEAM DETECTING ELEMENT, AND SEMICONDUCTOR WAFER - A through-slit is provided in a semiconductor wafer. A first virtual cutting line defines a chip portion including an energy ray sensitive region as viewed from a direction perpendicular to a first main surface. The shortest distance from a second virtual cutting line to the edge of a second semiconductor region is smaller than the shortest distance from the first virtual cutting line to the edge of the second semiconductor region. The through-slit penetrates through the semiconductor wafer in the thickness direction along the second virtual cutting line. A side surface to which a first semiconductor region is exposed is formed in the chip portion by providing the through-slit. A fourth semiconductor region of a first conductivity type is provided on the side surface side of the chip portion by adding impurities to the side surface to which the first semiconductor region is exposed. | 2020-12-31 |
20200411703 | HIGH SPEED PHOTO DETECTORS WITH REDUCED APERTURE METAL CONTACT AND METHOD THEREFOR - A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less. | 2020-12-31 |
20200411704 | PHOTOELECTRIC CONVERSION ELEMENT AND METHOD OF MANUFACTURING THEREOF - A photoelectric conversion element includes: a first photoelectric conversion layer including: a bottom electrode; a photoelectric conversion layer; and a top electrode; and a second photoelectric conversion part including: a bottom electrode; a photoelectric conversion part; and a top electrode. A conductive layer is formed on the bottom electrode. The top electrode and the bottom electrode are electrically connected by a conductive portion and the conductive layer. The conductive portion is formed of a part of the top electrode filled in a first groove that makes a surface of the conductive layer exposed and separates a photoelectric conversion layer and a photoelectric conversion layer from each other. The top electrodes are physically separated by a second groove provided to make a step surface of a stepped portion provided in the photoelectric conversion layer exposed and have a bottom surface thereof overlap the surface of the conductive layer. | 2020-12-31 |
20200411705 | COLORED TRANSPARENT SOLAR CELL - Provided is a transparent solar cell including a first transparent electrode, a second transparent electrode, a light absorbing layer, a first color implementation layer, and a second implementation layer, wherein each of the first color implementation layer and the second implementation layer includes an insulation layer and a conductive layer. By using a double layer, it is possible to provide a colored transparent solar cell securing stability and durability and implementing colors on both sides. | 2020-12-31 |
20200411706 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT AND SEMICONDUCTOR RELAY - A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part. | 2020-12-31 |
20200411707 | Photovoltaic Junctions and Methods of Production - The present disclosure is directed to photovoltaic junctions and methods for producing the same. Embodiments of the disclosure may be incorporated in various devices for applications such as solar cells and light detectors and may demonstrate advantages compared to standard materials used for photovoltaic junctions such as silica. An example embodiment of the disclosure includes a photovoltaic junction, the junction including a light absorbing material, an electron acceptor for shuttling electrons, and a metallic contact. In general, embodiments of the disclosure as disclosed herein include photovoltaic junctions which provide absorption across one or more wavelengths in the range from about 200 nm to about 1000 nm, or from near IR (NIR) to ultra-violet (UV). Generally, these embodiments include a multi-layered light absorbing material that can be formed from quantum dots that are successively deposited on the surface of an electron acceptor (e.g., a semiconductor). | 2020-12-31 |
20200411708 | SOLAR CELL DESIGN OPTIMIZED FOR PERFORMANCE AT HIGH RADIATION DOSES - A solar cell optimized for performance at high radiation doses, wherein the solar cell includes: a sub-cell comprised of a base and an emitter; the base of the sub-cell has a thickness of about 2 to 3 μm; the base of the sub-cell is doped at about 1e14 cm | 2020-12-31 |
20200411709 | Voltage-Matched Multi-junction Solar Module Made of 2D Materials - A voltage-matched solar module for converting incident solar radiation into electricity consisting of a plurality of wafer-sized multi-junction solar devices and wiring circuitry adjacent to a module-sized bottom substrate. Each solar device has at least two photovoltaic (PV) cells separated by electrically insulating transparent layers. The PV cells are aligned so as to overlap and are electrically connected to the wiring circuitry by conducting vias. The wiring circuitry includes a multiplicity of serial strings electrically connected in parallel and having substantially the same voltage. A method of producing the solar module is disclosed which utilizes an ALD/LPCVD tool for van der Waals epitaxy of 2D materials. | 2020-12-31 |
20200411710 | SINGLE PHOTON AVALANCHE DIODE DEVICES - A single photon avalanche diode (SPAD) device comprises:
| 2020-12-31 |
20200411711 | SOLAR CELL EMITTER REGION FABRICATION USING SUBSTRATE-LEVEL ION IMPLANTATION - Methods of fabricating solar cell emitter regions using substrate-level ion implantation, and resulting solar cells, are described. In an example, a method of fabricating a solar cell involves forming a lightly doped region in a semiconductor substrate by ion implantation, the lightly doped region of a first conductivity type of a first concentration. The method also involves forming a first plurality of dopant regions of the first conductivity type of a second, higher, concentration by ion implantation, the first plurality of dopant regions overlapping with a first portion of the lightly doped region. The method also involves forming a second plurality of dopant regions by ion implantation, the second plurality of dopant regions having a second conductivity type of a concentration higher than the first concentration, and the second plurality of dopant regions overlapping with a second portion of the lightly doped region and alternating with but not overlapping the first plurality of dopant regions. | 2020-12-31 |
20200411712 | METHOD AND APPARATUS FOR PROCESSING A SOLAR CELL STRUCTURE - A method for processing a solar cell structure includes providing a solar cell structure ( | 2020-12-31 |
20200411713 | METHOD FOR MANUFACTURING SOLAR CELL - The method for manufacturing a solar cell includes: forming a first semiconductor layer of first conductivity type on a surface of a semiconductor substrate; forming a lift-off layer containing a silicon-based material on the first semiconductor layer; selectively removing the lift-off layer and first semiconductor layer; forming a second semiconductor layer of second conductivity type on a surface having the lift-off layer and first semiconductor layer; and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution. The linear expansion coefficients of the semiconductor substrate and the lift-off layer satisfy the relational expression: the linear expansion coefficient of the lift-off layer2020-12-31 | |
20200411714 | METHOD OF DEPOSITING GALLIUM NITRIDE ON A SUBSTRATE - A method of depositing a coating layer comprising gallium nitride on a substrate comprising the steps of: (a) providing the substrate having a plurality of side walls and valleys; (b) forming a first layer of gallium nitride deposited on the substrate, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 400 to 500° C., such that the first layer is formed on the side walls and the valleys; and (c) forming a second layer of gallium nitride deposited on top of the first layer, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 1000 to 1200° C., to obtain the coating layer comprising the first layer of gallium nitride and the second layer of gallium nitride at a thickness ranging from 3.0 to 4.5 μm. | 2020-12-31 |
20200411715 | LIGHT-EMITTING THYRISTOR, LIGHT-EMITTING ELEMENT CHIP, OPTICAL PRINT HEAD, AND IMAGE FORMING DEVICE - A light-emitting thyristor includes a first semiconductor layer of a P type, a second semiconductor layer of an N type arranged adjacent to the first semiconductor layer; a third semiconductor layer of the P type arranged adjacent to the second semiconductor layer; and a fourth semiconductor layer of the N type arranged adjacent to the third semiconductor layer. A part of the first semiconductor layer is an active layer adjacent to the second semiconductor layer. A dopant concentration of the active layer is higher than or equal to a dopant concentration of the third semiconductor layer. A thickness of the third semiconductor layer is thinner than a thickness of the second semiconductor layer. A dopant concentration of the second semiconductor layer is lower than the dopant concentration of the third semiconductor layer. | 2020-12-31 |
20200411716 | ALUMINUM NITRIDE SUBSTRATE REMOVAL FOR ULTRAVIOLET LIGHT-EMITTING DEVICES - In various embodiments, extraction efficiency of light-emitting devices fabricated on aluminum nitride substrates is enhanced via removal of at least a portion of the substrate. | 2020-12-31 |
20200411717 | MICRO LIGHT-EMITTING DIODE DISPLAYS HAVING COLOR CORRECTION FILMS APPLIED THERETO - Micro light-emitting diode displays having color correction films applied thereto and methods of applying color correction films to a display are described. In an example, a method of fabricating a micro light emitting diode display includes applying a color correction film to a flexible transparent backing film. The method also includes placing the flexible transparent backing film over a display with the color correction film facing the display. The method also includes applying a laser to a portion of the flexible transparent backing film to eject a patch of the color correction film onto the display. | 2020-12-31 |
20200411718 | Method of producing substrates including gallium nitride - A method of producing a functional device has an etched gallium nitride layer and a functional layer having a nitride of a group 13 element. The method includes providing a body comprising a surface gallium nitride layer, performing a dry etching treatment of a surface of the surface gallium nitride layer to provide the etched gallium nitride layer using a plasma etching system comprising an inductively coupled plasma generating system, introducing an etchant during the dry etching treatment, the etchant consisting essentially of a fluorine-based gas, and forming the functional layer on a surface of the etched gallium nitride layer. | 2020-12-31 |
20200411719 | ELEMENT, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING ELEMENT - An element includes an electron transportation layer containing nanoparticles, a QD layer containing QD phosphor particles, and a mixed layer sandwiched between the electron transportation layer and the QD layer to be adjacent to these layers. The mixed layer contains QD phosphor particles and nanoparticles. | 2020-12-31 |
20200411720 | III-Nitride Multi-Wavelength Led For Visible Light Communication - A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate. | 2020-12-31 |
20200411721 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) device includes a substrate, an epitaxial layered structure disposed on the substrate, a current-spreading layer disposed on the epitaxial layered structure, a current-blocking unit disposed on the current-spreading layer, and a distributed Bragg reflector. The epitaxial layered structure, the current-spreading layer and the current-blocking unit are covered by the distributed Bragg reflector. One of the current-spreading layer, the current-blocking unit, and a combination thereof has a patterned rough structure. A method for manufacturing the LED device is also disclosed. | 2020-12-31 |
20200411722 | GROUP III-NITRIDE LIGHT EMITTING DEVICES INCLUDING A POLARIZATION JUNCTION - Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure. | 2020-12-31 |
20200411723 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - A method of manufacturing a nitride semiconductor light-emitting element configured to emit deep ultraviolet light includes: providing a semiconductor structure comprising:
| 2020-12-31 |
20200411724 | NANOCONE ARRAYS FOR ENHANCING LIGHT OUTCOUPLING AND PACKAGE EFFICIENCY - An LED structure includes an epi layer grown on a substrate and a plurality of dielectric nanoantennas positioned within the epi layer. The dielectric antennas can be periodically arranged to reduce reabsorption of light and redirect oblique incident light to improve overall light coupling efficiency. Each of the dielectric nanoantennas can have a top, a bottom, a height less than 1000 nm and greater than 200 nm and a diameter less than 2000 nm and greater than 300 nm. | 2020-12-31 |
20200411725 | LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR - A light emitting diode chip including a light emitting structure and a distributed Bragg reflector (DBR) having first, second, and third regions and including first material layers having a low index of refraction and second material layers having a high index of refraction, in which the first material layers include a first group having an optical thickness greater than 0.25λ+10%, a second group having an optical thickness in a range of 0.25λ−10% to 0.25λ+10%, and a third group having an optical thickness less than 0.25λ−10%, the first region has alternately disposed first and second groups, the second region has the third group, the first material layers in the third region have a first material layer having an optical thickness less than 0.25λ and greater than 0.25λ, the second material layers have a smaller average optical thickness than the first group of the first material layers. | 2020-12-31 |
20200411726 | ULTRAVIOLET LIGHT-EMITTING DIODE CHIP AND METHOD FOR MAKING THE SAME - An ultraviolet light-emitting diode chip, including: a n-type semiconductor layer; an intermediate layer disposed on the n-type semiconductor layer, the intermediate layer including a plurality of first tapered pits; an active layer disposed on the intermediate layer; a p-type semiconductor layer disposed on the active layer; a n-type electrode disposed on the n-type semiconductor layer; a p-type electrode disposed on the p-type semiconductor layer; a reflecting layer; a bonding layer; and a substrate. The reflecting layer and the bonding layer are disposed between the p-type electrode and the substrate. The active layer includes a plurality of second tapered pits in a hexagonal structure and a plurality of first flat regions connecting every two adjacent second tapered pits. The projected area of the plurality of first flat regions is less than 30% of the projected area of the active layer. | 2020-12-31 |
20200411727 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate comprising a base member, a first wiring, a second wiring, and a via hole; at least one light-emitting element electrically connected to and disposed on the first wiring; and a covering member having light reflectivity and covering a lateral surface of the light-emitting element and a front surface of the substrate. The base member defines a plurality of depressed portions separated from the via hole in a front view and opening on a back surface and a bottom surface of the base member. The substrate includes a third wiring covering at least one of inner walls of the plurality of depressed portions and electrically connected to the second wiring. A depth of each of the plurality of depressed portions defined from the back surface toward the front surface is larger on a bottom surface side than on an upper surface side of the base member. | 2020-12-31 |
20200411728 | ADHESIVE LAYER WITH VARIED MATERIAL PROPERTIES - A light emitting package and method of making the package are described. The package contains an LED bonded to a light converting layer using an adhesive. The adhesive is jet printed, mask sprayed or extruded onto one of the surfaces before bonding. The adhesive has materials in different sections that differ in refractive index, oxygen permeability, and/or heat conductivity. The materials are formed in concentric rings around the adhesive center, islands or lines and are disposed to provide optical lensing or increasing permeability/heat conductivity with decreasing distance from the center. A substantially-reflective optical side coat surrounds the LED, adhesive layer and connecting structure. | 2020-12-31 |
20200411729 | METHOD FOR MANUFACTURING WAVELENGTH CONVERSION MEMBER, WAVELENGTH CONVERSION MEMBER, AND LIGHT-EMITTING DEVICE - Provided are a method for manufacturing wavelength conversion members that enables manufacturing of wavelength conversion members having a high light extraction efficiency and suppression of material loss, a wavelength conversion member obtained by the method, and a light-emitting device. A method for manufacturing a plurality of wavelength conversion members by breaking into parts a base material | 2020-12-31 |
20200411730 | LIGHT EMITTING DIODE PACKAGES - Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. LED packages are disclosed that include an LED chip with multiple discrete active layer portions mounted on a submount. The LED packages may further include wavelength conversion elements and light-altering materials. The multiple discrete active layer portions may be electrically connected in series, parallel, or in individually addressable arrangements. The LED chip with the multiple discrete active layer portions may provide the LED package with improved brightness, improved alignment, simplified manufacturing, and reduced costs. | 2020-12-31 |
20200411731 | EPITAXY WAVELENGTH CONVERSION ELEMENT, LIGHT-EMITTING SEMICONDUCTOR COMPONENT, AND METHODS FOR PRODUCING THE EPITAXY WAVELENGTH CONVERSION ELEMENT AND THE LIGHT-EMITTING SEMICONDUCTOR COMPONENT - An epitaxial wavelength conversion element ( | 2020-12-31 |
20200411732 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material. | 2020-12-31 |
20200411733 | WIDE COLOR GAMUT LIGHT-EMITTING ELEMENT - A light emitting element including a housing having a cavity and an inner wall, a light emitting part disposed in the cavity to emit light having a peak wavelength in a blue wavelength band and including first and second light emitting chips spaced apart from each other, and a wavelength converter including a first phosphor layer including a first phosphor to emit light having a peak wavelength in a green wavelength band, and a second phosphor layer including a second phosphor to emit light having a peak wavelength in a red wavelength band, in which the second phosphor includes at least one of a nitride-based red phosphor and a fluoride-based red phosphor represented by A | 2020-12-31 |
20200411734 | LIGHT-EMITTING DEVICE AND ILLUMINATION APPARATUS - A light-emitting device in an aspect of the present invention includes at least one light emitter, a first phosphor, and a second phosphor. The first phosphor emits, in response to light emitted from the at least one light emitter, light having a first peak wavelength in a wavelength region of 400 to 480 nm. The second phosphor emits, in response to light emitted from the at least one light emitter, light having a second peak wavelength in a wavelength region of 480 to 600 nm. The at least one light emitter has a third peak wavelength in a wavelength region of 280 to 315 nm and emits light in the wavelength region of 280 to 315 nm. | 2020-12-31 |
20200411735 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element including a first surface; a light guide member covering at least a part of a lateral surface of the light emitting element; a first wavelength conversion member covering the first surface and including a first wavelength conversion particles; and a reflective member being in contact with the light emitting element. The first wavelength conversion member has a thickness of 60 μm or more and 120 μm or less. The first wavelength conversion particles have an average particle size of 4 μm or longer and 12 μm or smaller; the first wavelength conversion particles have a central particle size of 4 μm or longer and 12 μm or smaller. A weight ratio of the first wavelength conversion particles is 60% by weight or more and 75% by weight or less with respect to the total weight of the first wavelength conversion member. | 2020-12-31 |
20200411736 | PHOSPHOR LAYER FOR MICRO-LED APPLICATIONS - Embodiments include a device having a micro-LED that includes at least two, individually addressable light emitting diodes on a same substrate; a phosphor converter layer disposed on the micro-LED, the phosphor converter layer including phosphor particles having a D50 of greater than 1 μm and less than 10 μm. | 2020-12-31 |
20200411737 | LIGHT EMITTING DEVICE - A light emitting device includes at least one LED package, and at least one light transmissive sealing member. Each of the at least one LED package includes a light emitting element, a wavelength converter, and a reflection member. The light emitting element is mounted on a mounting surface of a base and electrically connected to a conductor wiring. The wavelength converter is provided on an upper surface of the light emitting element. The reflection member covers a side surface and a lower surface of the light emitting element. Each of the at least one light transmissive sealing member includes a light diffusion material and covers each of the at least one LED package. Each of the at least one light transmissive sealing member has a projection shape with a substantially circular bottom surface facing the base and with a height in the light axis direction of the light emitting element. | 2020-12-31 |
20200411738 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package according to an embodiment may comprise: a first package body including a first and a second opening; a light emitting device disposed on the first package body and including a first and a second bonding part; and a first resin disposed between the first package body and the light emitting device. The light emitting device may comprise one surface on which the first and second bonding parts are disposed, the first bonding part may comprise a first side surface and a lower surface facing the first package body, and the second bonding part may comprise a second side surface opposite to the first side surface, and a lower surface facing the first package body. The first resin may comprise an upper surface disposed on the one surface of the light emitting device, a third side surface extending from the upper surface to the lower surface of the first bonding part along the first side surface of the first bonding part, and a fourth side surface extending from the upper surface to the lower surface of the second bonding part along the second side surface of the second bonding part. | 2020-12-31 |
20200411739 | MICRO DEVICE AND MICRO DEVICE DISPLAY APPARATUS - A micro device includes an epitaxial structure and a light guide structure. The epitaxial structure has a top surface. The light guide structure is disposed on the top surface, and the light guide structure includes a connecting portion and a covering portion. The connecting portion is disposed on an edge of the epitaxial structure and extends along a sidewall of the epitaxial structure. The covering portion is disposed on the top surface and connected to the connecting portion. A width of the connecting portion at the edge of the epitaxial structure is smaller than a width away from the top surface. | 2020-12-31 |
20200411740 | DISPLAY DEVICE - A display device includes: a transparent circuit board and a plurality of light-emitting elements arrayed in matrix on the transparent circuit board, the light-emitting elements each including a pair of terminals which drive voltage for light emission is applied, the circuit board including a plurality of row wires each connecting ones of the pairs of terminals of ones of the light-emitting elements to each other, the ones of the light-emitting elements belonging to a same one of rows in the matrix array, and a plurality of column wires each connecting other ones of the pairs of terminals of ones of the light-emitting elements to each other, the ones of the light-emitting elements belonging to a same one of columns in the matrix array, the plurality of row wires and the plurality of column wires being formed on different surfaces of the circuit board. | 2020-12-31 |