53rd week of 2009 patent applcation highlights part 33 |
Patent application number | Title | Published |
20090323377 | OPTIMAL UTILIZATION OF POWER CONVERTERS FOR ENGINE START SYSTEM - A method and system for utilization of power converters in an aircraft engine start system includes measurement of power converter operation data that is utilized with a mathematical model of the power converter thermal characteristics to calculate operation limits for subsequent start duty cycles. A warning indicator is utilized in the event the start duty cycle limits are exceeded. This invention can be extended for any More Electric Vehicle applications, which utilizes an electric engine start system. | 2009-12-31 |
20090323378 | SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER - The disclosure describes techniques for converting an input voltage level to two or more output voltage levels using only two pump capacitors and three switching phases. The disclosure also describes techniques for selectively controlling a dc-dc converter to operate in different conversion modes. One mode may use only two pump capacitors and three switching phases to produce output voltage levels with a first set of conversion ratios. Another mode may use two pump capacitors and two switching phases to produce output voltage levels with a second set of conversion ratios. The first mode may use three different subcircuit arrangements of the pump capacitors. The second mode may use two different subcircuit arrangements of the pump capacitors. A converter may include switches and pump capacitors that can be selectively configured to transition between two or three different subcircuits, thereby producing output voltages according to different conversion ratios on a selective basis. | 2009-12-31 |
20090323379 | High efficiency photovoltaic inverter - A photovoltaic (PV) inverter includes a single DC to AC converter configured to operate solely in a buck mode for PV array voltage levels greater than a connected power grid instantaneous voltage plus converter margin, and further configured to operate solely in a boost mode for PV array voltage levels plus margin less than the connected power grid instantaneous voltage, such that the PV inverter generates a rectified sine wave current in response to the available PV array power, and further such that the PV inverter generates a utility grid current in response to the rectified sine wave current. | 2009-12-31 |
20090323380 | CYCLO-CONVERTER AND METHODS OF OPERATION - A three phase full resonant cyclo-converter suitable for converting a three phase AC supply to a DC output. In one embodiment the cycloconverter controls switching frequency to control converter output and adjusts phase on times for power factor correction. A switching sequence is employed which provides resonant switching to reduce losses and component ratings. The converter provides high conversion efficiency with a simple power component design. | 2009-12-31 |
20090323381 | ADAPTABLE POWER SUPPLY CIRCUIT - A power supply circuit and a transponder having a circuit for rectifying an A.C. voltage and two power storage elements, the rectifying circuit providing a rectified voltage to at least one of the storage elements and an output voltage being provided by at least one of the storage elements, and at least one switching element for switching the circuit operation between a state of provision of a relatively high voltage and a state of provision of a relatively low voltage, the second state configuring the rectifying circuit in halfwave operation. | 2009-12-31 |
20090323382 | ADAPTER CONNECTION STRUCTURE - The present invention discloses an adapter connection structure, which comprises a first converter and a second converter. The first converter is connected to at least one input terminal to receive an input power and converts the input power into a transitional power. The second converter is connected to the first converter via a transit cable to transmit the transitional power, converts the transitional power into a DC output power and outputs the DC output power via a DC power cable. As the transitional power transmitted from the first converter to the second converter is in form of a high-voltage and high-frequency AC power or a high-voltage DC power, the power transmission loss in the transit cable is reduced. Therefore, the present invention not only can reduce transmission loss but also can adopt a less expensive cable. Thus is reduced the total cost of buying and using the adapter. | 2009-12-31 |
20090323383 | COMPARING DATA REPRESENTATIONS TO STORED PATTERNS - A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at least one of the plurality of data patterns to select one of the plurality of representations of the search word for comparing to the at least one of the plurality of data patterns, and a logic circuit operatively coupled to the storage module, to the plurality of busses, and to the selector to compare the selected one of the plurality of representations of the search word to the at least one of the plurality of data patterns. | 2009-12-31 |
20090323384 | HIGH DENSITY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices. | 2009-12-31 |
20090323385 | Method for fabricating high density pillar structures by double patterning using positive photoresist - A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern. | 2009-12-31 |
20090323386 | Methods and Systems for Reducing Heat Flux in Memory Systems - The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus. | 2009-12-31 |
20090323387 | One-Time Programmable Memory and Operating Method Thereof - A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug. | 2009-12-31 |
20090323388 | Buried Bit Line Anti-Fuse One-Time-Programmable Nonvolatile Memory - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 2009-12-31 |
20090323389 | MASKED MEMORY CELLS - An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array. | 2009-12-31 |
20090323390 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line. | 2009-12-31 |
20090323391 | REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE - A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion. | 2009-12-31 |
20090323392 | SMART DETECTION CIRCUIT FOR WRITING TO NON-VOLATILE STORAGE - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. | 2009-12-31 |
20090323393 | CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells. | 2009-12-31 |
20090323394 | PULSE RESET FOR NON-VOLATILE STORAGE - A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells. | 2009-12-31 |
20090323395 | SEMICONDUCTOR STORAGE DEVICE - A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated by a current flowing through a selected memory cell. A reference voltage generation circuit includes: a resistance circuit including first and second resistive elements connected in parallel. Each of the first resistive elements has a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements has a resistance value substantially the same as a minimum resistance value in the variable resistance elements. A current regulator circuit averages currents flowing through the first and second resistive elements. | 2009-12-31 |
20090323396 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory according to an aspect of the invention including first and second bit lines, a word line, a resistive memory element which has one end and the other end, the one end being connected with the first bit line, a selective switch element which has a current path and a control terminal, one end of the current path being connected with the other end of the resistive memory element, the other end of the current path being connected with the second bit line, the control terminal being connected with the word line, a first column switch connected with the first bit line, a second column switch connected with the second bit line, wherein the first and second bit lines is activated and then the word line is activated when starting writing or reading data with respect to the resistive memory element. | 2009-12-31 |
20090323397 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell including a resistance memory element which memorizes a high resistance state or a low resistance state, switches the high resistance state and the low resistance state by voltage application, one end of the resistance memory element being coupled to a bit line, the other end of the resistance memory element being coupled to a source line via the first transistor; and a resistor whose resistance value is higher than a resistance value of the resistance memory element in the low resistance state and lower than a resistance value of the resistance memory element in the high resistance state, one end of the resistor being coupled to said one end of the resistance memory element and the bit line, the other end of the resistor being coupled to the source line via the second transistor. | 2009-12-31 |
20090323398 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor. | 2009-12-31 |
20090323399 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise. | 2009-12-31 |
20090323400 | SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell. | 2009-12-31 |
20090323401 | 8T LOW LEAKAGE SRAM CELL - This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line. | 2009-12-31 |
20090323402 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 2009-12-31 |
20090323403 | SPIN-TRANSFER TORQUE MEMORY NON-DESTRUCTIVE SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 2009-12-31 |
20090323404 | Write Operation for Spin Transfer Torque Magnetoresistive Random Access Memory with Reduced Bit Cell Size - Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation. | 2009-12-31 |
20090323405 | Controlled Value Reference Signal of Resistance Based Memory Circuit - Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell. | 2009-12-31 |
20090323406 | MAGNETIC MEMORY ELEMENT, AND METHOD OF MANUFACTURING MEMORY ELEMENT - A magnetic memory element includes an impurity element, and magnetic thin lines to which the impurity element is added to adjust the movement of a magnetic domain wall in a magnetic field. Applying a voltage to the magnetic thin lines controls a position of the magnetic domain wall to invert a magnetization direction of a magnetic recording layer adjacent to the magnetic domain wall, by which information is recorded. | 2009-12-31 |
20090323407 | Memory device, an information storage process, a process, and a structured material - A memory device, including a plurality of nanoscale memory cells ( | 2009-12-31 |
20090323408 | METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 2009-12-31 |
20090323409 | METHODS FOR HIGH SPEED READING OPERATION OF PHASE CHANGE MEMORY AND DEVICE EMPLOYING SAME - Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory. | 2009-12-31 |
20090323410 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction in a region in which a substrate resides during a deposition of a first magnetic material onto the substrate. The method further includes applying a second magnetic field along a second direction in the region during the deposition of the first magnetic material onto the substrate. | 2009-12-31 |
20090323411 | METHOD INCLUDING SELECTIVE TREATMENT OF STORAGE LAYER - Method including selective treatment of storage layer. One embodiment includes the formation of a material layer on a topology with protruding portions, which may be assigned to active areas, and with recessed portions, which may be assigned to isolation structures. A mask material is deposited that grows selectively above the protruding portions and that forms a mask which covers first portions of the material layer wrapping around at least portions of the protruding portions. Openings in the mask are formed above second portions of the material layer above the recessed portions. Then the material layer is treated in the second portions in a self-aligned manner. | 2009-12-31 |
20090323412 | READ DISTURB MITIGATION IN NON-VOLATILE MEMORY - Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula. | 2009-12-31 |
20090323413 | VOLTAGE REFERENCE GENERATOR FOR FLASH MEMORY - There is disclosed example embodiments of flash memory including reference generators using big flash memory cells to generate flash array wordline voltages, wherein the reference voltage values can be trimmed by changing the threshold voltage of the flash cells. In addition, the inventive subject matter provides for using the matching characteristics of two source followers in closed loop and open loop to achieve fast stabilization times. Further, the temperature characteristics of the wordline voltages track the temperature characteristics of the array flash cells. Still further, the disclosed reference generators use cascoding reference generators to provide more reliability and accuracy. | 2009-12-31 |
20090323414 | Method and Device for Storing Data - In one aspect a method of storing data in an integrated circuit may include identifying a group of storage sites from a plurality of storage sites; selecting a plurality of storage levels, each storage level being assignable to a storage site in the group of storage sites; and assigning a unique storage level to each of the storage sites in the group of storage sites, each unique storage level assigned from the plurality of storage levels. | 2009-12-31 |
20090323415 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 2009-12-31 |
20090323416 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS - Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. | 2009-12-31 |
20090323417 | SEMICONDUCTOR MEMORY REPAIRING A DEFECTIVE BIT AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective bits less than N (N is an integer number more than 0) in all pages of the block stores a first data showing a normal block. A block including at least one page having defective bits more than N and including no page having defective bits more than M (M is an integer number of M>N) stores a second data showing a psedo-pass block as a pseudo-normal block. A block including at least one page having defective bits more than M stores a third data showing a defective block. | 2009-12-31 |
20090323418 | Use of Alternative Value in Cell Detection - A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values. | 2009-12-31 |
20090323419 | READ-TIME WEAR-LEVELING METHOD IN STORAGE SYSTEM USING FLASH MEMORY DEVICE - Disclosed is a read-time wear-leveling method in a storage system using a flash memory device, in which the abrasion of the flash memory device generated by repeated read operations is dispersed over the entire region so that the abrasion of memory blocks can be equalized to prolong the life of the flash memory device, to minimize errors in the memory blocks, and to secure the reliability of the storage system. | 2009-12-31 |
20090323420 | MINIMIZING POWER NOISE DURING SENSING IN MEMORY DEVICE - In a sensing method, accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point. | 2009-12-31 |
20090323421 | MEMORY DEVICE WITH POWER NOISE MINIMIZATION DURING SENSING - Accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point. | 2009-12-31 |
20090323422 | GAIN CONTROL FOR READ OPERATIONS IN FLASH MEMORY - A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L2009-12-31 | |
20090323423 | METHODS, CIRCUITS AND SYSTEMS FOR READING NON-VOLATILE MEMORY CELLS - The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value. | 2009-12-31 |
20090323424 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors. | 2009-12-31 |
20090323425 | SYSTEMS AND METHODS FOR IMPROVED FLOATING-GATE TRANSISTOR PROGRAMMING - The present invention describes systems and methods for improving the programming of floating-gate transistors. An exemplary embodiment of the present invention provides a floating-gate transistor programming system including an array of floating-gate transistors and a measuring circuit comprising a logarithmic transimpedance amplifier and an analog-to-digital converter. Furthermore, the floating-gate transistor programming system includes an injecting circuit comprising a digital-to-analog converter, wherein the pulsing circuit can inject charge into each of the floating-gate transistors and the measuring circuit can measure a present charge value in one of the plurality of floating-gate transistors. | 2009-12-31 |
20090323426 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense. | 2009-12-31 |
20090323427 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion. | 2009-12-31 |
20090323428 | METHOD FOR IMPROVING MEMORY DEVICE CYCLING ENDURANCE BY PROVIDING ADDITIONAL PULSES - A method for programming and erasing a PHINES memory device is comprising providing one or more additional pulses that are associated with a program or erase pulse, wherein the additional pulses are of similar polarity, but of lesser magnitude than the program or erase pulses. For an erase pulse on a PHINES memory device, two additional pulses can be utilized. For a program pulse on the source-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a source of the memory device. For a program pulse on the drain-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a drain of the memory device. | 2009-12-31 |
20090323429 | PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY - Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass. | 2009-12-31 |
20090323430 | PROGRAM ACCELERATION OF A MEMORY DEVICE - Selective program acceleration of a memory device is generally described. In one example, a method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality of cells at a target threshold voltage to determine whether one or more cells of the plurality of cells have reached or surpassed the target threshold voltage, identifying slower cells of the plurality of cells, and selectively accelerating a program speed of the slower cells to reduce a programming time of a memory device. | 2009-12-31 |
20090323431 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a non-volatile memory device employing program loops. Each program loop comprises a programming operation and a subsequent plurality of verifying operations. The method includes preventing the next program loop based on the results of performing the plurality of verifying operations of a current program loop each verifying operation verifying whether the selected memory cell transistors are program-passed. The decision to re-program may be based on a program pass number of the memory cell transistors obtained as a result of the plurality of verifying operations of the current program loop. | 2009-12-31 |
20090323432 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 2009-12-31 |
20090323433 | DATA SENSING METHOD FOR DYNAMIC RANDOM ACCESS MEMORY - A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line. | 2009-12-31 |
20090323434 | COMBINATION MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell. | 2009-12-31 |
20090323435 | TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY - In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals. | 2009-12-31 |
20090323436 | Refresh signal generating circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal. | 2009-12-31 |
20090323437 | Method and Apparatus for Data Inversion in Memory Device - The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device. | 2009-12-31 |
20090323438 | CIRCUIT AND METHOD FOR GENERATING WORD LINE OFF VOLTAGE - A circuit and method for generating a word line off voltage which can minimize a leakage current by actively adjusting a level of the word line off voltage. The circuit includes a current information provider for providing information about an amount of current flowing through a cell transistor, and a voltage generator for generating a word line off voltage with a varying level depending on the information. | 2009-12-31 |
20090323439 | MEMORY FOR STORING A BINARY STATE - A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value. | 2009-12-31 |
20090323440 | Data processing device and method of reading trimming data - A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions. | 2009-12-31 |
20090323441 | Write Latency Tracking Using a Delay Lock Loop in a Synchronous DRAM - A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency. | 2009-12-31 |
20090323442 | SEMICONDUCTOR MEMORY DEVICE AND RESET CONTROL CIRCUIT OF THE SAME - The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal. | 2009-12-31 |
20090323443 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit. | 2009-12-31 |
20090323444 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines. | 2009-12-31 |
20090323445 | High Performance Read Bypass Test for SRAM Circuits - A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode. | 2009-12-31 |
20090323446 | MEMORY OPERATION TESTING - Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered. | 2009-12-31 |
20090323447 | Apparatus for measuring data setup/hold time - An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a data latch unit for latching buffered data signals in synchronization with the internal clock signal, wherein the buffered data signals are produced by buffering the data signals, a flag signal generating unit for generating flag signals from the latched data signals latched in the data latch unit in response to the test signals, and a counter for producing the counting signals in response to the flag signals. | 2009-12-31 |
20090323448 | Bias Sensing in Dram Sense Amplifiers Through Voltage-Coupling/Decoupling Device - Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased. | 2009-12-31 |
20090323449 | CIRCUIT AND METHOD FOR CONTROLLING SELF-REFRESH CYCLE - The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature. | 2009-12-31 |
20090323450 | NON-VOLATILE PROGRAMMABLE MEMORY CELL AND MEMORY ARRAY - A non-volatile one time programmable memory cell couples in series a two terminal fuse and a three terminal antifuse. The non-volatile one time programmable memory cell includes a memory cell write enable node and a memory cell output node. The non-volatile one time programmable memory cell includes fuse having a first node and a second node, and an antifuse having a trigger node, a first node, and a second node. The trigger node is coupled to the memory cell write enable node. The first node of the antifuse and the second node of the fuse are coupled to the memory cell output node. First and second voltages appearing at the memory cell output node are indicative of first and second binary states of the memory cell. A plurality of such memory cells can be included in a non-volatile programmable memory array. A non-volatile programmable memory cell capable of re-programming is also described. | 2009-12-31 |
20090323451 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh. | 2009-12-31 |
20090323452 | Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition - A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time. | 2009-12-31 |
20090323453 | Dynamic Power Saving Memory Architecture - A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports. | 2009-12-31 |
20090323454 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of easily checking whether banks are overlappingly activated. The semiconductor memory device includes a bank active signal generating unit and an overlap detecting unit. The bank active signal generating unit generates bank active signals for respective different banks in response to an active signal and bank addresses. The overlap detecting unit detects whether the bank active signals of the different banks are overlappingly enabled. | 2009-12-31 |
20090323455 | WORD LINE DRIVER, METHOD FOR DRIVING THE WORD LINE DRIVER, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE WORD LINE DRIVER - A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption. | 2009-12-31 |
20090323456 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. | 2009-12-31 |
20090323457 | SYSTEM AND METHOD FOR SYNCHRONIZING ASYNCHRONOUS SIGNALS WITHOUT EXTERNAL CLOCK - One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device. | 2009-12-31 |
20090323458 | CONTINUOUS PROCESS FOR PERFORMING A CHEMICAL REACTION IN WHICH A GASEOUS PHASE IS ADDED TO A CHARGE SYSTEM COMPRISING ONE OR MORE SOLID PHASES WHICH HAVE BEEN DISSOLVED OR DISPERSED IN WATER - A chemical reaction is performed by first adding the incoming stream to a shear zone of an apparatus by way of a feed upstream of the shear zone. The apparatus includes a rotor and a stator, with the shear zone being formed by facing surfaces of the rotor and the stator. The shear zone is followed by a mixing zone having an outlet toward an outside of the apparatus. A gage pressure of at least 1 bar is generated in the shear zone. The gaseous phase is mixed into the mixing zone through the aperture and into the incoming stream under the generated gage pressure to create a reaction mixture. The reaction mixture is fed to a residence-time zone via a downstream outlet from the mixing zone, where a reaction takes place, and pressure in the mixing zone is controlled using a downstream pressure-control valve. | 2009-12-31 |
20090323459 | CYLINDRICAL MEMBRANE APPARATUS FOR FORMING FOAM - An apparatus and process for making a foam having a controlled size distribution of gas bubbles in a liquid matrix. The invention utilizes a porous material having a controlled pore size and pore distance to produce a substantially uniform size distribution of gas bubbles; a gas pumping device for directing a flow of gas to and through the porous material to form the gas bubbles; a fluid pumping device for directing a flow of liquid matrix past the porous material and a rotating element moving in the vicinity of the membrane surface causing an additional flow to detach, collect accumulate and entrain the gas bubbles in the liquid matrix to form a foam having gas bubbles of generally uniform size and a substantially uniform gas bubble size distribution. Advantageously, the pore size and pore distance of the porous material, the gas flow from the gas pumping device, the flow field generated by the rotating element and the liquid flow from the fluid pumping device cooperate to provide gas bubbles having a mean diameter X | 2009-12-31 |
20090323460 | SYSTEM AND METHOD FOR MIXING COMPONENTS USING TURBULENCE | 2009-12-31 |
20090323461 | Magnetic system in a pVT cell - A magnetic stirring system for pVT and condensate cell is described. The stirring detection is performed by a solenoid to achieve reliable monitoring of the rotation of the stirring impeller in high-viscous fluids, dark fluids or cells without window. | 2009-12-31 |
20090323462 | Machine for producing and dispensing liquid or semi-liquid consumer food product - A machine for producing and dispensing liquid or semi-liquid consumer food products, comprising: a tank ( | 2009-12-31 |
20090323463 | Devices And Fluid Flow Methods For Improving Mixing - The invention provides devices and methods for increasing the degree of mixing of fluids, including under conditions of laminar flow and turbulent flow. In one embodiment, mixing of fluids using the invention's devices and methods is increased by splitting the flow of at least one of the fluids into two or more inlet channels. This is optionally followed by further splitting and merging (e.g., using one or more split and merge (SAM) mixer) the fluids. | 2009-12-31 |
20090323464 | Horizontal-flow hydration apparatus - A novel apparatus is disclosed which comprises:
| 2009-12-31 |
20090323465 | MIXER - The present invention is related to an apparatus for massaging and/or tumbling of a product with a drum and a shaft with paddles rotated by a motor. | 2009-12-31 |
20090323466 | SYSTEMS AND DEVICES FOR MIXING SUBSTANCES AND METHODS OF MAKING SAME - A mixing apparatus including a kinetic energy source, a mixing tank, a pivot guide, and transfer shaft is used to drive a mixing paddle through a circular path within a tank without substantial shaft rotation. Sleeved and sleeveless mixing paddles are provided in combination with sealable mixing tanks. A volumetric compensation system responsive to tank wall deflection is used to maintain the internal volume of a mixing tank within predetermined limits. One mixing apparatus includes multiple mixing shafts and paddles coupled to at least one kinetic energy source. Methods for fabricating sleeved paddle-containing mixing apparatuses are further provided. | 2009-12-31 |
20090323467 | SYSTEM AND TECHNIQUE TO OBTAIN STREAMER DEPTH AND SHAPE AND APPLICATIONS THEREOF - A technique includes obtaining first measurements acquired by sensors of a towed seismic streamer, which are indicative of an inclination of the streamer. Based at least in part on the measurements, a shape of the streamer while in tow is determined. | 2009-12-31 |
20090323468 | SEISMIC SENSOR CABLE - An apparatus includes a cable; and seismic sensors that are disposed in the cable. The apparatus also includes spacers that are distributed in the cable such that each seismic sensor is disposed in an interval of the cable separating a different adjacent pair of the spacers. The spacers of each pair are separated by at least twenty-five centimeters. | 2009-12-31 |
20090323469 | TECHNIQUE AND SYSTEM TO INCREASE THE LENGTH OF A SEISMIC SHOT RECORD - A system includes an interface and a processor. The interface receives seismic datasets, which are associated with multiple firings of a set of at least one seismic source. Each dataset is acquired by seismic sensors during a different time period of a sequence of time periods that are limited by times at which the set of seismic source(s) are fired. The processor, for each of the firings of the set of seismic source(s), generates an associated shot record based on information contained at least two of the datasets. | 2009-12-31 |
20090323470 | Method for attenuation of multiple reflections in seismic data - A method for attenuating multiple reflections in seismic signals includes coherency filtering the seismic signals. The seismic signals are low pass filtered and high pass filtered seismic signals at a frequency selected such that substantially only multiple reflections exist in the seismic signals above the frequency. A mask is generated having unity value where the high pass filtered signal amplitude exceeds a selected threshold. The mask has unity zero value for all other filtered signals. The mask value is multiplied by the low pass filtered signals. The multiplied signals are added to the high pass filtered signals and a coherency filter is applied to remove remaining primary energy to generate a model of the multiple reflections. The multiple reflection model is subtracted from the coherency filtered seismic signals. | 2009-12-31 |
20090323471 | Vector 3-Component 3-Dimensional Kirchhoff Prestack Migration - An apparatus and a method for migration of three components, 3-Dimensions seismic (3-C, 3-D) data acquired by down-hole receivers and surface seismic sources. This method utilizes full 3 components reflection wave field. It uses a dynamic, vector energy mapping method to image a reflection position and maps each time sample only to its reflected image point. Therefore, this method reduces unwanted data smearing and false mirror images. This method overcomes the weakness of using only a single component trace or pre-rotated three-component traces in the 1-C or 3-C 3-D VSP migration and produces better 3-D image. | 2009-12-31 |
20090323472 | SEISMIC SURVEY METHOD - A method of performing a 3-D seismic survey operation using (i) a plurality of vibroseis sources, and (ii) an array of seismic sensors arranged within a survey area wherein each vibroseis source emits a distinctive acoustic signal and each seismic sensor of the array is in a continuous state of readiness to detect reflected acoustic signals, the method comprising: (a) assigning vibroseis points (VPs) to each of the vibroseis sources; (b) independently moving each vibroseis source to assigned vibroseis point (VPs) where the vibroseis source emits its distinctive acoustic signal independently in time of the emission of the distinctive acoustic signals of the other vibroseis sources at their assigned vibroseis points (VPs); (c) recording the emission time of the distinctive acoustic signal by each vibroseis source at its assigned VPs together with the geographic position of the assigned VPs; (d) continuously listening for reflected acoustic signals using the array of seismic sensors and recording a time domain record of the reflected acoustic signals received by each seismic sensor of the array; wherein the reflected acoustic signals associated with the emission of a distinctive acoustic signal by a vibroseis source at an assigned VP are determined by: (i) extracting the reflected acoustic signals from the time domain records for the seismic sensors of the array during a predetermined listening time associated with the emission of the distinctive acoustic signal by the vibroseis source at the assigned VP; (ii) cross-correlating the extracted reflected acoustic signals with the distinctive emitted acoustic signal for the vibroseis source at the assigned VP thereby eliminating weakly correlated signals; and (iii) attenuating randomised cross-contamination in the cross-correlated extracted reflected acoustic signals from step (ii) using random noise attenuation techniques. | 2009-12-31 |
20090323473 | TARGET SEARCHING DEVICE, TARGET SEARCHING PROGRAM, AND TARGET SEARCHING METHOD - The target searching device includes: a sound source which transmits a sound wave into a propagation space; a transducer array placed in an area to receive a forward scattering wave which scatters forward from the target within the propagation space; a subtraction processing device which subtracts a traveling wave directly traveling towards the transducer array from a mixed wave of the forward scattering wave and the traveling wave so as to separate the forward scattering wave; a passive-phase conjugate processing device which performs passive-phase conjugate processing on the forward scattering wave separated by the subtraction processing device so as to generate a passive-phase conjugated signal of the forward scattering wave; an autocorrelation processing device which performs autocorrelation processing on the traveling wave to generate an autocorrelation processed signal of the traveling wave; and a correlation device which judges a similarity between the autocorrelation processed signal and the passive-phase conjugated signal. | 2009-12-31 |
20090323474 | SOUND SOURCE DETECTING DEVICE AND METHOD THEREOF - A sound source detecting device includes a number of sound wave detectors, a voltage comparator, and an analyzer. The sound wave detectors are positioned at different positions, and configured for detecting a sound wave, and each of the detectors produces an electrical signal associated to the sound wave detected by the detector and outputting the electrical signal. The voltage comparator is connected to the detectors and configured for receiving the electrical signals transmitted from the detectors and comparing the voltages of electrical signals to get the highest, second highest, and lowest voltages, then outputs a comparison result. The analyzer is connected to the voltage comparator and configured for identifying the position of a sound source producing the sound wave according to the comparison result transmitted from the voltage comparator and a predetermined principle stored in the analyzer, and then outputs an analyzing result indicating the direction of the sound source. | 2009-12-31 |
20090323475 | Thermoacoustic device - A sound wave generator includes one or more carbon nanotube films. The carbon nanotube film includes a plurality of carbon nanotubes substantially parallel to each other and joined side by side via van der Waals attractive force. The one or more carbon nanotube films produce sound by means of the thermoacoustic effect. | 2009-12-31 |
20090323476 | Thermoacoustic device - A sound wave generator includes one or more carbon nanotube films. The carbon nanotube film includes a plurality of carbon nanotubes substantially parallel to each other and joined side by side via van der Waals attractive force therebetween. At least part of the sound wave generator is supported by a supporting element. The one or more carbon nanotube films produce sound by means of the thermoacoustic effect. | 2009-12-31 |