53rd week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090321876 | SYSTEM WITH RADIO FREQUENCY INTEGRATED CIRCUITS - A semiconductor package comprises an integrated radio frequency circuit that may be provided in a semiconductor die. A ground plane may be attached to the semiconductor die. The ground plane is selectively patterned in a direction that is perpendicular to an inductor trace of an inductor of the radio frequency circuit. In some embodiments, the ground plane may be selectively patterned to allow an eddy current in the semiconductor package not to flow in opposite direction of a main current in the inductor. In one example, the ground plane may be a portion of the semiconductor package substrate or a die back metallization of the semiconductor die. | 2009-12-31 |
20090321877 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film. | 2009-12-31 |
20090321878 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode. | 2009-12-31 |
20090321879 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices ( | 2009-12-31 |
20090321880 | SEMICONDUCTOR DEVICE - A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region. | 2009-12-31 |
20090321881 | EPITAXIAL LIFT OFF STACK HAVING A PRE-CURVED HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a flattened, pre-curved support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process includes bending the pre-curved support handle to have substantial curvature while peeling the epitaxial material from the substrate and forming an etch crevice therebetween. Compression is maintained within the epitaxial material during the etching process. The flattened, pre-curved support handle may be formed by flattening a pre-curved support material. | 2009-12-31 |
20090321882 | EPITAZIAL GROWTH OF CRYSTALLINE MATERIAL - A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. | 2009-12-31 |
20090321883 | SILICON SUBSTRATE FOR SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - This method for manufacturing a silicon substrate for a solid-state imaging device, includes: a carbon compound layer forming step of forming a carbon compound layer on the surface of a silicon substrate; an epitaxial step of forming a silicon epitaxial layer on the carbon compound layer; and a heat treatment step of subjecting the silicon substrate having the epitaxial layer formed thereon to a heat treatment at a temperature of 600 and 800° C. for 0.25 to 3 hours so as to form gettering sinks that are complexes of carbon and oxygen below the epitaxial layer. This silicon substrate for a solid-state imaging device is manufactured by the above-mentioned method and includes: n epitaxial layer positioned on the surface of a silicon substrate; and a gettering layer which is positioned below the epitaxial layer and includes BMDs having a size of 10 to 100 nm at a concentration of 1.0×10 | 2009-12-31 |
20090321884 | METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER - A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion. | 2009-12-31 |
20090321885 | EPITAXIAL LIFT OFF STACK HAVING A UNIVERSALLY SHRUNK HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a universally shrinkable support handle onto the epitaxial material, wherein the universally shrinkable support handle contains a shrinkable material, and shrinking the support handle to form tension in the support handle and compression in the epitaxial material during a shrinking process. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature. | 2009-12-31 |
20090321886 | EPITAXIAL LIFT OFF STACK HAVING A UNIDIRECTIONALLY SHRUNK HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a unidirectionally induced-shrinkage support handle onto the epitaxial material, and shrinking the support handle tangential to reinforcement fibers therein to form tension in the support handle and compression in the epitaxial material during the shrinking process. The unidirectionally induced-shrinkage support handle contains a shrinkable material and reinforcement fibers extending unidirectional throughout the shrinkable material. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature. | 2009-12-31 |
20090321887 | METHOD OF FABRICATING AN ELECTROMECHANICAL STRUCTURE INCLUDING AT LEAST ONE MECHANICAL REINFORCING PILLAR - The invention relates to a method of fabricating an electromechanical structure presenting a first substrate ( | 2009-12-31 |
20090321888 | ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR - Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces. | 2009-12-31 |
20090321889 | Scribe Seal Connection - A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the scribe seal, possibly in more than one location, connecting an interior region to an exterior region. A feedthrough vertical seal surrounds the conductive element in the IC and connects to the scribe seal. A horizontal diffusion barrier connects to the scribe seal and the feedthrough vertical seal. The feedthrough vertical seal, the horizontal diffusion barrier and the IC substrate form a continuous barrier to chemical impurities around the conductive element in the interior region. The conductive structure includes any combination of a doped region in an active area, an MOS transistor gate layer, and one or more interconnect metal layers. The feedthrough is compatible with aluminum and copper interconnect metallization. | 2009-12-31 |
20090321890 | Protective Seal Ring for Preventing Die-Saw Induced Stress - A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer. | 2009-12-31 |
20090321891 | METHOD AND APPARATUS FOR GENERATING RETICLE DATA - A method for generating reticle data for forming a reticle. The method includes recognizing a non-layout region free from main chips in a process pattern, dividing the non-layout region into a plurality of rectangular non-layout regions, generating scribe data using the plurality of divided rectangular non-layout region as a plurality of dummy chips, and generating a dummy pattern for each of the dummy chips. | 2009-12-31 |
20090321892 | SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES HAVING VOIDS - A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package. | 2009-12-31 |
20090321893 | Multi-die integrated circuit device and method - In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die. | 2009-12-31 |
20090321894 | Multi-functional linear siloxane compound, a siloxane polymer prepared from the compound, and a process for forming a dielectric film by using the polymer - A novel multi-functional linear siloxane compound, a siloxane polymer prepared from the siloxane compound, and a process for forming a dielectric film by using the siloxane polymer. The linear siloxane polymer has enhanced mechanical properties (e.g., modulus), superior thermal stability, a low carbon content and a low hygroscopicity and is prepared by the homopolymerization of the linear siloxane compound or the copolymerization of the linear siloxane compound with another monomer. A dielectric film can be produced by heat-curing a coating solution containing the siloxane polymer which is highly reactive. The siloxane polymer prepared from the siloxane compound not only has satisfactory mechanical properties, thermal stability and crack resistance, but also exhibits a low hygroscopicity and excellent compatibility with pore-forming materials, which leads to a low dielectric constant. Furthermore, the siloxane polymer retains a relatively low carbon content but a high SiO | 2009-12-31 |
20090321895 | SILICON THIN-FILM AND METHOD OF FORMING SILICON THIN-FILM - Issue Providing a silicon film which can prevent damage of electronic devices formed on a substrate from occurrence, can prevent apparatus arrangement from becoming large-scale one, can improve coherency of a silicon thin film to a substrate, and is hardly happened crack and/or flaking, and providing a method for forming the silicon thin film. | 2009-12-31 |
20090321896 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - There is provided a semiconductor device | 2009-12-31 |
20090321897 | METHOD AND APPARATUS OF POWER RING POSITIONING TO MINIMIZE CROSSTALK - A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire. | 2009-12-31 |
20090321898 | CONFORMAL SHIELDING INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads. | 2009-12-31 |
20090321899 | INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES - An integrated circuit package system includes: providing a finger lead having a side with an outward exposed area and an inward exposed area separated by a lead cavity; positioning a chip adjacent the finger lead and connected to the finger lead; and a stack encapsulant encapsulating the chip and the finger lead with the outward exposed area and the inward exposed area of the finger lead substantially exposed. | 2009-12-31 |
20090321900 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure. | 2009-12-31 |
20090321901 | THERMALLY BALANCED HEAT SINKS - According to example embodiments, a device configured to dissipate heat from a first chip and a second chip on a multi-chip package includes a primary heat sink configured to contact an upper surface of the first chip, a secondary heat sink configured to contact an upper surface of the second chip, the secondary heat sink disposed within the primary heat sink and movable in relation to the primary heat sink, and a thermally conductive substance disposed in contact with the primary heat sink and the secondary heat sink. | 2009-12-31 |
20090321902 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer. | 2009-12-31 |
20090321903 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate | 2009-12-31 |
20090321904 | Semiconductor device and semiconductor integrated circuit - The present invention provides a semiconductor device, including: a semiconductor substrate having a circuit formed thereon; a mounting substrate cemented to a rear face of the semiconductor substrate; a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal; a plurality of wires individually cemented at one end thereof to the pads; and a plurality of wire cemented elements formed on the mounting substrate and cemented to the other end of the wires. | 2009-12-31 |
20090321905 | Multi-Package Ball Grid Array - A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages. | 2009-12-31 |
20090321906 | SEMICONDUCTOR DEVICE WITH PACKAGE TO PACKAGE CONNECTION - A semiconductor package comprises a first package; a second package that is provided on the first package; and a first interconnect that comprises a bump to couple to the first package and a base material layer to cover the bump, wherein the second package is supported on the base material layer that is coupled to the bump. | 2009-12-31 |
20090321907 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier. | 2009-12-31 |
20090321908 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION - A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect. | 2009-12-31 |
20090321909 | Active Thermal Control for Stacked IC Devices - Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired. | 2009-12-31 |
20090321910 | SEMICONDUCTOR PACKAGE, STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME, AND A METHOD FOR SELECTING ONE SEMICONDUCTOR CHIP IN A STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison. | 2009-12-31 |
20090321911 | Semiconductor Package and Manufacturing Method Thereof - Provided are a semiconductor package and a manufacturing method thereof. A semiconductor package according to an embodiment comprises a chip part on a board, a mold member, and a plated layer on the mold member. The plated layer comprises an electrode pattern connected to a pattern of the board. The electrode pattern of the plated layer can be mounted at least one of at least one a chip part and at least one another semiconductor package. | 2009-12-31 |
20090321912 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate. | 2009-12-31 |
20090321913 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LOCKING TERMINAL - An integrated circuit package system includes: forming a first locking terminal having a first terminal recess with a top portion of the first terminal recess narrower than a bottom portion of the first terminal recess; connecting an integrated circuit and the first locking terminal; and forming a package encapsulation over the integrated circuit and in the first locking terminal. | 2009-12-31 |
20090321914 | PRODUCTION OF INTEGRATED CIRCUIT CHIP PACKAGES PROHIBITING FORMATION OF MICRO SOLDER BALLS - Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability. | 2009-12-31 |
20090321915 | System-in-package and manufacturing method of the same - The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via. | 2009-12-31 |
20090321916 | SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE - A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material. | 2009-12-31 |
20090321917 | Electrical Component - The invention discloses an electrical component with a carrier substrate, on which at least one semiconductor chip is mounted. Terminal areas are arranged on the underside of the carrier substrate and contact areas designed for the assembly with semiconductor chips are arranged on the upper side. The carrier substrate has a functional area that is divided into sections, wherein each section is assigned at least one function such as, e.g., as a filter, a frequency-separating filter, a balun, etc. A separate area of the carrier substrate is assigned to each section. The following applies to at least one of the sections: the contact area and/or the terminal area that is conductively connected to the section lies outside the base of this section. The connecting line that conductively connects the input or output of the respective section to the contact area and/or the terminal area is preferably shielded from the section by a ground area. | 2009-12-31 |
20090321918 | CHIP PACKAGE - A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved. | 2009-12-31 |
20090321919 | SEMICONDUCTOR DEVICE - The semiconductor device | 2009-12-31 |
20090321920 | Semiconductor device and method of manufacturing the same - A semiconductor device includes: a substrate; a plurality of connection pads provided on the substrate; a semiconductor chip; a plurality of electrode pads provided on the semiconductor chip; a plurality of wires electrically connecting the connection pads and the electrode pads; and a seal covering the semiconductor chip and the wires. The semiconductor chip is distanced from the substrate while being placed inside a periphery of the substrate. The seal intervenes between the semiconductor chip and the substrate. | 2009-12-31 |
20090321921 | EMBEDDED WIRING BOARD, SEMICONDUCTOR PACKAGE INCLUDING THE SAME AND METHOD OF FABRICATING THE SAME - Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings. | 2009-12-31 |
20090321922 | SELF-HEALING THERMAL INTERFACE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material. | 2009-12-31 |
20090321923 | MAGNETIC PARTICLE-BASED COMPOSITE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity. | 2009-12-31 |
20090321924 | Power Semiconductor Module - A power semiconductor module includes: a power semiconductor device; a first heat dissipation plate; a second heat dissipation plate; a first channel; a second channel; a first channel wall; a second channel wall; a first refrigerant outlet provided on the first channel wall in a position corresponding to the power semiconductor device; a second refrigerant outlet provided on the second channel wall in a position corresponding to the power semiconductor device; first pin fins provided on at least one of the first heat dissipation plate and the second heat dissipation plate so as to be arranged radially around at least one of the first refrigerant outlet and the second refrigerant outlet; and second pin fins arranged in a staggered manner or in a tessellated manner around the first pin fins that are arranged radially. | 2009-12-31 |
20090321925 | INJECTION MOLDED METAL IC PACKAGE STIFFENER AND PACKAGE-TO-PACKAGE INTERCONNECT FRAME - In some embodiments, an injection molded metal IC package stiffener and package-to-package interconnect frame is presented. In this regard, an apparatus is introduced comprising a microelectronic device package substrate, a microelectronic device coupled with a top surface of the package substrate, and an injection-molded, metal stiffener coupled with the package substrate, wherein the stiffener includes a central opening and at least partially surrounds the microelectronic device, and wherein the stiffener includes a plurality of vias that each couple a contact on a bottom surface of the stiffener with a respective contact on a top surface of the stiffener. Other embodiments are also disclosed and claimed. | 2009-12-31 |
20090321926 | MOUNTING STRUCTURE AND MOUNTING METHOD - A mounting structure of the present invention includes a semiconductor element | 2009-12-31 |
20090321927 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate | 2009-12-31 |
20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 2009-12-31 |
20090321929 | Standing chip scale package - A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed. | 2009-12-31 |
20090321930 | SEMICONDUCTOR WITH BOTTOM-SIDE WRAP-AROUND FLANGE CONTACT - A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact. | 2009-12-31 |
20090321931 | Semiconductor device and method of manufacturing the same - A semiconductor device and a method of manufacturing the semiconductor device maintain an insulating distance between contact plugs and wiring lines formed on the contact plugs by using an etch mask pattern for forming contact holes. The device comprises a substrate comprising a plurality of conductive areas; an inter-layer insulating layer on the substrate having a plurality of contact holes through which the conductive areas are exposed; a first insulating layer covering the top surface of the inter-layer insulating layer; a plurality of contact plugs respectively connected to the plurality of conductive areas through the plurality of contact holes, the plurality of contact plugs having top surfaces a distance from each of which to a top surface of the substrate is less than a distance from the top surface of the inter-layer insulating layer to the top surface of the substrate; a plurality of ring-shaped insulating spacers covering inner sidewalls of the inter-layer insulating layer, inner sidewalls of the first insulating layer, and outer edge areas of top surfaces of the contact plugs so as to expose center areas of the top surfaces of the contact plugs in the contact holes; and a plurality of wiring lines above the first insulating layer and on the insulating spacers and respectively electrically connected to the plurality of contact plugs. | 2009-12-31 |
20090321932 | Coreless substrate package with symmetric external dielectric layers - A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package. | 2009-12-31 |
20090321933 | Structure to Facilitate Plating Into High Aspect Ratio Vias - Improved high aspect ratio vias and techniques for the formation thereof are provided. In one aspect, a method of fabricating a copper plated high aspect ratio via is provided. The method comprises the following steps. A high aspect ratio via is etched in a dielectric layer. A diffusion barrier layer is deposited into the high aspect ratio via and over one or more surfaces of the dielectric layer. A copper layer is deposited over the diffusion barrier layer. A ruthenium layer is deposited over the copper layer. The high aspect ratio via is filled with copper plated onto the ruthenium layer. A copper plated high aspect ratio via formed by this method is also provided. | 2009-12-31 |
20090321934 | SELF-ALIGNED CAP AND BARRIER - A semiconductor device comprising an insulator layer formed on a substrate; a via formed by etching into the insulator layer to a first depth; a first metal layer formed over the insulator layer; a second metal layer deposited on the first metal layer to substantially fill the via; a metal-dopant alloy layer deposited over the second metal, wherein the dopant is diffused by annealing through the second metal layer and the first metal layer deposited in the via, such that the dopant migrates to a boundary between the first metal layer and the insulator to form a barrier; and an etch stop layer deposited over the via after planarization of the via and the insulator layer to form a barrier cap. | 2009-12-31 |
20090321935 | Methods of forming improved electromigration resistant copper films and structures formed thereby - Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a doping material on an overburden region of a conductive structure, diffusing a portion of the doping material into a portion of the conductive structure, and then removing the overburden region. | 2009-12-31 |
20090321936 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE, COMPUTER PROGRAM AND STORAGE MEDIUM - Provided is a semiconductor device which has excellent adhesiveness to a copper film and a base film thereof and has a small resistance between wirings. The semiconductor device includes a porous insulating layer (SIOC film | 2009-12-31 |
20090321937 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess. | 2009-12-31 |
20090321938 | Methods of Manufacturing Copper Interconnect Systems - An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region. | 2009-12-31 |
20090321939 | Through Silicon via Bridge Interconnect - An integrated circuit bridge interconnect system includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die. | 2009-12-31 |
20090321940 | Method for Manufacturing Contact Openings, Method for Manufacturing an Integrated Circuit, an Integrated Circuit - An integrated circuit is described including a first and a second plurality of conductor lines, each of the lines being separated from an adjacent line by a spacer dielectric and capped with a first and second dielectric cap material, respectively. A contact element is embedded in a covering dielectric layer with electrical contact to one of the first plurality of conductor lines in a contact portion, while being separated from a line adjacent to the contacted line only by the second cap material. | 2009-12-31 |
20090321941 | Phase memorization for low leakage dielectric films - Embodiments of a phase-stable amorphous high-κ dielectric layer in a device and methods for forming the phase-stable amorphous high-κ dielectric layer in a device are generally described herein. Other embodiments may be described and claimed. | 2009-12-31 |
20090321942 | Method of forming stacked trench contacts and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 2009-12-31 |
20090321943 | SEED LAYER FOR REDUCED RESISTANCE TUNGSTEN FILM - Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed. | 2009-12-31 |
20090321944 | SEMICONDUCTOR DEVICE WITH IMPROVED INTERCONNECTION OF CONDUCTOR PLUG - The semiconductor device comprises a conductor plug | 2009-12-31 |
20090321945 | SIDE WALL PORE SEALING FOR LOW-K DIELECTRICS - A dual damascene process for forming conductive interconnects on an integrated circuit die. The process comprises providing a layer ( | 2009-12-31 |
20090321946 | PROCESS FOR FABRICATING AN INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A PROCESS REQUIRING A VOLTAGE THRESHOLD BETWEEN A METAL LAYER AND A SUBSTRATE - A process for fabricating an electronic integrated circuit comprising a multi-layer interconnect stack. A structure ( | 2009-12-31 |
20090321947 | SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. | 2009-12-31 |
20090321948 | METHOD FOR STACKING DEVICES - A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process. | 2009-12-31 |
20090321949 | BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed. | 2009-12-31 |
20090321950 | STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING - A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication. | 2009-12-31 |
20090321951 | STACKED WIRE BONDED SEMICONDUCTOR PACKAGE WITH LOW PROFILE BOND LINE - A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes. | 2009-12-31 |
20090321952 | WIRE ON WIRE STITCH BONDING IN A SEMICONDUCTOR DEVICE - A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first semiconductor die may be electrically coupled to the substrate with a plurality of stitches in a forward ball bonding process. The second semiconductor die may in turn be electrically coupled to the first semiconductor die using a second set of stitches bonded between the die bond pads of the first and second semiconductor die. The second set of stitches may each include a lead end having a stitch ball that is bonded to the bond pads of the second semiconductor die. The tail end of each stitch in the second set of stitches may be wedge bonded directly to lead end of a stitch in the first set of stitches. | 2009-12-31 |
20090321953 | CIRCUIT SUBSTRATE HAVING CIRCUIT WIRE FORMED OF CONDUCTIVE POLARIZATION PARTICLES, METHOD OF MANUFACTURING THE CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE CIRCUIT WIRE - A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit. | 2009-12-31 |
20090321954 | STACKED SEMICONDUCTOR PACKAGE ELECTRICALLY CONNECTING SEMICONDUCTOR CHIPS USING OUTER SURFACES THEREOF AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips. | 2009-12-31 |
20090321955 | Securing integrated circuit dice to substrates - A conductive material may be jet dispensed (i.e. jet sprayed) on an integrated circuit die and a bond pad to form a conformal electrical connection on and between the bond pad and the die. In some cases, a smaller package footprint and/or height may result. | 2009-12-31 |
20090321956 | Layered chip package and method of manufacturing same - A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces. | 2009-12-31 |
20090321957 | Layered chip package and method of manufacturing same - A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals. | 2009-12-31 |
20090321958 | SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF - Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device. | 2009-12-31 |
20090321959 | Chip Arrangement and Method of Manufacturing a Chip Arrangement - A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side. | 2009-12-31 |
20090321960 | SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor memory chips are stacked on a first main surface of a wiring board, and an interposer chip is stacked on the plurality of semiconductor chips, and a semiconductor controller chip is stacked on the interposer chip. The plurality of semiconductor memory chips are independently and electrically connected with inner connecting terminals formed on the wiring board, respectively, and independently controlled by the semiconductor controller chip which is electrically connected with another inner connecting terminals formed on the wiring board via the interposer chip. | 2009-12-31 |
20090321961 | Method of Packaging a Die - A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads. | 2009-12-31 |
20090321962 | MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. | 2009-12-31 |
20090321963 | INJECTION MOLDED METAL STIFFENER FOR PACKAGING APPLICATIONS - In some embodiments, an injection molded metal stiffener for packaging applications is presented. In this regard, an apparatus is introduced comprising a microelectronic device package substrate, a microelectronic device coupled with a top surface of the package substrate, and an injection-molded, metal stiffener coupled with the package substrate, wherein the stiffener includes a central opening and at least partially surrounds the microelectronic device. Other embodiments are also disclosed and claimed. | 2009-12-31 |
20090321964 | Stress Buffer Layer for Ferroelectric Random Access Memory - An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer. | 2009-12-31 |
20090321965 | ELECTRONIC DEVICE HAVING A WIRING SUBSTRATE - A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer. | 2009-12-31 |
20090321966 | Quench Zone Design Using Spray Nozzles - A liquid distribution device is presented for the collection and distribution of liquid between reactor or adsorbent beds. The device includes a liquid collection tray, a mixing chamber in fluid communication with the liquid collection tray, a liquid distribution tray in fluid communication with the mixing chamber, and a plurality of nozzles for delivering the liquid over the top of a reactor or adsorbent bed. | 2009-12-31 |
20090321967 | Auxiliary cooling apparatus - For fire prevention, an auxiliary cooling apparatus applied to an outdoor condenser of a refrigerating cycle is provided with a filter which has air permeability and is arranged to oppose to an ambient air intake port of the condenser, and cools ambient air by heat exchange between the ambient air sucked into the ambient air intake port through the filter and water supplied to the filter, lots of implanted fibers ( | 2009-12-31 |
20090321968 | Structure of cooling tower - An improved structure of cooling tower includes a fan housing with a fan disposed therein, induction openings distributed on the fan housing and located below the fan, and a diffuser stack disposed at one end surface of the fan housing. In operation, cold air is drawn into the cooling tower by the fan through inlet openings of the cooling tower so as to exchange heat with the condensing water within a water chiller. When warm and wet air is drawn out of the cooling tower and the warm and wet air outside the cooling tower is induced in through the induction openings and then is drawn out, circulation reflux of warm and wet air, which tends to occur in conventional cooling towers, can be avoided and therefore increase the efficiency of the water chiller. | 2009-12-31 |
20090321969 | OPTICAL ELEMENT MOLDING METHOD - An optical element molding method provides to mold an optical element without a defective configuration such as a groove on the outer surface when one optical element is molded by placing different molding materials one on another. | 2009-12-31 |
20090321970 | OPHTHALMIC LENS MOLDS PARTS WITH SILOXANE WAX - This invention discloses improved mold parts for ophthalmic lenses fashioned from a thermal plastic resin compounded with a siloxane wax resulting in a thermal plastic compound with a deionized water contact angle that is greater than the deionized water contact angle of the pure thermal plastic resin. The mold parts can be used in manufacturing processes, such as, for example: continuous, in-line or batched processes. | 2009-12-31 |
20090321971 | Methods of Manufacturing Dental Restorations Using Nanocrystalline Materials - Dental articles are produced using relatively low sintering temperatures to achieve high density dental articles exhibiting strengths equal to and greater than about 700 MPa. Ceramic powders comprised of nanoparticulate crystallites are used to manufacture dental articles. The ceramic powders may include sintering agents, binders and other similar additives to aid in the processing of the ceramic powder into a dental article. The ceramic powders may be processed into dental articles using various methods including, but not limited to, injection molding, gel-casting, slip casting, or electroforming, hand, cad/camming and other various rapid prototyping methods. The ceramic powder may be formed into a suspension, pellet, feedstock material or a pre-sintered blank prior to forming into the dental article. | 2009-12-31 |
20090321972 | Vapor smoothing surface finishing system - A system and method is provided for vapor smoothing a rapid manufactured three-dimensional object. A cabinet housing has a sealable interior. A heated vapor chamber in the interior of the cabinet housing contains solvent that is vaporizable to fill the vapor chamber with vapor for smoothing the object when the object is placed in the vapor chamber. A drying chamber is also provided in the interior of the cabinet housing that is separate from the vapor chamber for drying the object when the object is moved from the vapor chamber to the drying chamber. | 2009-12-31 |
20090321973 | Method Of Partially Engraving Foamed Plastic Extrusions - A method of only partially engraving foamed plastic extrusions and foamed plastic extrusions so engraved, the method comprising formulating the plastic to leave residual foaming agents after extrusion and contacting one or both sides of the extrusion with an embossed engraving roller or rollers controlled to limit penetration and contact of the foamed plastic with the outer portions only of the roller embossment to activate residual foaming agents to foam the plastic around such penetrating portions. | 2009-12-31 |
20090321974 | ROLL FED FLOTATION/IMPINGEMENT AIR OVENS AND RELATED THERMOFORMING SYSTEMS FOR CORRUGATION-FREE HEATING AND EXPANDING OF GAS IMPREGNATED THERMOPLASTIC WEBS - Disclosed herein are roll fed air heated flotation ovens and related thermoforming systems, assemblies, and machines that enable the corrugation-free expansion of a gas impregnated thermoplastic web passing through an oven chamber (without use of a pin-chain assembly), as well as to related methods. In an embodiment, a gas impregnated thermoplastic web is conveyed and expanded through an elongated air heated oven chamber, wherein the elongated oven chamber includes a plurality of downwardly directed heated air nozzles positioned at regular intervals along and within the upper portion of the oven chamber, and a plurality of upwardly directed heated air nozzles positioned at regular intervals along and within the lower portion of the oven chamber, but staggered apart from the downwardly directed heated air nozzles such that the gas impregnated thermoplastic material web undulates in an up and down wavelike fashion, thereby minimizing sagging, bagging, puckering, and/or buckling of the web. | 2009-12-31 |
20090321975 | Apparatus and method for the introduction of a foaming agent into a polymer melt - The apparatus for the production of foams includes an extrusion device for the plastification of a polymer melt, a heat exchanger for the cooling of the polymer melt, and also a connection piece for the connection of the extrusion apparatus to the heat exchanger. The connection piece contains a metering device for the introduction of a foaming agent into the polymer melt. | 2009-12-31 |