52nd week of 2021 patent applcation highlights part 82 |
Patent application number | Title | Published |
20210408975 | SWITCHED-CAPACITOR AMPLIFIER CIRCUIT - A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor. | 2021-12-30 |
20210408976 | MULTI-ZONE RADIO FREQUENCY TRANSISTOR AMPLIFIERS - RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure. | 2021-12-30 |
20210408977 | WIDEBAND RF SHORT/DC BLOCK CIRCUIT FOR RF DEVICES AND APPLICATIONS - Inductance-capacitance (LC) resonators having different resonant frequencies, and radio frequency (RF) transistor amplifiers including the same. One usage of such LC resonators is to implement RF short/DC block circuits. A RF transistor amplifier may include a transistor on a base of the RF transistor amplifier coupled to an input and an output of the RF transistor amplifier; a first inductance-capacitance (LC) resonator comprising a first inductance and a first capacitance; and a second LC resonator comprising a second inductance and a second capacitance. The first LC resonator may be configured to resonate at a first frequency, and the second LC resonator may be configured to resonate at a second frequency different from the first frequency. | 2021-12-30 |
20210408978 | RADIO FREQUENCY TRANSISTOR AMPLIFIERS HAVING LEADFRAMES WITH INTEGRATED SHUNT INDUCTORS AND/OR DIRECT CURRENT VOLTAGE SOURCE INPUTS - A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die. | 2021-12-30 |
20210408979 | RADIO FREQUENCY (RF) TRANSISTOR AMPLIFIER PACKAGES WITH IMPROVED ISOLATION AND LEAD CONFIGURATIONS - A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed. | 2021-12-30 |
20210408980 | MULTI-FREQUENCY BAND COMMUNICATION BASED ON FILTER SHARING - The present disclosure relates to systems and methods for operating transceiver circuitry to transmit or receive signals on various frequency ranges. To do so, a transmitter or a receiver of the transceiver circuitry is selectively coupled to or uncoupled from an antenna of the transceiver circuitry. Additionally, radio frequency filters may be individually or collectively coupled to and/or uncoupled from the antenna to filter different frequencies in the transmitting or receiving signals. | 2021-12-30 |
20210408981 | DIGITAL POWER AMPLIFIER AND METHOD OF OPTIMISING A DIGITAL POWER AMPLIFIER - A digital power amplifier for a signal, the digital power amplifier comprising: | 2021-12-30 |
20210408982 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes a first power amplifier, a balun, a second power amplifier, and a third power amplifier. The second and third power amplifiers each include unit bipolar transistors each including a first terminal electrically connected to a reference potential, a second terminal, and a third terminal that outputs an amplified signal; a common input terminal electrically connected to the second terminals of the transistors and receives an RF signal; a common bias terminal electrically connected to the second terminals of the transistors and receives a bias current; a common output terminal electrically connected to the third terminals of the transistors and outputs the amplified signal; and resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the transistors and cuts a DC component of the bias current. | 2021-12-30 |
20210408983 | Digital Power Amplifier with RF Sampling Rate and Wide Tuning Range - A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal. | 2021-12-30 |
20210408984 | DUAL CONNECTIVITY POWER AMPLIFIER SYSTEM - Aspects of this disclosure relate to a dual connectivity power amplifier system. The power amplifier system includes first and second power amplifiers that are concurrently active in a dual connectively mode. The first power amplifier is active in a different mode. A switch electrically connects the first power amplifier to different radio frequency signal paths in the dual connectivity mode and the different mode. Related methods, power amplifier modules, and wireless communication devices are disclosed. | 2021-12-30 |
20210408985 | MULTI-MODE POWER AMPLIFIER SYSTEM AND RELATED WIRELESS DEVICES AND METHODS - Aspects of this disclosure relate to a multi-mode power amplifier system. A first power amplifier is configured to provide a radio frequency signal associated with a different radio access technology in a first mode than in a second mode. A second power amplifier is configured to be active in the first mode such that the first power amplifier and the second power amplifier are concurrently active in the first mode. A switch can electrically connect the output of the first power amplifier to different radio frequency signal path in the first mode than in the second mode. Related methods, power amplifier modules, and wireless communication devices are disclosed. | 2021-12-30 |
20210408986 | NOVEL PROGRAMMABLE CHOPPING ARCHITECTURE TO REDUCE OFFSET IN AN ANALOG FRONT END - An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed. | 2021-12-30 |
20210408987 | BALUN DEVICE AND DIFFERENTIAL PHASE SHIFTER - Balun device and differential phase shifter are provided. The balun device includes a first primary coil, a first secondary coil, a second primary coil and a second secondary coil, the first primary coil having a first terminal receiving a first differential signal, and a second terminal outputting a first in-phase component, the first secondary coil having a first terminal outputting a first component orthogonal to the first in-phase component, and a second terminal coupled to AC ground, the second primary coil having a first terminal receiving a second differential signal, and a second terminal outputting a second in-phase component; the second secondary coil having a first terminal outputting a second component orthogonal to the second in-phase component, and a second terminal coupled to AC ground; phase differences between the first and second differential signals, between the first and second in-phase components, between the first and second orthogonal component are 180°. | 2021-12-30 |
20210408988 | A SECOND GENERATION CURRENT CONVEYOR (CCII) HAVING A TUNABLE FEEDBACK NETWORK - A Second-Generation Current Conveyor (CCII) has a three-port network with ports designated as X, Y, and Z, wherein the CCII includes a tunable feedback network. The tunable feedback network may be provided between at least two of the ports, e.g., ports Z and Y. The tunable feedback network may comprise a tunable RC (Resister-Capacitor) network which may be provided by solid-state components such as a MOS (Metal-Oxide Semiconductor) device or a MOS resistor (for the resistive element) and a varactor (for the capacitive element). | 2021-12-30 |
20210408989 | PROGRAMMABLE BASEBAND FILTER FOR SELECTIVELY COUPLING WITH AT LEAST A PORTION OF ANOTHER FILTER - An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles. | 2021-12-30 |
20210408990 | AMPLIFIER CIRCUIT STRUCTURE AND METHOD FOR CONTROLLING CIRCUIT - An amplifier circuit structure can include an amplifier located in a main path, and a first switch located in a bypass. One end of a second switch is a signal output end of the amplifier circuit structure, and the other end of the second switch is configured to selectively connect to a signal output end of the bypass or a signal output end of the main path. The first and second switches are configured to control their respective operating states when a first instruction is received, such that the main path is connected to the signal input end and the signal output end of the amplifier circuit structure; and to control their respective operating states when a second instruction is received, such that the bypass is connected to the signal input end of the amplifier circuit structure and the signal output end of the amplifier circuit structure. | 2021-12-30 |
20210408991 | TOUCHLESS INTERACTION USING AUDIO COMPONENTS - The present teachings relate to an electronic device comprising: a first module for generating an audio signal; a second module for generating an ultrasonic signal; a mixer for generating a combined signal; a transmitter for outputting an acoustic signal dependent upon the combined signal; and, a processing means for controlling the ultrasonic signal; wherein, in response to receiving a first instruction signal for initiating the ultrasonic signal, the processing means is configured to increase the amount of the ultrasonic signal in the combined signal from an essentially zero value to a predetermined value over a predetermined enable time-period. The present teachings also relate to an electronic device configured to decrease the amount of the ultrasonic signal in the combined signal from an essentially zero value to a predetermined value over a predetermined disable time-period, and to an electronic device configured to remove the audio signal from the combined signal whilst preventing pop-noise, and to an electronic device capable of replacing the ultrasonic signal whilst minimizing the processing time. The present teachings further relate to a method for reducing the occurrence of pop noise in an acoustic signal associated with: initiating the ultrasonic signal in the combined signal, terminating the ultrasonic signal in the combined signal, terminating the audio signal in the combined signal, and replacing the ultrasonic signal in the combined signal. The present teachings also relate to a computer software product for implementing any of the method steps disclosed herein, and to a computer storage medium storing the computer software herein disclosed. | 2021-12-30 |
20210408992 | TUNABLE FILTER WITH MUTUALLY COUPLED INDUCTORS - Aspects of this disclosure relate to a tunable filter with tunable rejection. The tunable filter includes mutually coupled inductors and a tunable impedance circuit electrically connected to at least one of the mutually coupled inductors. The tunable impedance circuit is configured to adjust at least two notches in a frequency response of the tunable filter by changing a state of a switch. The tunable filter can filter a radio frequency signal. Related methods, radio frequency systems, radio frequency modules, and wireless communication devices are also disclosed. | 2021-12-30 |
20210408993 | RF Impedance Measurement Circuit - An RF impedance measurement circuit includes a sensing capacitor connectable with an RF signal path; a first amplitude detector and a first frequency divider, each coupled, with the measurement circuit in operation, to the RF signal path at a first terminal of the sensing capacitor; a second amplitude detector and a second frequency divider, each coupled, with the measurement circuit in operation, to a second terminal of the sensing capacitor; and a phase detection circuit connected to an output of the first frequency divider and to an output of the second frequency divider. | 2021-12-30 |
20210408994 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a support substrate, a piezoelectric film, a functional electrode, and a support. The support substrate includes a cavity. The piezoelectric film is provided on the support substrate to cover the cavity. The functional electrode is provided on the piezoelectric film to overlap the cavity when viewed in a plan view. The support is in the cavity of the support substrate to support the piezoelectric film. The functional electrode includes electrodes arranged in a direction crossing the thickness direction of the piezoelectric film. The electrodes include a first electrode and a second electrode. The first electrode and the second electrode oppose each other in a direction crossing the thickness direction of the piezoelectric film and are connected to different potentials. Adjacent ones of the electrodes overlap each other in a direction orthogonal to a longitudinal direction of the first electrode. | 2021-12-30 |
20210408995 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes an energy confinement layer, a piezoelectric film, and an IDT electrode laminated on a support substrate. Acoustic velocity adjustment films are at least partially provided between the piezoelectric film and the support substrate and are made of a material different from that of the piezoelectric film. | 2021-12-30 |
20210408996 | TWO-STAGE LATERAL BULK ACOUSTIC WAVE FILTER - Acoustic wave filter devices are disclosed. A device includes a layer providing or on a topmost layer of an acoustic reflector. The intermediary layer has a first region and a second region. The first region has a first layer thickness and the second region has a second layer thickness different from the first layer thickness. The device includes a first multilayer stack on the first region and a second multilayer stack on the second region of the intermediary layer. Each of the first and the second stacks includes a piezoelectric layer on a counter electrode that is located on the respective region, an input and an output electrode. Application of a radio frequency voltage between the input electrode and the counter electrode layer of the first stack creates acoustic resonance modes in the piezoelectric layer between the input and output electrodes of the first and the second stack. | 2021-12-30 |
20210408997 | SURFACE ACOUSTIC WAVE DEVICE - A surface acoustic wave device includes a piezoelectric substrate and a pair of IDT electrodes. The pair of IDT electrodes includes a pair of busbars and multiple electrode fingers. The pair of busbars are formed on the piezoelectric substrate. The electrode fingers extend in a comb shape from each of the busbars toward the opposing busbar. The pair of IDT electrodes has an intersection region as a region where the electrode fingers connected to one busbar and the electrode fingers connected to another busbar are intersected when viewed along an arrangement direction of the electrode fingers. The electrode finger in a non-intersection region outside the intersection region has a thickness thinner than a thickness of the electrode finger in the intersection region. | 2021-12-30 |
20210408998 | ELECTRONIC COMPONENT - An electronic component comprises a piezoelectric substrate ( | 2021-12-30 |
20210408999 | ELASTIC WAVE DEVICE, SPLITTER, AND COMMUNICATION APPARATUS - An elastic wave device includes a substrate, a multilayer film located on the substrate, a piezoelectric layer located on the multilayer film, resonators located on the piezoelectric layer and including an IDT electrode, and a protective film located on the resonators. The resonators include a first resonator and a second resonator having a higher resonant frequency than the first resonator. A thickness of the protective film on the first resonator is larger than the thickness of the protective film on the second resonator. | 2021-12-30 |
20210409000 | Piezoelectric MEMS Resonators based on Porous Silicon Technologies - A piezoelectric MEMS resonator is provided. The resonator comprises a single crystal silicon microstructure suspended over a buried cavity created in a silicon substrate and a piezoelectric resonance structure located on the microstructure. The resonator is designed and fabricated based on porous silicon related technologies including selective formation and etching of porous silicon in silicon substrate, porous silicon as scarified material for surface micromachining and porous silicon as substrate for single crystal silicon epitaxial growth. All these porous silicon related technologies are compatible with CMOS technologies and can be conducted in a standard CMOS technologies platform. | 2021-12-30 |
20210409001 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATOR WITH SYMMETRIC DIAPHRAGM - Acoustic resonator devices and filters are disclosed. An acoustic resonator includes a substrate having a surface. A back surface of a single-crystal piezoelectric plate is attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm spanning a cavity in the substrate. An interdigital transducer (IDT) is formed on a front surface of the piezoelectric plate with interleaved IDT fingers of the IDT disposed on the diaphragm. Back-side fingers are formed the back surface of the diaphragm. A pitch of the IDT fingers and a pitch of the back-side fingers are substantially equal. | 2021-12-30 |
20210409002 | TRANSCONDUCTOR CIRCUITS WITH PROGRAMMABLE TRADEOFF BETWEEN BANDWIDTH AND FLICKER NOISE - Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise. | 2021-12-30 |
20210409003 | REFLECTION ATTENUATION DEVICE FOR A BUS OF A BUS SYSTEM, AND METHOD FOR ATTENUATING REFLECTIONS DURING A DATA TRANSFER IN A BUS SYSTEM - A reflection attenuation device for a bus of a bus system and a method for attenuating reflections during a data transfer in a bus system. The reflection attenuation device may close off a free end of bus lines of the bus in a transceiver device of a user station of the bus system. Alternatively, the reflection attenuation device may be connected to a branch point of the bus which is a star point or is used to connect a user station to the bus. Thus, bus users in a vehicle trailer are also connectable to the bus system of the vehicle, as needed. The reflection attenuation device includes at least one pair of electrical semiconductor components connected in parallel, and at least one capacitor that is connected in series to the pair of electrical semiconductor components connected in parallel, for attenuating reflections on a bus line of the bus. | 2021-12-30 |
20210409004 | LOW POWER BIQUAD SYSTEMS AND METHODS - Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption. | 2021-12-30 |
20210409005 | CHIP, SIGNAL LEVEL SHIFTER CIRCUIT, AND ELECTRONIC DEVICE - This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip. | 2021-12-30 |
20210409006 | Waveform Generator - The waveform generator ( | 2021-12-30 |
20210409007 | Frequency Doubler with Duty Cycle Correction - An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell. | 2021-12-30 |
20210409008 | Gated Ring Oscillator with Constant Dynamic Power Consumption - A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1. | 2021-12-30 |
20210409009 | HIGH-SPEED FLIP FLOP CIRCUIT INCLUDING DELAY CIRCUIT - A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level. | 2021-12-30 |
20210409010 | LEVEL SHIFTER - In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source. | 2021-12-30 |
20210409011 | SPREAD SPECTRUM CLOCK GENERATION DEVICE AND METHOD FOR OPERATING SPREAD SPECTRUM CLOCK GENERATION DEVICE - A device includes a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal, and an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output signal, wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and wherein a cycle of the output clock signal is longer than or equal to a cycle of the reference clock signal. | 2021-12-30 |
20210409012 | SENSOR OUTPUT CIRCUIT - A sensor output circuit is limited with high accuracy, and reduces radio wave radiation by signal transmission using a single-line signal. The sensor output includes a pulse signal Vin that changes according to a physical quantity to be measured, MOS transistors that perform on/off operations according to the pulse signal Vin, a constant current source that generates a constant current, a MOS transistor which generates a gate voltage of a MOS transistor, MOS transistors which form a current mirror circuit, and the MOS transistor which works to maintain a drain voltage of the MOS transistor at a constant voltage, and the output terminal which is driven by the MOS transistors connected in series. In addition, an output signal from the sensor output circuit is transmitted to a control circuit via an output signal line. The control circuit includes a pull-up resistor, a capacitor, and an input gate circuit. | 2021-12-30 |
20210409013 | COMMUNICATION SYSTEM - A communication system includes a transmission line and a reception coupler that couples to the transmission line in an electromagnetic field and moves along the transmission line, wherein the reception coupler has end parts narrower than other parts with respect to a transmission direction of the transmission line. | 2021-12-30 |
20210409014 | SELF-REFERENCED CLOCKLESS DELAY ADAPTATION FOR RANDOM DATA - A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate. | 2021-12-30 |
20210409015 | BOOTSTRAPPED SWITCH CIRCUIT, A TRACK-AND-HOLD CIRCUIT, AN ANALOG-TO-DIGITAL CONVERTER, A METHOD FOR OPERATING A TRACK-AND-HOLD CIRCUIT, A BASE STATION AND A MOBILE DEVICE - The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor. | 2021-12-30 |
20210409016 | POWER SWITCH SHORT CIRCUIT PROTECTION - Systems, methods, techniques and apparatuses of power switch protection are disclosed. One exemplary embodiment is a protection system for a power switch comprising a resistor and a detection circuit. The resistor is coupled in series with a decoupling capacitor. The detection circuit is structured to receive a voltage of the resistor, determine a short circuit is occurring based on the received electrical characteristic, and transmit a fault trigger signal in response to determining the short circuit is occurring. | 2021-12-30 |
20210409017 | LOCAL INTERCONNECT NETWORK (LIN) DRIVER CIRCUIT - A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node. | 2021-12-30 |
20210409018 | Fast Active Clamp for Power Converters - A switching system can include a main switching device configured to switch a voltage, a gate driver having an output coupled to a drive terminal of the main switching device and configured to deliver a drive signal to the main switching device, and a clamp circuit. The clamp circuit can be coupled to the drive terminal of the main switching device. The clamp circuit can include a logic gate configured to drive a clamp switching device coupled to and configured to clamp a voltage at the drive terminal of the main switching device. A drive signal of the clamp switching device can be substantially complementary to the main switching device drive signal. The logic gate can provide at least a portion of a delay between switching transitions of the main switching device and switching transitions of the clamp switching device. | 2021-12-30 |
20210409019 | OUTPUT DRIVING CIRCUIT - An output driving circuit may include a pull-up-pull-down driver connected to a pad, a level shifter operating based on a first power voltage and a second power voltage that is greater than the first power voltage, level shifting a data signal to generate a first control signal, and applying the first control signal to the pull-up-pull-down driver, and a driver control logic operating based on the first power voltage, generating a second control signal based on the data signal, and applying the second control signal to the pull-up-pull-down driver. | 2021-12-30 |
20210409020 | HIGH VOLTAGE OUTPUT CIRCUIT WITH LOW VOLTAGE DEVICES USING DATA DEPENDENT DYNAMIC BIASING - A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices. | 2021-12-30 |
20210409021 | APPROACH TO MEASURE THIN FILM LAYERS, NANOMETER SCALE, ON SURFACES THROUGH NON-CONTACT CAPACITIVE PROXIMITY SENSOR - An ultra-high resolution capacitive sensor affixed above an imaging member surface measures the thickness of fountain solution on the imaging member surface in real-time during a printing operation. The sensor is considered ultra-high resolution with a resolution high enough to detect nanometer scale thicknesses. The capacitive sensor would initially be zeroed to the imaging member surface. As fluid is added, the capacitive sensor detects the increase and can measure and communicate with the image forming device to adjust fountain solution flow rate to the imaging member surface and correct for any anomalies in thickness. This fountain solution monitoring system may be fully automated. The capacitive sensor may have a resolution (e.g., as low as about 1 nm resolution) of about 0.001% of the distance/gap that the capacitive sensor is mounted away from the imaging member surface. | 2021-12-30 |
20210409022 | LIVING BODY DETECTION METHOD AND APPARATUS - Methods and apparatus for detecting possible living body contact at an electrical contact surface is disclosed, comprising sending a non-hazardous probing signal to the contact surface, detecting an electrical response from the contact surface in response to the electrical probing signal, and determining whether a captured responsive signal has characteristics of an expected responsive pulse, and to output a positive output signal indicative of possible living body to mitigate risks of electrical shock. | 2021-12-30 |
20210409023 | SEMICONDUCTOR DEVICE - A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter. | 2021-12-30 |
20210409024 | RECOGNIZING TRANSISTOR-TRANSISTOR LOGIC LEVELS (TTL) AT AN INPUT CIRCUIT WITH INCREASED IMMUNITY TO STATIC CURRENT DRAW - An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low. A third inverter may be maintained utilizing an input signal voltage to detect a falling edge of the input signal and turn ON power supply to the first inverter at least partially responsive thereto. | 2021-12-30 |
20210409025 | DUAL-EDGE AWARE CLOCK DIVIDER - A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided. | 2021-12-30 |
20210409026 | CIRCUIT FOR ELIMINATING CLOCK JITTER BASED ON RECONFIGURABLE MULTI-PHASE-LOCKED LOOPS - A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer. | 2021-12-30 |
20210409027 | CLOCK GENERATOR - A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal. | 2021-12-30 |
20210409028 | MONITOR CIRCUITRY FOR POWER MANAGEMENT AND TRANSISTOR AGING TRACKING - Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node. | 2021-12-30 |
20210409029 | Calibration of Sampling-Based Multiplying Delay-Locked Loop (MDLL) - An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler. | 2021-12-30 |
20210409030 | PROCESS FOR MANAGING THE START-UP OF A PHASE-LOCKED LOOP, AND CORRESPONDING INTEGRATED CIRCUIT - A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation. | 2021-12-30 |
20210409031 | METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OSCILLATOR - A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment. | 2021-12-30 |
20210409032 | TIMING SKEW MISMATCH CALIBRATION FOR TIME INTERLEAVED ANALOG TO DIGITAL CONVERTERS - A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time. | 2021-12-30 |
20210409033 | ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage. | 2021-12-30 |
20210409034 | METHOD FOR FAST DETECTION AND AUTOMATIC GAIN ADJUSTMENT IN ADC BASED SIGNAL - A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed. | 2021-12-30 |
20210409035 | Analog-to-digital converter - An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs. | 2021-12-30 |
20210409036 | Sigma-Delta Analog-to-Digital Converter and Sensor Arrangements Including the Same - In an embodiment, an ADC converter includes a first injection branch and a second injection branch, a first feedback branch and a second feedback branch, an integration node connected to the first and second injection branches and the first and second feedback branches, an integrator connected to the integration node and a comparator connected downstream of the integrator and configured to generate a comparator output signal to control the first and second feedback branches, wherein the first and second injection branches are configured to provide a charge injection dependent on a respective input quantity to the integration node, wherein the input quantity of the first injection branch is selected from a differential voltage signal, a capacitance dependent signal and a current dependent signal, wherein the input quantity of the second injection branch is selected from another one of the differential voltage signal, the capacitance dependent signal and the current dependent signal, and wherein the first and second feedback branches are configured to provide a feedback charge injection dependent on the comparator output signal to the integration node, the first and second feedback branches configured to receive one of a fixed voltage signal or a differential voltage signal. | 2021-12-30 |
20210409037 | ADDITIONAL COMPRESSION FOR EXISTING COMPRESSED DATA - Techniques are provided for implementing additional compression for existing compressed data. Format information stored within a data block is evaluated to determine whether the data block is compressed or uncompressed. In response to the data block being compressed according to a first compression format, the data block is decompressed using the format information. The data block is compressed with one or more other data blocks to create compressed data having a second compression format different than the first compression format. | 2021-12-30 |
20210409038 | OPTIMIZATIONS FOR VARIABLE SECTOR SIZE IN STORAGE DEVICE NAMESPACES - A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability. | 2021-12-30 |
20210409039 | DATA PROCESSING METHOD AND DEVICE - Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K. | 2021-12-30 |
20210409040 | T-SWITCH WITH SHUNT FOR IMPROVED RECEIVER SENSITIVITY - Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a t-switch with gate shunting. One aspect is an apparatus including a first differential switch having a control input. The apparatus further includes a second differential switch coupled to the first differential switch, the second differential switch a control input. A shunt capacitor is coupled between a first output and a second output of the first differential switch, and a first input and a second input of the second differential switch. A first shunt switch having a control input, an input, and an output has the input and the output coupled to the control input of the first differential switch. A second shunt switch having a control input, an input, and an output, has the input and the output coupled to the control input of the second differential switch. | 2021-12-30 |
20210409041 | PROGRAMMABLE BASEBAND FILTER FOR SELECTING BETWEEN SINGLE-POLE OR COMPLEX-POLES FREQUENCY RESPONSE - An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles. | 2021-12-30 |
20210409042 | MULTIPLEXER, FRONT END MODULE, AND COMMUNICATION DEVICE - A multiplexer includes a common terminal, reception output terminals ( | 2021-12-30 |
20210409043 | Electronic Device - The present disclosure provides an electronic device. The electronic device includes a body and a display screen. The display screen is fixed to the body. A back of the body includes a spacing area not covered by the display screen, the spacing area including a conductor layer. The electronic device further includes an antenna of the electronic device disposed in the spacing area to emit or receive radio frequency signals. The antenna includes the conductor layer. | 2021-12-30 |
20210409044 | Radio Frequency Switching Circuit With Hot-Switching Immunity - Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states. | 2021-12-30 |
20210409045 | COMMUNICATION SYSTEM AND METHOD FOR EQUIPMENT IN AIRBORNE OPERATIONS - A communication system for equipment in airborne operations comprising: at least one first double transceiver and at least one second double transceiver, wherein the at least one first double transceiver is configured to send data to the at least one second double transceiver in two redundant main channels and wherein the data to be sent through each redundant main channel is first compared with each other so as to ensure that the data sent through a first main channel is the same data sent through a second main channel. | 2021-12-30 |
20210409046 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes a mounting board having first and second major surfaces opposite to each other and a duplexer including a transmit filter coupled to a node and a receive filter coupled to the node. The transmit filter is mounted on the first major surface, and the receive filter is mounted on the second major surface. When the mounting board is viewed in a plan view, a footprint of the transmit filter at least partially overlaps a footprint of the receive filter. | 2021-12-30 |
20210409047 | TUNABLE FILTER WITH HARMONIC REJECTION - Aspects of this disclosure relate to a tunable filter with harmonic rejection. The tunable filter includes mutually coupled inductors and a tunable capacitance circuit electrically connected to at least one of the mutually coupled inductors. The tunable capacitance circuit includes N switches configured to adjust effective capacitance of the tunable capacitance circuit to tune harmonic rejection of the tunable filter for at least 2×2 | 2021-12-30 |
20210409048 | WIRELESS RECEIVER APPARATUS AND METHOD - Embodiments of the invention include a wakeup receiver (WRX) featuring a charge-domain analog front end (AFE) with parallel radio frequency (RF) rectifier, charge-transfer summation amplifier (CTSA), and successive approximation analog-to-digital converter (SAR ADC) stages. The WRX operates at very low power and exhibits above-average sensitivity, random pulsed interferer rejections, and yield over process. | 2021-12-30 |
20210409049 | INTEGRATED FREQUENCY SELECTIVE LIMITER UTILIZING QUADRATIC AND AN-HARMONIC ENERGY SCATTERING - An adaptive filter includes, in part, a linear filter, and a non-linear resonator coupled to the linear filter and adapted to resonate at a frequency that is an integer multiple of the frequency of a received RF signal. The adaptive filter filters out the received RF signal. The resonant frequency may be twice the frequency of the received RF signal. The adaptive filter optionally includes a second non-linear resonator coupled to the linear filter and adapted to resonate at a frequency defined by a sum of the integer multiple of the frequency of the received signal and an offset frequency. | 2021-12-30 |
20210409050 | REDUCING UPLINK ACCUMULATED NOISE FLOOR IN A DISTRIBUTED COMMUNICATIONS SYSTEM (DCS - Reducing an uplink accumulated noise floor in a distributed communications system (DCS) is disclosed. The DCS includes a number of remote units that communicate a number of uplink digital communications signals to a base station concurrently. In DCSs disclosed in certain aspects herein, a signal source, such as a digital baseband unit (BBU) for example, includes multiple receiver circuits each configured to receive and decode a respective one of the uplink digital communications signals. By individually receiving and decoding the uplink digital communications signals before combining the uplink digital communications signals, each of the receiver circuits can operate with a lowered noise floor. As a result, it is possible to improve received sensitivity of the receiver circuits, thus helping to improve coverage range, spectrum efficiency, and data throughput of the DCS. | 2021-12-30 |
20210409051 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module is able to simultaneously communicate a signal of a first communication band and a signal of a second communication band and does not simultaneously communicate a signal of the first communication band and a signal of a third communication band. The radio-frequency module includes a mounting substrate, a filter, a filter, and a filter. The filter is provided on the mounting substrate and has the first communication band as the pass band thereof. The filter is provided on the mounting substrate and has the second communication band as the pass band thereof. The filter is provided on the mounting substrate and has the third communication band as the pass band thereof. The filter and the filter are indirectly stacked on top of each other and the filter and the filter are not stacked on top of each other. | 2021-12-30 |
20210409052 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes an integrated circuit (IC) device and an external inductor provided outside the IC device. The IC device includes a plurality of low-noise amplifiers, one or more inductors, and a switching circuit. The plurality of low-noise amplifiers includes a plurality of transistors in one to one correspondence. The one or more inductors are coupled to one or more of the plurality of transistors. Each inductor is coupled to the emitter or source of a corresponding one of the plurality of transistors. The switching circuit is coupled between the emitter or source of each of the plurality of transistors and the external inductor. The external inductor is coupled between the switching circuit and ground in series with each of the one or more inductors via the switching circuit. | 2021-12-30 |
20210409053 | Unique Word and Burst Header Detection for an Expanded Frequency Range - Various data transmission detection systems are described. A receiver input through which a wireless data transmission signal is received may be present. A plurality of mixers in communication with the receiver input may be present, which may be digitally implemented. A data transmission detector may be present that receives a mixed wireless data transmission signal from each mixer and creates a plurality of scores. A match detection module may be present that receives the scores and identifies a highest score. The signal mapped to the highest score to be selected for further processing. | 2021-12-30 |
20210409054 | METHOD OF DEMODULATION OF A STEREOPHONIC SIGNAL - A method for demodulating a multiplexed stereophonic signal, the signal including a signal called the sum signal, a signal called the difference signal, and a pilot signal, the method including the following steps: removing the pilot frequency from the multiplexed stereophonic signal, the resulting signal being called the pilotless signal, and subtracting the sum signal from the pilotless signal. | 2021-12-30 |
20210409055 | CONFIGURABLE WIDEBAND SPLIT LNA - Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations. | 2021-12-30 |
20210409056 | METHOD AND APPARATUS FOR MITIGATING IMAGE INTERFERENCE IN A RECEIVER - An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal. | 2021-12-30 |
20210409057 | RING ATTACHMENT FOR MOBILE DEVICE - A ring attachment for a mobile device assembly wherein the mobile device assembly further includes a mobile device and a mobile device case. The mobile device case has sidewalls defining an inner cavity sized to receive the mobile device therein. The ring attachment includes an anchor having a height, width and thickness. The height and the width are sized to fit within the inner cavity. The thickness is sized to fit between the inner cavity of the mobile device case and a back surface of the mobile device when the mobile device is secured within the inner cavity. A ring is secured to the anchor. The ring is sized to receive a finger of a user. The ring is comprised of a resilient material such that inner surfaces of the ring may be compressed together when squeezed and the ring may return to an original shape when released. | 2021-12-30 |
20210409058 | ANTIMICROBIAL PHONE CASE - A cover for a device that can provide antimicrobial protection is provided. The cover includes a case for enveloping an external device, an antimicrobial plate coupled to the case, and one or more protrusions provided on the antimicrobial plate for creating a physical separation between the antimicrobial plate and an external surface. The antimicrobial plate can be made of copper or a copper alloy that exhibit antimicrobial properties. Moreover, one or more magnets can be provided on the underside of the case to removably attach the case onto the external device. In certain embodiments, the case can be omitted and the antimicrobial plate can be directly coupled to the external device. | 2021-12-30 |
20210409059 | Cover Plate, Display Screen, and Electronic Device - A cover plate, a display screen, and an electronic device are provided. The cover plate includes a flat portion and a curved portion connected with the flat portion. A flat portion has a flat front surface and a first side surface. The flat front surface has a first sideline and a second sideline connected with the first sideline. The curved portion is arranged around a periphery of the flat portion and has a curved surface and a second side surface. The curved surface is connected between the flat front surface and the second side surface. The first sideline serves as a boundary line between the curved surface and the flat front surface. The second sideline serves as a boundary line between the flat front surface and the first side surface. The first side surface is in the same direction as the second side surface. | 2021-12-30 |
20210409060 | MULTI-RAT DYNAMIC TRANSMIT POWER BOOST USING AN ANTENNA FRONT END MODULE - An antenna front-end module, method, and information handling system are adapted to the application of a direct-current (DC) bias voltage in relation to an antenna and detect a connection status of the antenna based on a sensed DC voltage. When the connection status corresponds to the antenna being connected, a first transmit power level is configured. When the connection status corresponds to the antenna being disconnected, a second transmit power level is configured. A transmit power boost can be provided such that the first transmit power level is greater than the second transmit power level. The first transmit power level can correspond to a radiative transmission mode, and the second transmit power level can correspond to a conductive transmission mode. | 2021-12-30 |
20210409061 | FORWARD ERROR CORRECTION - The Forward Error Correction (FEC) technique completely estimates the total path length, time delays, as well as amplitude values and variations for the full path between the RF exciters and antennas, in an RF Phased Array System. These paths are normally unknown and therefore difficult to calibrate. The technique also corrects for phase and amplitude differences and variations in non-equal length RF cables, thus removing the requirement for phase matched cables in the array system. | 2021-12-30 |
20210409062 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes a module substrate, a power amplifier, and a control circuit configured to control the power amplifier. The control circuit includes a temperature sensor. The power amplifier and the control circuit are stacked one on top of another on a principal surface of the module substrate. | 2021-12-30 |
20210409063 | DUPLEXER WITH BALANCED IMPEDANCE LADDER - An electrical balance duplexer has multiple impedance gradients and multiple impedance tuners. The electrical balance duplexer transmits an outgoing signal from a transmitter during a transmission mode when a first set of impedance gradients of the multiple impedance gradients is operating in a first impedance state and a first set of impedance tuners of the multiple impedance tuners is operating in a second state. The electrical balance duplexer isolates the outgoing signal from a receiver during the transmission mode when a second set of impedance gradients of the multiple impedance gradients and a second set of impedance tuners of the multiple impedance tuners are operating in the second impedance state. | 2021-12-30 |
20210409064 | RADIO FREQUENCY ARCHITECTURE FOR REDUCING MUTUAL INTERFERENCE BETWEEN MULTIPLE WIRELESS COMMUNICATION MODALITIES - Radio frequency architecture for reducing mutual interference between multiple wireless communication modalities. One embodiment provides a portable communications device including a housing and an RF antenna system including a first RF antenna, a second RF antenna, and a third RF antenna in the housing. The portable communications device includes an RF transceiver system including a first RF transceiver, a second RF transceiver, and a third RF transceiver operating in respective bands and an isolator circuit coupled to the RF antenna system and the RF transceiver system and configured to provide RF isolation between the first RF transceiver, the second RF transceiver, and the third RF transceiver. The isolator circuit includes an RF coupler featuring six RF coupler ports coupled to the first RF antenna, the second RF antenna, the third RF antenna, the first RF transceiver, the second RF transceiver, and the third RF transceiver through respective phasor shaping networks. | 2021-12-30 |
20210409065 | TRANSFORMER, TRANSMITTER CIRCUIT, SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE, BASE STATION, MOBILE DEVICE, AND METHOD FOR A RADIO FREQUENCY TRANSMITTER - The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal. | 2021-12-30 |
20210409066 | WIDE AREA POSITIONING SYSTEM - Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals. | 2021-12-30 |
20210409067 | OCCUPANCY SENSING USING ULTRA-WIDE BAND - Occupancy sensing using ultra-wideband (UWB) keyless infrastructure is provided. Channel impulse response (CIR) measurements are received from a plurality of UWB transceiver nodes arranged about a plurality of locations. A classification model it utilized to predict occupancy of each of the plurality of locations based on CIR tensors formed from the CIR measurements for each of the UWB transceiver nodes. | 2021-12-30 |
20210409068 | SIGNAL POWER REDUCTION SYSTEMS AND METHODS - A method of reducing transmission power for an encoded data stream includes the steps of receiving an incoming data stream having equal probability for a plurality of incoming data bits, assigning a symbol scheme to the received data bits of the incoming data stream according to probabilities of occurrence of individual ones of the received data bits, and transmitting an outgoing data stream according to the assigned symbol scheme having a second average transmit power, different than the first average transmit power, for a plurality of outgoing symbols. | 2021-12-30 |
20210409069 | POWER LINE COMMUNICATION DEVICE - The power line communication device detects inverter noise from the voltage waveforms of the power line, and executes the output of the transmission signal in a period in which it is determined that the signal amplitude of the transmission signal in the transmission processing unit exceeds a predetermined value from the output amplitude of the inverter noise, and stops the output of the transmission signal in other periods. | 2021-12-30 |
20210409070 | SIGNAL MULTIPLEXER FOR SONAR - A sonar includes a first part and a second part linked by an electric carrier cable configured to mechanically support the second part and allow the two parts of the sonar to exchange signals comprising: a unidirectional signal, called electrical power supply signal, unidirectional signals, called signals to be emitted, transmitted by the first part to the second part for them to be transmitted in the form of acoustic waves, and a bidirectional signal conveying communication data, the sonar wherein the first part comprises signal combination means configured for the signals to be transmitted simultaneously over the electric carrier cable, and in that the second part comprises separation means allowing the recovery of each of the signals transmitted over the electric carrier cable. | 2021-12-30 |
20210409071 | SCREEN TRANSMISSION METHOD, VEHICLE MOUNT, AND STORAGE MEDIUM - A screen delivery method, a vehicle bracket and a storage medium are provided. In the method, at least one mobile terminal around the vehicle bracket is detected; a target mobile terminal is determined from the at least one mobile terminal based on a change in intensity of a magnetic field between the at least one mobile terminal and the vehicle bracket; and screen delivery is performed between the vehicle bracket and the target mobile terminal based on a communicational connection between the vehicle bracket and the target mobile terminal in a case that it is determined that the target mobile terminal is fixed on the vehicle bracket. Therefore, with the method, the user's different application requirements for the vehicle bracket are met, and the user experience is improved. | 2021-12-30 |
20210409072 | WIRELESS COMMUNICATION APPARATUS AND METHOD - A wireless communication apparatus may include: an oscillator including a coil assembly exposed to an outside of the wireless communication apparatus, a variable capacitor, and a negative resistor; and a phase locking circuit connected to the coil assembly and the negative resistor. The phase locking circuit may be configured to generate a control signal to lock an oscillation frequency of the oscillator based on an oscillation signal generated by the oscillator, and provide the generated control signal to the variable capacitor. | 2021-12-30 |
20210409073 | Communication Between Devices During Wireless Power Transfer - A wireless power system has a wireless power transmitting device and a wireless power receiving device. The devices in the wireless power system may communicate using in-band communication. The wireless power transmitting device may transmit data to the wireless power receiving device using frequency-shift keying (FSK) modulation. The wireless power receiving device may transmit data to the wireless power transmitting device using amplitude-shift keying (ASK) modulation. While transmitting data to the wireless power receiving device using FSK modulation, the wireless power transmitting device may monitor for ASK modulation from the wireless power receiving device. In response to detecting the ASK modulation from the wireless power receiving device, the wireless power transmitting device may abort the FSK data transmission and process the detected ASK modulation to receive data from the wireless power receiving device. | 2021-12-30 |
20210409074 | FAST NFC PROCESSING - In an embodiment, an NFC controller of an NFC device is configured to transmit, after the detection, by the NFC controller, of an NFC reader in relation with a first NFC transaction and prior to receiving an application selection command from the NFC reader, an application selection message to a transaction handling element of the NFC device. | 2021-12-30 |