| 52nd week of 2021 patent applcation highlights part 75 |
| Patent application number | Title | Published |
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| 20210408275 | SOURCE OR DRAIN STRUCTURES WITH HIGH SURFACE GERMANIUM CONCENTRATION - Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures. | 2021-12-30 |
| 20210408276 | Semiconductor Device and Method - A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support. | 2021-12-30 |
| 20210408277 | Transistor Device Structure - A transistor device comprising a core device and an input/output device, a field oxide layer isolates an active region of a core device region from an active region of an input/output device region on a semiconductor substrate, a gate-all-around structure is formed in the active region of the core device region, and a fin gate structure is formed in the active region of the input/output device region, thereby improving the short channel effect of the core device. In addition, the thickness of a gate dielectric layer of the fin gate structure of the input/output device is not affected by a gap between channel wires of the gate-all-around structure, such that the on-current and off-current performance of the input/output device is not affected when the short channel effect of the core device is improved. | 2021-12-30 |
| 20210408278 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active portion and a gate pad portion; a first semiconductor layer of the first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has first semiconductor regions of the first conductivity type, first trenches, gate insulating films, first gate electrodes, an interlayer insulating film, and second semiconductor regions of the second conductivity type. The gate pad portion has at least one second trench, an insulating film 9 | 2021-12-30 |
| 20210408279 | SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE STRUCTURE AND BURIED SHIELDING REGION AND METHOD OF MANUFACTURING - In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface. | 2021-12-30 |
| 20210408280 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins. | 2021-12-30 |
| 20210408281 | CURRENT REFERENCE - In an example, an integrated circuit includes a junction-gate field effect transistor (JFET), a current generator, a dynamic filter, and an output transistor. The JFET has a JFET gate, a JFET source, and a JFET drain, the JFET drain adapted to be coupled to a power supply. The current generator has a current generator input and current generator outputs, the current generator input coupled to the JFET source and a first of the current generator outputs coupled to the JFET gate. The dynamic filter has a dynamic filter input and a dynamic filter output, the dynamic filter input coupled to a second of the current generator outputs. The output transistor has an output transistor gate coupled to the dynamic filter output. | 2021-12-30 |
| 20210408282 | FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYER AND HAVING A GATE STRESSOR LAYER - Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side. | 2021-12-30 |
| 20210408283 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON INSULATOR - Gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is on the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. Each of the pair of epitaxial source or drain structures has a compressed or an expanded lattice. | 2021-12-30 |
| 20210408284 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON GATE DIELECTRIC LAYER - Gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires. The gate stack includes a high-k dielectric layer continuous with and having a same composition as the insulator layer. | 2021-12-30 |
| 20210408285 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GERMANIUM-DOPED NANORIBBON CHANNEL STRUCTURES - Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire. | 2021-12-30 |
| 20210408286 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer. | 2021-12-30 |
| 20210408287 | Method for Inducing Stress in Semiconductor Devices - Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area. | 2021-12-30 |
| 20210408288 | TMD INVERTED NANOWIRE INTEGRATION - Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell. | 2021-12-30 |
| 20210408289 | NANOWIRE TRANSISTORS AND METHODS OF FABRICATION - A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant. | 2021-12-30 |
| 20210408290 | THIN FILM TRANSISTOR AND VERTICAL NON-VOLATILE MEMORY DEVICE INCLUDING METAL OXIDE CHANNEL LAYER HAVING BIXBYITE CRYSTAL - A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively. | 2021-12-30 |
| 20210408291 | PASSIVATION LAYERS FOR THIN FILM TRANSISTORS AND METHODS OF FABRICATION - A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition. | 2021-12-30 |
| 20210408292 | THIN-FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME - A thin-film transistor substrate includes: an active layer on a substrate, the active layer including: a first semiconductor material layer; a conductor layer on the first semiconductor material layer, and including a metal element; and a second semiconductor material layer on the conductor layer; a gate insulating layer on the active layer; and a gate electrode on the gate insulating layer, and at least partially overlapping with the active layer. | 2021-12-30 |
| 20210408293 | OXIDE SEMICONDUCTOR TRANSISTOR STRUCTURE IN 3-D DEVICE AND METHODS OF FORMING THE SAME - A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration. | 2021-12-30 |
| 20210408294 | Elevationally-Extending Transistors, Devices Comprising Elevationally-Extending Transistors, And Methods Of Forming A Device Comprising Elevationally-Extending Transistors - A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed. | 2021-12-30 |
| 20210408295 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. In the array substrate, a functional layer disposed between an active layer and a gate insulating layer protects the active layer during etching of the active layer, which prevents the active layer from damage and conducts a source/drain layer and the active layer, so that transistors in the array substrate work normally, solving the technical problem that current display panels damage the active layer during a preparation process, which causes performance of thin film transistors to decrease. | 2021-12-30 |
| 20210408296 | TRANSITION METAL DICHALCOGENIDE TRANSISTOR AND PREPARATION METHOD THEREOF - A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties. The present invention provides a transition metal dichalcogenide transistor and a preparation method thereof, which can solve a problem of excessive contact resistance between a transition metal dichalcogenide transistor channel and a source/drain region and can make the transition metal dichalcogenide transistor compatible with the existing CMOS process. | 2021-12-30 |
| 20210408297 | TRANSISTORS COMPRISING TWO-DIMENSIONAL MATERIALS AND RELATED MEMORY CELLS AND SEMICONDUCTOR DEVICES - A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device. | 2021-12-30 |
| 20210408298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with high reliability is provided. A first conductor and a second conductor are provided over and in contact with a first oxide. A first insulator is provided to cover the first oxide, a first conductor, and a second conductor. The first insulator includes an opening portion. The first oxide is exposed on a bottom surface of the opening portion. A side surface of the first conductor and a side surface of the second conductor are exposed on a side surface of the opening portion. A second oxide is provided in contact with the first oxide, the side surface of the first conductor, and the second conductor in the opening portion. A second insulator is provided in the opening portion with the second oxide therebetween. A third conductor is provided in the opening portion with the second insulator therebetween. Lower end portions of the side surface of the first conductor and the second conductor touch an ellipse or a circle with a center above the first oxide. | 2021-12-30 |
| 20210408299 | MULTI-LAYER CRYSTALLINE BACK GATED THIN FILM TRANSISTOR - Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer. | 2021-12-30 |
| 20210408300 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion. | 2021-12-30 |
| 20210408301 | NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME - Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars. | 2021-12-30 |
| 20210408302 | Arrangement For an Optoelectronic Component, Manufacturing Process and Optoelectronic Component - An arrangement for an optoelectronic component includes a substrate and an optical semiconductor chip arranged on the substrate. The optical semiconductor chip has an optically active region, a first optically non-active region, and a second optically non-active region. A connection structure connects a chip-side electrical connection to the optically active region. An electrical connection connects the chip-side electrical connection to a second substrate-side electrical connection. A coating is provided in a layer stack in the optically active region, in the first optically non-active region, and in the second optically non-active region. The layer stack includes a first layer and a second layer arranged above the first layer. The chip-side electrical connection and the connection structure in the first optically non-active region and the protective layer in the second optically non-active region are each arranged between the first layer and the second layer. | 2021-12-30 |
| 20210408303 | SEMICONDUCTOR LIGHT-RECEIVING ELEMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT-RECEIVING ELEMENT - A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode. | 2021-12-30 |
| 20210408304 | THIN-FILM PHOTOVOLTAIC CELL WITH HIGH PHOTOELECTRIC CONVERSION RATE AND PREPARATION PROCESS THEREOF - The present disclosure provides a thin-film photovoltaic cell with a high photoelectric conversion rate and a preparation process thereof. The thin-film photovoltaic cell comprises a transparent substrate and photovoltaic units which are disposed on the transparent substrate and arranged toward the display module, and the photovoltaic unit disposed in the display area comprises a transparent front electrode disposed on the transparent substrate, a light absorption layer disposed on the transparent front electrode and a transparent back electrode disposed on the light absorption layer; and the photovoltaic unit disposed in the non-display area comprises a transparent front electrode disposed on the transparent substrate, a light absorption layer disposed on the transparent front electrode and a metal back electrode disposed on the light absorption layer. | 2021-12-30 |
| 20210408305 | INORGANIC COMPOUND SEMICONDUCTOR, METHOD FOR MANUFACTURING SAME, AND LIGHT ENERGY CONVERSION ELEMENT USING SAME - An inorganic compound semiconductor of the present disclosure contains yttrium, zinc, and nitrogen. | 2021-12-30 |
| 20210408306 | SUPERLATTICE PHOTO DETECTOR - A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer. | 2021-12-30 |
| 20210408307 | METHOD FOR PRODUCING MOSAIC SOLAR CELL ASSEMBLIES - A method for producing a mosaic solar cell assembly, comprising the steps of singulating a III-V compound semiconductor solar cell wafer into four identical discrete solar cell mosaic elements each substantially shaped as a quadrant of a circle, comprising a first and second solar cell mosaic element having one curved edge in the shape of an arc of the circumference of the circular wafer from which the element was singulated, and a single straight edge, rearranging and positioning two of the mosaic elements into a substantially rectangular mosaic assembly; providing a metal interconnect between each of the mosaic elements along one edge of the assembly so that the mosaic elements may be electrically connected to an adjacent mosaic assembly; and optionally bonding the cover glass support to the top of the mosaic assembly. | 2021-12-30 |
| 20210408308 | DEVICE FOR PHOTO SPECTROSCOPY HAVING AN ATOMIC-SCALE BILAYER - Aspects of the subject disclosure may include, for example, a photo detecting device that includes a bottom gate, a bilayer semiconductor formed on the bottom gate, and a top gate above the bilayer semiconductor comprising a polymer electrolyte. Other embodiments are disclosed. | 2021-12-30 |
| 20210408309 | COMPOSITE ENCAPSULATING MATERIAL AND PHOTOVOLTAIC MODULE INCLUDING THE SAME - Provided is a composite encapsulating material and a photovoltaic module encapsulated with the composite encapsulating material, which relate to the technical field of photovoltaic modules. At least a partial area of the composite encapsulating material includes a high insulation material, and the high insulation material includes polyimide, modifier and modified polyimide. The above technical solution can improve an insulation performance of the encapsulating material, reduce a blank area of an edge of the module, reduce a weight of the photovoltaic module, and further reduce comprehensive cost of the photovoltaic module. | 2021-12-30 |
| 20210408310 | SEMICONDUCTOR PHOTO-DETECTING DEVICE - A photo-detecting device includes a substrate, a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, a semiconductor contact layer, an insulating layer, and an electrode structure. The second semiconductor layer includes a first region and a second region. The semiconductor contact layer is on the first region. The insulating layer covers the semiconductor contact layer, the first region, and the second region. The electrode structure covers the semiconductor contact layer, the insulating layer, the first region, and the second region. | 2021-12-30 |
| 20210408311 | SEMICONDUCTOR PHOTO-DETECTING DEVICE - A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 Å and smaller than 1000 Å. | 2021-12-30 |
| 20210408312 | PHOTOVOLTAIC MODULE, SOLAR CELL AND METHOD FOR MANUFACTURING THEREOF - Provided is a solar cell, a shingled photovoltaic module, and a method for manufacturing solar cell, the solar cell includes a body portion, a first extending portion and a second extending portion provided at two ends of the body portion; a thickness of the body portion is greater than a thickness of the first extending portion and a thickness of the second extending portion. In the shingled photovoltaic module, adjacent solar cells can be electrically connected through the first extending portion and the second extending portion, and the adjacent solar cells do not need to be stacked in a thickness direction to achieve electrical connection, so that space in the thickness direction occupied by the stacked solar cells is reduced, and light-receiving area of the solar cell is not decreased, thereby improving photoelectric conversion efficiency of the solar cell, reducing the number of solar cells required, and saving cost. | 2021-12-30 |
| 20210408313 | STRINGS OF SOLAR CELLS HAVING LASER ASSISTED METALLIZATION CONDUCTIVE CONTACT STRUCTURES AND THEIR METHODS OF MANUFACTURE - Strings of solar cells having laser assisted metallization conductive contact structures, and their methods of manufacture, are described. For example, a solar cell string includes a first solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a first metal foil to the back side of the first solar cell. The solar cell string also includes a second solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a second metal foil to the back side of the second solar cell. The solar cell string also includes a conductive interconnect coupling the first and second solar cells, the conductive interconnect including a strain relief feature. | 2021-12-30 |
| 20210408314 | PHOTOVOLTAIC CELL ARRAY AND PHOTOVOLTAIC MODULE - A photovoltaic cell array and a photovoltaic module are provided. The photovoltaic cell array includes multiple solar cells and a flexible metal conductive strip. Each of an upper surface and a lower surface of each solar cell is arranged with a segment electrode. In adjacent two solar cells which are respectively referred to as a first solar cell and a second solar cell, the segment electrode on the lower surface of the first solar cell is connected with the segment electrode on the upper surface of the second solar cell by the flexible metal conductive strip. The photovoltaic cell array has a stack structure in a normal direction of the upper surface of the solar cell, and a connection region at which the segment electrode is connected with the flexible metal conductive strip is located outside an overlapped region of the stack structure. | 2021-12-30 |
| 20210408315 | SOLAR CELL, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND PHOTOVOLTAIC POWER GENERATION SYSTEM - A solar cell of an embodiment includes: a transparent substrate; a p-electrode on the substrate, the p-electrode including a first p-electrode containing an Sn-based metal oxide, a second p-electrode having an opening and consisting of a wiring containing a metal or graphene, and a third p-electrode containing an In-based metal oxide; a p-type light absorbing layer in direct contact with a surface of the first p-electrode on a side opposite to the second p-electrode side; an n-type layer provided on the p-type light absorbing layer; and an n-electrode provided on the n-type layer. The third p-electrode is provided to be present between the first p-electrode and the second p-electrode and to be in direct contact with an upper surface of the second p-electrode. An entire side surface of the second p-electrode is in direct contact with the first p-electrode. | 2021-12-30 |
| 20210408316 | SOLAR CELL SYSTEMS AND METHODS OF MAKING THE SAME - A solar cell system and a flexible solar panel are disclosed herein. The solar cell system includes a glass housing, a set of rows of solar cells each defining a front side and a rear side and arranged within the glass housing. The solar cell system can also include a reflective element disposed in the glass housing and facing the rear side of the set of rows of solar cells and a first terminal coupled to a first end of the set of rows of solar cells, traversing through and sealed against the first end of the glass housing. The solar cell system can be configured with other solar cell systems into the flexible solar panel that is deployable in a wide range of potential applications. | 2021-12-30 |
| 20210408317 | HARVESTABLE INDOOR ENERGY METER - An indoor light energy harvesting meter is described that includes a solar module including at least one photovoltaic cell to capture ambient light energy; and a circuit module coupled to the solar module. The circuit module may include a power management circuit configured to convert the ambient light energy captured by the solar module into electric energy; and a micro-controller configured to control the power management circuit and to receive the electric energy from the power management circuit to monitor an amount of indoor harvestable power. The micro-controller may monitor the amount of indoor harvestable power and generate parameters including one or more of an accumulated harvestable power, an instantaneous harvestable power, or a peak instantaneous harvestable power. The indoor light energy harvesting meter may include a display coupled to the micro-controller and configured to display one or more parameters associated with the amount of indoor harvestable power. | 2021-12-30 |
| 20210408318 | Space Charge Trap-Assisted Recombination Suppressing Layer for Low-Voltage Diode Operation - Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration n | 2021-12-30 |
| 20210408319 | AVALANCHE PHOTODETECTOR WITH DEEP-LEVEL-ASSISTED IMPACT IONIZATION - Avalanche photodetector devices and methods of use thereof are provided that incorporate deep levels to increase secondary carrier generation via impact ionization under application of a reverse bias. An avalanche photodetector device may include p+ and n+ regions, an intermediate semiconductor absorption region provided therebetween, and at least one semiconductor region residing between the p+ and n+ regions that incorporates deep levels. When light is incident on the device such that the absorption depth of the light extends into the intermediate semiconductor absorption region, a photocurrent is produced under a reverse bias includes both photocarriers generated within the intermediate semiconductor absorption region and secondary carriers released from the deep levels via impact ionization. The deep levels may facilitate an increased sensitivity, relative to a device absent of deep levels, via a deep-level ionization energy threshold that is less than a threshold for conventional impact ionization across a bandgap. | 2021-12-30 |
| 20210408320 | METAMORPHIC SOLAR CELLS - A multijunction solar cell including a metamorphic layer, and particularly the design and specification of the composition, lattice constant, and band gaps of various layers above the metamorphic layer in order to achieve reduction in “bowing” of the semiconductor wafer caused by the lattice mismatch of layers associated with the metamorphic layer. | 2021-12-30 |
| 20210408321 | POSITIONING MASK, SYSTEM AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE - A positioning mask includes a body delimiting conduits dimensioned to each accommodate a single functional electronic object and opening through a first opening on a cooperation face, and through a second opening on a reception face. | 2021-12-30 |
| 20210408322 | METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT - A method of manufacturing a light-emitting element includes: providing a semiconductor structure including: a first layer containing gallium and nitrogen, a second layer of a first conductive type, the second layer containing gallium, aluminum, and nitrogen and being located on or above the first layer, an active layer located on or above the second layer, and a third layer of a second conductive type, the third layer located on or above the active layer, wherein a thickness of the first layer is larger than a thickness of the second layer; performing chemical-mechanical polishing from a first layer side to reduce the thickness of the first layer; and performing dry etching from the first layer side to remove the first layer and reduce the thickness of the second layer. | 2021-12-30 |
| 20210408323 | MANUFACTURING PROCESS OF LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - This present disclosure provides a manufacturing process of light emitting device and a light emitting device. The manufacturing process of light emitting device includes: step S1, making a quantum dot film; step S2, providing a LED unit, the LED unit including at least one LED chip; step S3, disposing a first transparent adhesive layer on an exposed surface of each LED chip; step S4, disposing the quantum dot film on the surface of the first transparent adhesive layer far away from the LED chip. | 2021-12-30 |
| 20210408324 | ENHANCED ROOM TEMPERATURE MID-IR LEDS WITH INTEGRATED SEMICONDUCTOR 'METALS' - Mid-IR light emitting diodes (LEDs) based on type-II quantum dot (QD) active regions grown with monolithically integrated semiconductor metal layers are provided. These LEDs comprise layers of type-II semiconductor (e.g., InGaSb) quantum dots integrated into a pn junction diode (e.g., InAs) grown above a highly doped backplane, such as an n++ InAs backplane, all in the same epitaxial growth. Aspects described herein minimize non-radiate recombination times and significantly increase radiative recombination rates by controlling the emission of the emitting QDs in the near field of an optical metal. | 2021-12-30 |
| 20210408325 | PHOTORESIST CONTACT PATTERNING OF QUANTUM DOT FILMS - The present disclosure describes one or more embodiment of a method for creating a patterned quantum dot layer. The method includes bringing a patterning stamp in contact with a layer of quantum dots disposed on a substrate, the patterning stamp comprising a patterned photoresist layer disposed on an elastomer layer, such that a portion of the quantum dots in contact with the patterned photoresist layer adheres to the patterning stamp, the portion of the quantum dots being adhered quantum dots. The method also includes peeling the patterning stamp from the substrate with a peeling speed larger than a pre-determined peeling speed to remove the adhered quantum dots from the substrate. A remaining portion of the quantum dots forms a patterned quantum dot layer on the substrate. | 2021-12-30 |
| 20210408326 | LIGHT EMITTING APPARATUS, METHOD OF FABRICATING LIGHT EMITTING APPARATUS, AND METHOD OF EMITTING LIGHT USING LIGHT EMITTING APPARATUS THEREOF - A light emitting apparatus is provided. The light emitting apparatus includes a frame structure having a bottom side and a reflective lateral side connecting to the bottom side; and a first light emitting element and a second light emitting element on the bottom side of the frame structure. The first light emitting element is configured to emit a first light having a first wavelength range along a first direction. The second light emitting element is configured to emit a second light having a second wavelength range along a second direction. The first direction and the second direction are substantially opposite to each other. The reflective lateral side of the frame structure is configured to reflect the first light having the first wavelength range into a first reflected light and reflect the second light having the second wavelength range into a second reflected light. | 2021-12-30 |
| 20210408327 | SEMICONDUCTOR LIGHT EMITTING DEVICES - A semiconductor light emitting device is provided. The device includes a light emitting structure stack including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; and a field control structure on a sidewall of the light emitting structure stack, the field control structure including a field control electrode on a sidewall of the active layer; and a dielectric layer between the field control electrode and the active layer. | 2021-12-30 |
| 20210408328 | LED CHIPS WITH IRREGULAR MICROTEXTURED LIGHT EXTRACTION SURFACES, AND FABRICATION METHODS - LED chips and related fabrication methods are disclosed. A LED chip includes an active layer arranged on or over a light-transmissive substrate having a light extraction surface. The light extraction surface comprises a microtextured etched surface having a non-repeating, irregular textural pattern (e.g., with an average feature depth in a range of from 120 nm to 400 nm, and preferably free of any plurality of equally sized, shaped, and spaced textural features). The microtextured etched surface may be formed by applying a micromask having first and second solid materials of different etching rates over the light extraction surface, and exposing the micromask to an etchant (e.g., via reactive ion etching) to form a microtextured etched surface having a non-repeating, irregular textural pattern. Lumiphoric material may be applied over the microtextured surface. | 2021-12-30 |
| 20210408329 | INTEGRATION OF III-NITRIDE NANOWIRE ON TRANSPARENT CONDUCTIVE SUBSTRATES FOR OPTOELECTRONIC AND ELECTRONIC DEVICES - A dislocation-free GaN/InGaN-based nanowires-LED epitaxially grown on a transparent, electrically conductive template substrate. The simultaneous transparency and conductivity are provided by a thin, translucent metal contact integrated with a quartz substrate. The light transmission properties of the translucent metal contact are tunable during epitaxial growth of the nanowires LED. Transparent light emitting diodes (LED) devices, optical circuits, solar cells, touch screen displays, and integrated photonic circuits can be implemented using the current platform. | 2021-12-30 |
| 20210408330 | DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a display substrate and a method for manufacturing the same. The display substrate includes: a substrate; a first electrode located on the substrate; and a conductive convex located on the first electrode. A dimension of a cross section of the conductive convex along a plane parallel to the substrate is negatively correlated to a distance from the cross section to a surface of the first electrode. | 2021-12-30 |
| 20210408331 | DISPLAY BACKPLANE AND METHOD OF MANUFACTURING THE SAME, DISPLAY DEVICE - A display backplane includes a base, a plurality of driving electrodes disposed above the base, and a connection structure disposed on at least one of the plurality of driving electrodes. An orthographic projection of the connection structure on the base is within an orthographic projection of a corresponding driving electrode on the base; and the connection structure includes at least one conductive portion disposed at a first included angle with the corresponding driving electrode. | 2021-12-30 |
| 20210408332 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - Provided is a display substrate including: a base substrate, a plurality of micro light-emitting diodes and a plurality of touch electrodes; wherein the micro light-emitting diode comprises: a first electrode, a light-emitting layer, and a second electrode that are sequentially arranged in a direction distal from the base substrate; and the touch electrode is disposed on a side of the micro LED distal from the base substrate. A manufacturing method of manufacturing a display substrate, a display panel, and a display device are also provided. | 2021-12-30 |
| 20210408333 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Discussed is a display device including: a substrate; a plurality of semiconductor light emitting devices arranged on the substrate; a first electrode arranged on the substrate, and electrically connected to the plurality of semiconductor light emitting devices at a lower side of the plurality of semiconductor light emitting devices; a second electrode electrically connected to the plurality of semiconductor light emitting devices at an upper side of the plurality semiconductor light emitting devices; and a plurality of partition walls arranged at the upper side of the plurality of semiconductor light emitting devices, and arranged between the plurality of semiconductor light emitting devices, wherein the substrate is formed of a light transmissive material, and wherein the plurality of partition walls have a width decreased as they become far from the substrate. | 2021-12-30 |
| 20210408334 | DISPLAY PANEL AND DISPLAY MODULE - The present invention provides a display panel and a display module, and the display panel includes: an array substrate; a light emitting device layer on the array substrate, including an anode layer on the array substrate, the anode layer including at least one metal layer; The display panel further includes at least one retaining wall on the array substrate; a distance between an edge of the at least one metal layer in the anode layer and a first boundary of the display panel is greater than a distance between the retaining wall and the first boundary. | 2021-12-30 |
| 20210408335 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a semiconductor layered body including an n-side semiconductor layer having a first region and second regions, a p-side semiconductor layer on the first region, and a light-emitting layer between the first region and the p-side semiconductor layer; an insulating film defining at least one p-side opening above the p-side semiconductor layer and n-side openings each defined above a corresponding second region; an n-side electrode connected to each second region at each corresponding n-side opening; and a p-side electrode electrically connected to the p-side semiconductor layer through the p-side opening. In a top view, the n-side electrode includes at least one base portion on the first region, at least one first extending portion extending in a first direction from the base portion, and at least one second extending portion extending in the first direction from the base portion. | 2021-12-30 |
| 20210408336 | Nanowire Optical Device - A nanowire optical device includes: a photonic crystal body having a planar shape and provided on a base part; an optical waveguide by a line defect in which a plurality of defects including a part without grating elements of the photonic crystal body are linearly arrayed; a trench formed in a waveguide direction in the optical waveguide; a nanowire made of a semiconductor and arranged in the trench; an n-type region formed on one end side of the nanowire; a p-type region formed on the other end side of the nanowire; an active region provided to be interposed between the n-type region and the p-type region in the nanowire; a first electrode connected to the n-type region; and a second electrode connected to the p-type region. | 2021-12-30 |
| 20210408337 | BACKPLATE MANUFACTURING METHOD - The present invention provides a backplate manufacturing method including: manufacturing a second metal layer on an underlay substrate; patterning the second metal layer to form an anode and a cathode; forming a first passivation layer on the second metal layer, patterning the first passivation layer to form an aperture region, wherein the aperture region is configured to expose out the anode and the cathode; manufacturing a second passivation layer on the first passivation layer, the anode, and the cathode; manufacturing a light shielding layer on the second passivation layer, patterning the light shielding layer to remove a part of the light shielding layer in a position corresponding to the aperture region; and removing a part of the second passivation layer above the anode and the cathode. The method of the present invention can provide a soldering effect of the light emitting device and a yield rate of a backplate. | 2021-12-30 |
| 20210408338 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength λ; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness. | 2021-12-30 |
| 20210408339 | PHOTONIC PACKAGE LASER AREA MACRO-VOID PRESSURE RELIEF MICRO-CHANNELS - Embodiments disclosed herein include electronic packages with vents to prevent pressure buildup below a die. In an embodiment, an electronic package comprises a package substrate and a die attached to the package substrate by interconnects. In an embodiment, an underfill is under the die and surrounds the interconnects. In an embodiment, a void is provided in the underfill, and a vent is in the underfill. In an embodiment, the vent is fluidically coupled to the void and extends to an edge of the underfill. | 2021-12-30 |
| 20210408340 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME - A micro-LED device of the present disclosure includes a crystal growth substrate ( | 2021-12-30 |
| 20210408341 | MICRO LED DEVICE AND PRODUCTION METHOD THEREFOR - A micro-LED device of the present disclosure includes a crystal growth substrate ( | 2021-12-30 |
| 20210408342 | Packaged White Light Emitting Devices Comprising Photoluminescence Layered Structure - A light emitting device includes a Chip Scale Packaged (CSP) LED, the CSP LED including an LED chip that generates blue excitation light; and a photoluminescence layer that covers a light emitting face of the LED chip, wherein the photoluminescence layer comprises from 75 wt % to 100 wt % of a manganese-activated fluoride photoluminescence material of the total photoluminescence material content of the layer. The device/CSP LED can further include a further photoluminescence layer that covers the first photoluminescence and that includes a photoluminescence material that generates light with a peak emission wavelength from 500 nm to 650 nm. | 2021-12-30 |
| 20210408343 | Light Source Circuit Unit, Illuminator, And Display - Provided are a light source circuit unit that improves light extraction efficiency, as well as an illuminator and a display that include such a light source circuit unit. The light source circuit unit includes: a circuit substrate having a wiring pattern on a surface thereof, the wiring pattern having light reflectivity, a circular pedestal provided on the circuit substrate, a water-repelling region provided at least from a peripheral edge portion of the pedestal to a part of a side face of the pedestal, and one or two or more light-emitting device chips mounted on the pedestal, and driven by a current that flows through the wiring pattern. | 2021-12-30 |
| 20210408344 | PACKAGED OPTOELECTRIC MODULE AND METHOD FOR ITS PRODUCTION - A stable, hermetically sealed, partially optically transparent package for use to protect optoelectronic components is provided. The package has good cooling for the installed circuit elements and is as stable in relation to temperature and UV. The package has a cap with a frame made of a nitride ceramic and a glass element. The frame has an opening and the glass element hermetically closes the opening. The glass is fused onto the nitride ceramic and is fixed in contact with the nitride ceramic of the frame. | 2021-12-30 |
| 20210408345 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device. The display panel includes a substrate, at least three different light-emitting units disposed on the substrate, and at least three different buffer encapsulation layers disposed on the side of the at least three different light-emitting units facing away from the substrate. The at least three different light-emitting units emit at least three different colors. The thickness of at least one buffer encapsulation layer corresponding to at least one light-emitting unit among the at least three different light-emitting units is different from the respective thicknesses of the other buffer encapsulation layers corresponding to the other light-emitting units among the at least three different light-emitting units. | 2021-12-30 |
| 20210408346 | BACKLIGHT MODULE AND DISPLAY DEVICE - An embodiment of the present invention discloses a backlight module and a display device. The backlight module includes a circuit board. A side surface of the circuit board is provided with a plurality of light emitting elements spaced apart from each other. A light output surface of at least one of the light emitting elements is covered with a first encapsulation layer. A side surface of the first encapsulation layer away from the at least one light emitting elements is a curved surface. | 2021-12-30 |
| 20210408347 | LIGHT EMITTING MODULE AND LIQUID CRYSTAL DISPLAY DEVICE - A light emitting module includes a substrate; at least one light emitting device each including: at least one light emitting element each including: a semiconductor layered structure having a lower surface, an upper surface, and lateral surfaces, and electrodes on the lower surface of the semiconductor layered structure; a light-reflecting part having a lower surface and covering at least the lateral surfaces and the lower surface of the semiconductor layered structure, at least one recessed portion being formed in the lower surface of the light-reflecting part; and a light-transmitting part located over the light-reflecting part and covering an upper surface side of the semiconductor layered structure; an electrically conductive bonding member configured to bond the substrate and the electrodes of each of the at least one light emitting device; and a covering resin spaced apart from the light-transmitting part and disposed at least in the at least one recessed portion and around at least one of the at least one light emitting device. | 2021-12-30 |
| 20210408348 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a transparent substrate, a reflection structure and a light-emitting unit. The transparent substrate is defined with a first surface and a second surface opposite to each other. The reflection structure is disposed on and contacts the second surface of the transparent substrate. The reflection structure includes a reflection layer and a circuit layer. The reflection structure is configured to define a light-transmitting window. The light-emitting unit is disposed corresponding to the light-transmitting window. The light-emitting unit is electrically connected to the circuit layer of the reflection structure, and one optical path of the light-emitting unit passes through the light-transmitting window. | 2021-12-30 |
| 20210408349 | SUBSTRATE, DISPLAY PANEL AND ASSEMBLY DETECTION METHOD THEREOF - Substrate, display panel and assembly detection method thereof are provided. The substrate includes a supporting base and a plurality of sub-pixel areas arranged in an array. A main conductive pad unit and a spare conductive pad unit are formed on the supporting base in each sub-pixel area. An anti-reflection layer is disposed on a side of the supporting base adjacent to the main conductive pad unit and the spare conductive pad unit. An orthographic projection of the anti-reflection layer on the supporting base at least covers an orthographic projection of the spare conductive pad unit on the supporting base. | 2021-12-30 |
| 20210408350 | ELECTRONIC DEVICE - An electronic device includes a substrate, a first circuit, a plurality of bonding pads and a diode. The first circuit is disposed on the substrate. The bonding pads are disposed on the substrate, wherein at least one of the bonding pads is electrically connected to the first circuit through a bridge line. The diode is disposed on the substrate and electrically connected to the first circuit through at least one of the bonding pads. The bridge line crosses over a data line in a top view. | 2021-12-30 |
| 20210408351 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT COMPRISING FIRST CONNECTION REGIONS, AND OPTOELECTRONIC DEVICE - An optoelectronic semiconductor component having an optoelectronic semiconductor chip for emitting electromagnetic radiation. The optoelectronic semiconductor chip may have a first semiconductor layer, a second semiconductor layer, first and second current spreading layers, electrical connection elements and first connection regions. The first current spreading layer is arranged on a side of the first semiconductor layer facing away from the second semiconductor layer. The first current spreading layer is electrically connected to the first semiconductor layer. The electrical connection elements electrically connect the second semiconductor layer to the second current spreading layer. The first connection regions are connected to the first current spreading layer and extend through the second current spreading layer. An area coverage of the first connection regions in a region between adjacent parts of the second current spreading layer is greater than 20% of the area coverage of the second current spreading layer. | 2021-12-30 |
| 20210408352 | THERMOELECTRIC GENERATOR - A thermoelectric generator includes a heat reception portion, a heat release portion, a thermoelectric generation module that is arranged between the heat reception portion and the heat release portion, and a heat transfer mechanism that includes a first connection portion configured to be connected to the thermoelectric generation module and a second connection portion configured to be connected to at least one of the heat reception portion and the heat release portion, the heat transfer mechanism being at least partially resiliently deformed. | 2021-12-30 |
| 20210408353 | HEAT SINK SHIELD AND THERMOELECTRIC FAN WITH HEAT SINK SHIELD - A thermoelectric fan including: a heat collector; a thermoelectric generator (TEG) thermally coupled to the heat collector; a heat sink thermally coupled to the TEG and positioned to provide a temperature differential across the TEG; a motor in electrical communication with the TEG; a fan blade coupled to the motor and configured to generate a first airflow through the heat sink; and a heat sink shield configured to shield the heat sink from a second airflow, the second airflow having a higher temperature than the first airflow. The second airflow may be generated by the fan blade interacting with the first airflow. A heat sink shield for a thermoelectric fan wherein the heat sink shield is configured to attach to the thermoelectric fan and configured to at least partially shield the heat sink from a vorticity vector field and related air flows generated by the fan blade. | 2021-12-30 |
| 20210408354 | QUANTUM DEVICE - To provide a quantum device capable of preventing a connection member connecting a quantum chip with an interposer from being broken. The quantum device | 2021-12-30 |
| 20210408355 | SYSTEM AND METHOD FOR SUPERCONDUCTING MULTI-CHIP MODULE - A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged. | 2021-12-30 |
| 20210408356 | Diode Devices Based on Superconductivity - An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode. | 2021-12-30 |
| 20210408357 | Photodetector with Superconductor Nanowire Transistor Based on Interlayer Heat Transfer - A transistor includes (i) a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature and (ii) a second wire including a superconducting component configured to operate in a superconducting state while: a temperature of the superconducting component is below a superconducting threshold temperature and a first input current supplied to the superconducting component is below a current threshold. The semiconducting component is located adjacent to the superconducting component. In response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold. | 2021-12-30 |
| 20210408358 | QUANTUM DEVICE AND METHOD OF MANUFACTURING THE SAME - A quantum device ( | 2021-12-30 |
| 20210408359 | SUPERCONDUCTOR FLUX PINNING WITHOUT COLUMNAR DEFECTS - There is a superconducting article that includes a superconducting film comprising a substrate, one or more buffer layers, and a high temperature superconducting (HTS) layer. The superconducting layer may be comprised of the chemical composition REBa | 2021-12-30 |
| 20210408360 | SELECTIVE CHEMICAL FREQUENCY MODIFICATION OF JOSEPHSON JUNCTION RESONATORS - Techniques regarding selectively tuning the operating frequency of superconducting Josephson junction resonators are provided. For example, one or more embodiments described herein can comprise a method that can include chemically altering a Josephson junction of a Josephson junction resonator via a plasma treatment. The method can also comprise selectively tuning an operating frequency of the Josephson junction resonator based on a property of the plasma treatment. | 2021-12-30 |
| 20210408361 | Piezoelectric Element, Liquid Discharge Head, And Printer - A piezoelectric element includes: a first electrode and a second electrode; and a piezoelectric layer provided between the first electrode and the second electrode and having a perovskite structure, in which 0| 2021-12-30 | |
| 20210408362 | PIEZOELECTRIC ACTUATOR - A piezoelectric actuator includes a square suspension plate, an outer frame, a plurality of brackets and a square piezoelectric ceramic plate. The outer frame is arranged around the suspension plate. A second surface of the outer frame and a second surface of the suspension plate are coplanar with each other. Each of the plurality of brackets has two ends, a first end is perpendicular to and connected with the suspension plate, and a second end is perpendicular to and connected with the outer frame for elastically supporting the suspension plate. Each bracket has a length in a range between 1.22 mm and 1.45 mm and a width in a range between 0.2 mm and 0.6 mm. A length of the piezoelectric ceramic plate is not larger than a length of the suspension plate. The piezoelectric ceramic plate is attached on a first surface of the suspension plate. | 2021-12-30 |
| 20210408363 | ULTRASONIC WAVE GENERATION DEVICE - A low-profile ultrasonic wave generation device is provided that includes a drive unit having a piezoelectric member and an electrode formed on a surface of the piezoelectric member. The drive unit as a whole vibrates flexurally. The connection member is connected to a portion of the drive unit that includes a point of maximum displacement of the drive unit when the drive unit is subjected to flexural vibration. The vibrating unit is connected to the connection member. The vibrating unit vibrates due to the flexural vibration of the drive unit being transmitted by the connection member and thereby generates ultrasonic waves. | 2021-12-30 |
| 20210408364 | PIEZOELECTRIC SENSOR - A piezoelectric sensor, comprising at least one first electrode, at least one second electrode, and a piezoelectric material, wherein the piezoelectric material has an anisotropic electromechanical coupling and the at least one first and second electrodes are at least in part embedded in the piezoelectric material, the piezoelectric material having a first surface wherein the electrodes extend vertically within the piezoelectric material from the first surface. | 2021-12-30 |
| 20210408365 | Method For Manufacturing Vibrator, Vibrator, And Vibrator Device - A vibrator includes: a base portion; a vibrating arm including an arm portion which extends from the base portion, and a weight portion which is located on a tip end side of the arm portion and which has a first main surface and a second main surface that are in a front-back relationship; and a weight film disposed at the first main surface of the weight portion. The first main surface includes a first planar surface, a second planar surface which is located closer to the second main surface than is the first planar surface and which is parallel to the first planar surface, and an inclined surface which couples the first planar surface and the second planar surface and which forms an angle of 100° or less with the first planar surface. A method for manufacturing a vibrator includes: a preparation step of preparing the above-described vibrator; and a removing step of removing a part of the weight film by emitting an energy ray to the weight film from a normal direction of the first planar surface. | 2021-12-30 |
| 20210408366 | Method For Manufacturing Vibrator, Vibrator And Vibrator Device - A vibrator includes: a base portion; a vibrating arm including an arm portion which extends from the base portion, and a weight portion which is located on a tip end side of the arm portion and which has a first main surface and a second main surface that are in a front-back relationship; and a weight film disposed at the first main surface of the weight portion. The first main surface includes a planar surface and an inclined surface inclined with respect to the planar surface. A method for manufacturing a vibrator includes: a preparation step of preparing the above-described vibrator; and a removing step of removing a part of the weight film by emitting an energy ray to the weight film. In the removing step, the weight film disposed at the planar surface is removed and the weight film disposed at the inclined surface is not removed by emitting the energy ray to the weight film from a normal direction of the planar surface. | 2021-12-30 |
| 20210408367 | METHOD FOR PRODUCING FERROELECTRIC POLYMER ELEMENT, FERROELECTRIC POLYMER ELEMENT AND PIEZOELECTRIC SENSOR - A method for producing a ferroelectric polymer element includes: disposing one electrode on a substrate; applying polymer solution in which a polyvinylidene fluoride-based polymer is dissolved in a solvent including an aprotic polar solvent onto the one electrode by forme-based printing; firing the polymer solution to crystallize the polyvinylidene fluoride-based polymer, so that a ferroelectric layer is formed; and disposing the other electrode on the ferroelectric layer. | 2021-12-30 |
| 20210408368 | MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND MANUFACTURING METHOD THEREOF - A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device. | 2021-12-30 |
| 20210408369 | TOPOLOGICAL SPIN TEXTURES IN 3-DIMENSIONAL MAGNETIC STRUCTURES - Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a spin traversing along the band for a complete cycle will recover its original position, while having rotated away from its original orientation. The spins can respond to an external magnetic field, but cannot achieve a ferromagnetic state, in which all magnetic moments are pointing in the same direction, due to the topological knot. 3D assemblies of such nano-Möbius strips may form prototype secure magnetic information storage devices that are secure and with extremely low levels of energy dissipation. | 2021-12-30 |
| 20210408370 | Bismuth Antimony Alloys for Use as Topological Insulators - A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation. | 2021-12-30 |
| 20210408371 | MAGNETORESISTIVE STRUCTURE HAVING TWO DIELECTRIC LAYERS, AND METHOD OF MANUFACTURING SAME - A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer. | 2021-12-30 |
| 20210408372 | NON-VOLATILE RESISTANCE SWITCHING IN MONOSLAYER ATOMIC SHEETS - The present disclosure provides a 2-dimensional (2D) non-volatile switch (2DNS), with a vertical metal-insulator-metal (MIM) structure that includes a semiconducting monolayer crystalline non-metallic atomic sheet sandwiched between a top metal electrode and a bottom metal electrode. The 2DNS is able to perform stable non-volatile resistance switching, including both unipolar and bipolar switching, with a high ON/OFF ratio, low ON resistance, and low operating voltage. The monolayer atomic sheet may include hexagonal boron nitride (h-BN) or a transition metal dichalcogenide (TMD), such as MoS | 2021-12-30 |
| 20210408373 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode. | 2021-12-30 |
| 20210408374 | INSULATION OF PHASE-CHANGE MEMORY CELLS - Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells. | 2021-12-30 |
