52nd week of 2021 patent applcation highlights part 72 |
Patent application number | Title | Published |
20210407975 | MANUFACTURING METHOD OF MICRO-LED DISPLAY DEVICE - The present disclosure provides a manufacturing method of a micro-LED display device. In the method, a display backboard and a substrate are made separately, and then the display backboard and the substrate are synthesized, after the substrate is removed, a micro-LED array, a protective layer, and a transparent electrode layer are formed on the display backboard formed with an LED single crystal film layer. Beneficial effect is that LED transfer bonding can be self-aligned, conventional mass transfer process can be avoided, process is simple, production cost is reduced, and product yield and pixels of the micro-LED display device are greatly improved. | 2021-12-30 |
20210407976 | DISPLAY BACKPLATE AND METHOD FOR MANUFACTRING SAME, DISPLAY PANEL AND METHOD FOR MANUFACTUURING SAME, AND DISPLAY DEVICE - Provided is a display backplate includes including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate. | 2021-12-30 |
20210407977 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - The present disclosure provides a display panel, a method for manufacturing a display panel and a display device. The display panel includes a substrate, and a light emitting element array and a quantum dot color filter array arranged on the substrate, the quantum dot color filter array is arranged on a light exiting side of the light emitting element array, and quantum dot color filters in the quantum dot color filter array correspond to light emitting elements in the light emitting element array one to one, and the display panel further includes a blocking structure arranged between the light emitting element array and the quantum dot color filter array so as to block heat dissipated by the light emitting elements from being conducted to the quantum dot color filters. | 2021-12-30 |
20210407978 | METHOD AND DEVICE FOR MASS TRANSFER OF MICRO SEMICONDUCTOR ELEMENTS - A mass transfer method includes providing a transfer unit and a semiconductor carrying unit connected therewith, removing an element supporting structure of the semiconductor carrying unit from micro semiconductor elements of the semiconductor carrying unit, partially removing the photosensitive layer to form connecting structures, connecting a package substrate with electrodes of the micro semiconductor elements, breaking the connecting structures to separate the micro semiconductor elements from the transfer substrate. A mass transfer device is also disclosed. | 2021-12-30 |
20210407979 | INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING SPLIT, DOUBLE-SIDED METALLIZATION STRUCTURES TO FACILITATE A SEMICONDUCTOR DIE ("DIE") MODULE EMPLOYING STACKED DICE, AND RELATED FABRICATION METHODS - Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package. | 2021-12-30 |
20210407980 | 3D Semiconductor Package Including Memory Array - Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die is bonded to the being structure by dielectric-to-dielectric bonds and metal-to-metal bonds. | 2021-12-30 |
20210407981 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a display panel including a first surface and a second surface, where a display area which displays images is arranged in the first surface; a driving panel arranged on the display panel and including a first surface and a second surface; and a filling portion filled between the display panel and the driving panel. The display panel and the driving panel are stacked in a vertical direction in a cross-sectional view, and signal lines of the display panel may be electrically connected to signal lines of the driving panel, respectively, through a contact hole penetrating the display area and the driving panel. | 2021-12-30 |
20210407982 | DISPLAY PANEL, CHIP ON FILM, DISPLAY EQUIPMENT, AND MANUFACTURING METHOD - The display panel includes: a plurality of first connection terminals, the first connection terminals being arranged into a first terminal row along a second direction, long edges of the first connection terminals being oriented along a first direction; and a plurality of second connection terminals, the second connection terminals being arranged into a second terminal row along the second direction, long edges of the second connection terminals being oriented along the second direction, the first terminal row and the second terminal row being arranged side by side along the first direction, the second direction not paralleling the first direction, the first connection terminals and the second connection terminals being connected respectively to different display rows or display columns within a display region of the display panel, and configured respectively to receive a drive signal driving display by the display panel. | 2021-12-30 |
20210407983 | Wafer Bonding in Fabrication of 3-Dimensional NOR Memory Circuits - A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material. | 2021-12-30 |
20210407984 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace. | 2021-12-30 |
20210407985 | INTEGRATED CIRCUIT DEVICE AND METHOD - A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. | 2021-12-30 |
20210407986 | MULTI-BIT STRUCTURE - An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell. | 2021-12-30 |
20210407987 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW PARASITIC CAPACITANCE THEREOF - An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively. | 2021-12-30 |
20210407988 | METHODS OF FABRICATING SINGLE-STACK BIPOLAR-BASED ESD PROTECTION DEVICES - Methods of fabricating ESD protection devices include forming a single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40 V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly-doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40 V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage. | 2021-12-30 |
20210407989 | METHODS OF FORMING CIRCUIT-PROTECTION DEVICES - Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device. | 2021-12-30 |
20210407990 | CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS - A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus. | 2021-12-30 |
20210407991 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the third layer includes crystalline silicon; and at least one temperature sensor. | 2021-12-30 |
20210407992 | ON-CHIP HEATER TEMPERATURE CALIBRATION - Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor. | 2021-12-30 |
20210407993 | INTEGRATION OF SILICON CHANNEL NANOSTRUCTURES AND SILICON-GERMANIUM CHANNEL NANOSTRUCTURES - A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index. | 2021-12-30 |
20210407994 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height. | 2021-12-30 |
20210407995 | Method of Tuning Threshold Voltages of Transistors - A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer. | 2021-12-30 |
20210407996 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED DUAL NANORIBBON CHANNEL STRUCTURES - Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires. | 2021-12-30 |
20210407997 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING SELECTIVE BOTTOM-UP APPROACH - Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires. | 2021-12-30 |
20210407998 | DEVICE CHANNEL PROFILE STRUCTURE - A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect. | 2021-12-30 |
20210407999 | STACKED FORKSHEET TRANSISTORS - Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device. | 2021-12-30 |
20210408000 | Isolation Structure for Preventing Unintentional Merging of Epitaxially Grown Source/Drain - A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component. | 2021-12-30 |
20210408001 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer. | 2021-12-30 |
20210408002 | DOUBLE WALL CAPACITORS AND METHODS OF FABRICATION - An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer. | 2021-12-30 |
20210408003 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided. | 2021-12-30 |
20210408004 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region. | 2021-12-30 |
20210408005 | METHOD FOR PREPARING A MEMORY DEVICE WITH AIR GAPS FOR REDUCING CAPACITIVE COUPLING - The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, forming a word line in the substrate, wherein the word line is intersected with the active region; forming a contact structure on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; sequentially forming a first conductive layer and a second conductive layer over the substrate, wherein the contact structure is covered by the first and second conductive layers; patterning the first and second conductive layers to form a conductive pillar and a landing pad, respectively, wherein the conductive pillar is overlapped with and electrically connected to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and forming a dielectric layer to laterally surround the conductive pillar and the landing pad. | 2021-12-30 |
20210408006 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes. | 2021-12-30 |
20210408007 | Integrated Circuitry, DRAM Circuitry, Method Used in Forming Integrated Circuitry, and Method Used in Forming Memory Circuitry - A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias. Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness. A plurality of electronic components is formed above the fourth insulating material and that individually are directly electrically coupled to individual of the conductive vias through the fourth and second insulating materials. Other embodiments, including structure, are disclosed. | 2021-12-30 |
20210408008 | SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region. | 2021-12-30 |
20210408009 | CHANNEL DEPOPULATION FOR FORKSHEET TRANSISTORS - Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge. | 2021-12-30 |
20210408010 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a SRAM device including a pull-up device and a pull-down device. The pull-up device includes a plurality of first epitaxial source and drain (S/D) features on a first fin, and a plurality of first residues between the plurality of first epitaxial source and drain (S/D) features and the first fin. The pull-down device includes a plurality of second epitaxial S/D features on a second fin. | 2021-12-30 |
20210408011 | FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME - A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage. | 2021-12-30 |
20210408012 | Source/Drain Feature Separation Structure - A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion. | 2021-12-30 |
20210408013 | MEMORY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer. | 2021-12-30 |
20210408014 | MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a number of first semiconductor layers that are vertically spaced apart from one another, a second S/D structure coupled to a first end of the first semiconductor layers; and a third S/D structure coupled to a second end of the first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure. | 2021-12-30 |
20210408015 | PACKAGE EMBEDDED PROGRAMMABLE RESISTOR FOR VOLTAGE DROOP MITIGATION - Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor. | 2021-12-30 |
20210408016 | VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE - A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate. | 2021-12-30 |
20210408017 | METHOD FOR FABRICATING A METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A semiconductor substrate having a gate dielectric layer and a conductive layer is provided. The conductive layer is patterned into a main gate portion. A drain region and a source region are formed on two sides of the main gate portion, respectively. By thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between a channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region are formed. A first extension gate portion and a second extension gate portion are formed on two opposite sidewalls of the main gate portion, respectively. The main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor. | 2021-12-30 |
20210408018 | FERROELECTRIC CAPACITORS AND METHODS OF FABRICATION - An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode. | 2021-12-30 |
20210408019 | BONDED MEMORY DEVICES AND METHODS OF MAKING THE SAME - At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding. | 2021-12-30 |
20210408020 | BONDED MEMORY DEVICES AND METHODS OF MAKING THE SAME - At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding. | 2021-12-30 |
20210408021 | FERROELECTRIC MEMORY DEVICE USING BACK-END-OF-LINE (BEOL) THIN FILM ACCESS TRANSISTORS AND METHODS FOR FORMING THE SAME - A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate. | 2021-12-30 |
20210408022 | FERROELECTRIC RANDOM ACCESS MEMORY DEVICES AND METHODS - A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure. | 2021-12-30 |
20210408023 | POLYSILICON REMOVAL IN WORD LINE CONTACT REGION OF MEMORY DEVICES - The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure. | 2021-12-30 |
20210408024 | HOLE PRE-CHARGE SCHEME USING GATE INDUCED DRAIN LEAKAGE GENERATION - A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor. | 2021-12-30 |
20210408025 | SPACERLESS SOURCE CONTACT LAYER REPLACEMENT PROCESS AND THREE-DIMENSIONAL MEMORY DEVICE FORMED BY THE PROCESS - In-process source-level material layers including a source-level sacrificial layer is formed over a substrate, and an alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory openings and backside openings are formed through the alternating stack and into the in-process source-level material layers. Memory opening fill structures are formed in the memory openings. A source cavity is formed by removing the source-level sacrificial layer by introducing an etchant through the backside openings, and a source contact layer in the source cavity. The backside openings are laterally expanded and are merged to form backside trenches. Remaining portions of the sacrificial material layers are replaced with electrically conductive layers through the respective backside trenches. | 2021-12-30 |
20210408026 | VERTICAL MEMORY DEVICES - Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes. | 2021-12-30 |
20210408027 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper. | 2021-12-30 |
20210408028 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure. | 2021-12-30 |
20210408029 | FORMING TERMINATIONS IN STACKED MEMORY ARRAYS - A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment. | 2021-12-30 |
20210408030 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory includes: a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and the first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug disposed in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein a portion of the third line, located in the cell region contacts the second line, and another portion of the third line located over the contact plug is spaced apart from the second line. | 2021-12-30 |
20210408031 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LOW RESISTANCE SOURCE-LEVEL CONTACT AND METHOD OF MAKING THEREOF - A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity. | 2021-12-30 |
20210408032 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING III-V COMPOUND SEMICONDUCTOR CHANNEL LAYER AND METHOD OF MAKING THE SAME - A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached. | 2021-12-30 |
20210408033 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING III-V COMPOUND SEMICONDUCTOR CHANNEL LAYER AND METHOD OF MAKING THE SAME - A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached. | 2021-12-30 |
20210408034 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer. | 2021-12-30 |
20210408035 | SPACERLESS SOURCE CONTACT LAYER REPLACEMENT PROCESS AND THREE-DIMENSIONAL MEMORY DEVICE FORMED BY THE PROCESS - A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers. | 2021-12-30 |
20210408036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked structure with conductive layers and insulating layers that are stacked alternately with each other, an insulating pillar passing through the stacked structure, a first channel pattern surrounding a sidewall of the insulating pillar, a second channel pattern surrounding the sidewall of the insulating pillar, a first insulator formed between the first channel pattern and the second channel pattern, and a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, the memory layer with a first opening located that is between the first channel pattern and the second channel pattern. | 2021-12-30 |
20210408037 | SEMICONDUCTOR DEVICE - A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern. | 2021-12-30 |
20210408038 | 3D MEMORY ARRAY CONTACT STRUCTURES - A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths. | 2021-12-30 |
20210408039 | Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed. | 2021-12-30 |
20210408040 | VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate. | 2021-12-30 |
20210408041 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a first stack including a plurality of conductive layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; a second stack including a plurality of sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the substrate; a plurality of stepped grooves defined at different depths in the first stack; and an opening defined in the second stack, and having, on a sidewall thereof, a plurality of steps which have the same heights as differences in depth between the plurality of stepped grooves. | 2021-12-30 |
20210408042 | THREE-DIMENSIONAL STACKABLE FERROELECTRIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF FORMING - A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material. | 2021-12-30 |
20210408043 | HIGH DENSITY 3D FERAM - A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure. | 2021-12-30 |
20210408044 | MEMORY ARRAY ISOLATION STRUCTURES - A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %). | 2021-12-30 |
20210408045 | MEMORY ARRAY SOURCE/DRAIN ELECTRODE STRUCTURES - A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line. | 2021-12-30 |
20210408046 | MEMORY ARRAY CONTACT STRUCTURES - A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line. | 2021-12-30 |
20210408047 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another. | 2021-12-30 |
20210408048 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a substrate, a first stacking structure, a second stacking structure, struts, an isolation structure, memory films, channel layers, and conductive pillars. The first stacking structure includes first gate layers and is located on the substrate. The second stacking structure includes second gate layers and is located on the substrate, where the second stacking structure is separated from the first stacking structure through a trench. The struts stand on the substrate and are located in the trench, where the struts each have two opposite surfaces respectively in contact with the first stacking structure and the second stacking structure. The isolation structure stands on the substrate and is located in the trench, where cell regions are located in the trenches, and at least two of the cell regions are separated from one another through a respective one strut and the isolation structure connected therewith. The memory films are respectively located in the cell regions, and the memory films each cover a sidewall of a respective one of the cell regions. The channel layers respectively cover an inner surface of a respective one of the memory films, where the memory films are sandwiched between the first gate layers and the channel layers. The conductive pillars stand on the substrate within the cell regions and are covered by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars are laterally separated from one another. | 2021-12-30 |
20210408049 | SEMICONDUCTOR CHIP - A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors. | 2021-12-30 |
20210408050 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present application provides an array substrate and a display panel. The array substrate comprises: a substrate; a first metal layer; a first insulating layer; a second metal layer disposed on the first insulating layer, the second metal layer forming a scan line, a first connection metal, and a first drain of the first thin film transistor; a second insulating layer; a third metal layer disposed on the second insulating layer, the third metal layer being electrically connected to the first gate, and a portion of the third metal layer opposite to the first connecting metal forms a bootstrap capacitor. | 2021-12-30 |
20210408051 | METHOD OF MANUFACTURING ARRAY SUBSTRATE AND ARRAY SUBSTRATE - A method of manufacturing an array substrate and an array substrate are provided. The method includes steps of providing a first metallic layer, a semiconductor layer, a second metallic layer, a common electrode layer, a protecting layer, and a pixel electrode layer on a substrate in sequence. The semiconductor layer is electrically connected to a source electrode of the first metallic layer through a first via hole. Part of the semiconductor layer is electrically connected to a drain electrode of the second metallic layer. A touch electrode is electrically connected to a touch signal line through a second via hole. The pixel electrode layer is electrically connected to the drain electrode through a third via hole. | 2021-12-30 |
20210408052 | ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - An array substrate is provided. The array substrate includes a base substrate; a first bonding pad layer including a plurality of first bonding pads on a first side of the base substrate; a second bonding pad layer including a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and a plurality of signal lines on a side of the second bonding pad layer away from the base substrate. A respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads. The respective one of the plurality of first bonding pads includes a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side. | 2021-12-30 |
20210408053 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate and a manufacturing method thereof are provided. A patterned metal member of the array substrate includes a patterned first metal layer, a patterned second metal layer, and a patterned copper layer which are sequentially disposed on a substrate. An etching rate at which an etching solution etches the second metal layer is less than another etching rate at which the etching solution etches the first metal layer. An adhesion force between the patterned first metal layer and the substrate is greater than another adhesion force between the patterned copper layer and the substrate. | 2021-12-30 |
20210408054 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING SAME - The present disclosure provides an array substrate including a flexible substrate. The flexible substrate includes a display area and a bending area on a side of the display area. The bending area is provided with first traces, an insulating layer, buffer strips, a sealing layer, and second traces. The first traces are disposed on the flexible substrate at intervals. The insulating layer covers the flexible substrate and the first traces and is provided with a groove on each of the first traces. The buffer strips are respectively filled in the grooves. The sealing layer covers the insulating layer and the buffer strips to seal the buffer strips in the grooves. The second traces are disposed on the sealing layer at intervals. Projections of the second traces coincide with projections of the first traces on the flexible substrate. The present disclosure further provides a method for fabricating the array substrate. | 2021-12-30 |
20210408055 | DISPLAY PANEL AND TERMINAL DEVICE FOR APPLICATION - A display panel and a terminal device thereof are provided. The display panel defines a display region and a camera region, and includes substrate layers and a device function layer disposed on the substrate layers. The substrate layers include a first substrate, a first buffer layer, a second substrate and a second buffer layer, which are sequentially stacked. The device function layer is disposed on the second buffer layer. The first buffer layer is provided with a first through hole in the camera region, and the second substrate downwardly fills the first through hole and further contacts the first substrate. | 2021-12-30 |
20210408056 | ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - An array substrate having a plurality of subpixels is provided. In a respective one of the plurality of subpixels, the array substrate includes a base substrate; and a thin film transistor on the base substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The drain electrode includes a first portion, a second portion, and a third portion connecting the first portion and the second portion. An orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of a first gate line protrusion of a respective one of the plurality of gate lines on the base substrate. An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a second gate line protrusion of the respective one of the plurality of gate lines on the base substrate. | 2021-12-30 |
20210408057 | Display Panel And Display Device - Disclosed are a display panel and a display device. The display panel includes a display area, a wiring area, and a bending area connecting the display area and the wiring area; the bending area includes a first boundary on a side closer to the display area; in the first direction, an extension length of the first boundary is less than an extension length of the wiring area; in the second direction, a vertical projection of the first boundary in the wiring area is located within the coverage of the wiring area; in the second direction, the display area includes sub-pixel rows, and the last sub-pixel row is located on a side of the display area closer to the wiring area; in the first direction, a first sub-pixel in the last sub-pixel row is located on a side of the wiring area boundary closer to the center of the display panel. | 2021-12-30 |
20210408058 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present invention provides an array substrate and a display panel, the array substrate comprises: a first metal layer comprising a plurality of gate routings and a plurality of common electrode routings, at least one of the plurality of common electrode routings is arranged discontinuously and comprises a plurality of common electrode spacers spaced apart from each other; a second metal layer comprising a plurality of common electrode connecting portions; and a first insulating layer provided with a plurality of first through holes, adjacent two of the plurality of common electrode spacers are electrically connected to a common electrode connecting portion through two of the plurality of first through holes. | 2021-12-30 |
20210408059 | FAN-OUT WIRE STRUCTURE, DISPLAY PANEL, AND DISPLAY DEVICE - A fan-out wire structure, a display panel, and a display device are provided. The fan-out wire structure includes a first wiring layer, a second wiring layer, and a plurality of fan-out wires. The fan-out wires include a plurality of first fan-out wires and a plurality of second fan-out wires. The first fan-out wires are disposed in the first wiring layer. The fan-out wires are disposed in the second wiring layer. Each of the first fan-out wires is provided with a first impedance unit. Each of the second fan-out wires is provided with a second impedance unit. | 2021-12-30 |
20210408060 | ARRAY SUBSTRATE, DISPLAY APPARATUS AND DRIVE METHOD THEREFOR - An array substrate, a display device and a driving method thereof are provided. The array substrate includes a plurality of sub-pixels arranged in an array in a first direction and a second direction; and a plurality of gate lines and a plurality of data lines. The plurality of data lines include first data lines and second data lines alternately arranged in the first direction, two columns of sub-pixels arranged in the second direction are arranged between a first data line and a second data line, and the first data line and the second data line are respectively configured to transmit data signals of different polarities. Two adjacent sub-pixels arranged in the first direction are respectively connected to the first data line and the second data line, and two adjacent sub-pixels arranged in the second direction are respectively connected to the first data line and the second data line. | 2021-12-30 |
20210408061 | Display Device - Disclosed is a display device including a substrate including display and non-display areas, a first thin-film transistor located in the non-display area, and second and third thin-film transistors located in the display area. The first thin-film transistor includes a first semiconductor pattern, a first gate electrode overlapping the first semiconductor pattern, and first source and first drain electrodes connected to the first semiconductor pattern. The second thin-film transistor includes second and third semiconductor patterns including a first oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a third gate electrode overlapping the third semiconductor pattern, and second source and second drain electrodes connected to the second and third semiconductor patterns. The third thin-film transistor includes a fourth semiconductor pattern including a first oxide semiconductor, a fourth gate electrode overlapping the fourth semiconductor pattern, and third source and third drain electrodes connected to the fourth semiconductor pattern. | 2021-12-30 |
20210408062 | TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention provides a thin-film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method uses a four-mask process that uses an etch-stop layer on a semiconductor layer as a mask to perform alignment and etching to form a pattern of an amorphous silicon island. Tail fibers exposed outside of a source and a drain are removed, photoelectric sensitivity of a TFT device can be effectively reduced, and size of the TFT device is reduced, which can simplify processes, save layout space, and effectively increase display quality of large-size and high-resolution liquid crystal panels under high backlight intensity. | 2021-12-30 |
20210408063 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING SAME - An array substrate and a method of manufacturing the same are provided. The array substrate includes a base substrate, a buffer layer, an active layer, a dielectric insulating layer, and a source/drain layer stacked in sequence. A trench is provided on a surface of the base substrate facing the buffer layer, and the trench is sunk to another surface of the base substrate. The array substrate further includes a gate layer. The gate layer is disposed in the trench of the base substrate. The buffer layer is disposed on the base substrate and totally covers the gate layer. | 2021-12-30 |
20210408064 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - The disclosure relates to a display panel. The display panel may have a display area, a transition area, and a via hole area. The transition area may be between the via hole area and the display area. The display panel may include a substrate; an isolation structure on the substrate only in the transition area; and an encapsulation layer in both of the transition area and the display area. A first side surface of the isolation structure facing the via hole area may include a recess toward an interior of the isolation structure, and the encapsulation layer may include a cavity surrounding the isolation structure in the recess. | 2021-12-30 |
20210408065 | TFT SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a thin film transistor (TFT) substrate and a display device, the TFT substrate includes an base substrate and a plurality of pixel units, wherein each of the pixel units includes a TFT on the base substrate, the TFT includes a source drain layer, an active layer, and a gate layer; the TFT substrate further includes a light shielding layer on a side of the source drain layer of the TFT distal to the base substrate, and an orthographic projection of the light shielding layer on the base substrate completely covers an orthographic projection of the active layer of the TFT on the base substrate, and partially covers an orthographic projection of the gate layer of the TFT on the base substrate. | 2021-12-30 |
20210408066 | DEMULTIPLEXER AND ARRAY SUBSTRATE INCLUDING THE SAME, DISPLAY DEVICE - The present disclosure provides a demultiplexer, an array substrate and a display device. The array substrate comprises a plurality of data line leads, a plurality of data lines arranged side by side and the demultiplexer. The demultiplexer includes first to third control gate lines arranged in parallel and first to sixth thin film transistors. The first thin film transistor to the third thin film transistor are positioned at a side of the demultiplexer proximal to the first control gate line, the fourth thin film transistor to the sixth thin film transistor are positioned at a side of the demultiplexer proximal to the third control gate line, and drains of the first thin film transistor to the sixth thin film transistor are respectively coupled to corresponding ones of the plurality of data lines. | 2021-12-30 |
20210408067 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - The present disclosure relates to an array substrate, a manufacturing method thereof, and a display panel, the array substrate including: a substrate, and a low temperature polysilicon layer, an inorganic film group layer, and a source/drain layer disposed on the substrate in sequence. The substrate includes a display region, the low temperature polysilicon layer located at the display region, the inorganic film group layer provided with a through hole, and an angle between a sidewall and a bottom wall of the through hole is not less than 100 degrees; the source/drain layer covering the sidewall and the bottom wall of the through hole to be connected to the low temperature polysilicon layer. | 2021-12-30 |
20210408068 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE - An array substrate, a method of manufacturing the same, and a display device are provided. The array substrate includes a first active layer and a second active layer. A material of the first active layer comprises low temperature poly-silicon. A material of the second active layer comprises an oxide semiconductor. The first active layer and the second active layer are disposed at different layers and horizontally staggered. | 2021-12-30 |
20210408069 | TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes. | 2021-12-30 |
20210408070 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING SAME - An array substrate and a method for fabricating same are provided. Base on the existing process, the order of forming the coating film of the thin film transistor and forming the photoresist are adjusted. Thus, a patterning treatment can be directly performed on the first coating film, such that an etching process on the first coating film in the later can be avoided. Therefore, the etching process in the patterning treatment can be omitted, the fabrication process can be simplified, the production efficiency of the product can be improved, and the cost can be reduced. | 2021-12-30 |
20210408071 | TFT ARRAY SUBSTRATE AND DISPLAY PANEL - The present application discloses a thin-film transistor (TFT) array substrate and a display panel. The TFT array substrate includes an active layer and a source/drain electrode disposed on the active layer. The active layer includes an electrode coverage region, a channel region, and a first peripheral region disposed around the electrode coverage region and the channel region. The active layer located in the first peripheral region is distributed in multi-sections. | 2021-12-30 |
20210408072 | DISPLAY PANEL, GATE ELECTRODE DRIVING CIRCUIT, AND ELECTRONIC DEVICE - A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively. | 2021-12-30 |
20210408073 | METAL OXIDE AND FIELD-EFFECT TRANSISTOR - To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern. | 2021-12-30 |
20210408074 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance. | 2021-12-30 |