52nd week of 2021 patent applcation highlights part 71 |
Patent application number | Title | Published |
20210407875 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least one semiconductor element, a sealing resin body, a first main terminal, and a second main terminal. The at least one semiconductor element has, as main electrodes, a first main electrode and a second main electrode. A main current flows between the first main electrode and the second main electrode. The sealing resin body seals the at least one semiconductor element. The first main terminal is electrically connected to the first main electrode inside the sealing resin body. The second main terminal is electrically connected to the second main electrode inside the sealing resin body. Each of the first main terminal and the second main terminal extends to an outside of the sealing resin body for connecting to an external member. | 2021-12-30 |
20210407876 | SEMICONDUCTOR DEVICE - The semiconductor device includes a semiconductor element having first and second main electrodes, first and second substrates connected to the first and second main electrodes, respectively, first and second main terminals connected to the first and second main electrodes via the first and second substrates, respectively, and a bonding member. The bonding member is interposed between the first and second main electrodes and between the first and second substrates, respectively. At least one of the first and second main terminals includes a plurality of terminals. The first and second main terminals are alternately arranged in one direction orthogonal to the thickness direction of the semiconductor element. The first and second main terminals are directly bonded to the first and second substrates without the bonding member. | 2021-12-30 |
20210407877 | INTEGRATED CIRCUIT DIE PACKAGES INCLUDING A CONTIGUOUS HEAT SPREADER - A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous. | 2021-12-30 |
20210407878 | POWER SEMICONDUCTOR DEVICES WITH HIGH TEMPERATURE ELECTRICAL INSULATION - A device comprises: a high temperature semiconductor device comprising a first surface, wherein the high temperature semiconductor device comprises an active area and a termination area disposed adjacent to the active area; an inorganic dielectric insulating layer disposed on the first surface, wherein the inorganic dielectric insulating layer fills a volume extending over an entirety of the termination area and comprises a thickness greater than or equal to 25 μm and less than or equal to 500 μm; and an electrical connector connecting the active area of the high temperature semiconductor device to an additional component of the device. | 2021-12-30 |
20210407879 | Heat Sink Configuration for Multi-Chip Module - A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks. | 2021-12-30 |
20210407880 | POWER MODULE FOR OPERATING AN ELECTRIC VEHICLE DRIVE WITH IMPROVED TEMPERATURE DETERMINATION OF THE POWER SEMICONDUCTORS - A power module for operating an electric vehicle drive, comprising: numerous semiconductor components; a heatsink for discharging heat generated by the semiconductor components; a DC link capacitor connected in parallel to the semiconductor components; a DC link line electrically connecting the DC link capacitor to the semiconductor components; wherein the DC link line is at least partially located in a hole formed in the heatsink. | 2021-12-30 |
20210407881 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element having a first main electrode and a second main electrode; a first heat dissipation member and a second heat dissipation member; and a lead frame including a first main terminal connected to the first heat dissipation member and a second main terminal connected to the second main electrode. The second main terminal includes a connection portion connected with the second main electrode, a facing portion extending from the connection portion and facing the first heat dissipation member, and a non-facing portion. The non-facing portion and the first main terminal are arranged in a direction orthogonal to a thickness direction. A side surface of the first main terminal and a side surface of the non-facing portion of the second main terminal face each other. | 2021-12-30 |
20210407882 | SUBSTRATES FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH IMPROVED THERMAL PERFORMANCE AND METHODS FOR MAKING THE SAME - Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate. | 2021-12-30 |
20210407883 | GRAPHITE THIN FILM/SILICON SUBSTRATE LAMINATED ASSEMBLY, PROCESS FOR PRODUCING THE SAME, AND SUBSTRATE FOR ENHANCED HEAT DISCHARGE TYPE ELECTRONIC DEVICES - The invention provides a laminated assembly dedicated to an enhanced heat discharge type electronic device application by providing an enhanced thermal performance to a silicon device. A graphite thin film/silicon substrate laminated assembly is provided by cleaning the surfaces of a smoothed graphite thin film and a silicon substrate under deaeration conditions for activation, thereby bringing them close to each other for spontaneous bonding. In such a laminated assembly wherein the graphite thin film is provided on the silicon substrate, the silicon substrate and graphite thin film come into contact directly via an interface. | 2021-12-30 |
20210407884 | ADDITIVELY MANUFACTURED STRUCTURES FOR HEAT DISSIPATION FROM INTEGRATED CIRCUIT DEVICES - An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof. | 2021-12-30 |
20210407885 | TWO-PACK CURABLE COMPOSITION SET, THERMALLY CONDUCTIVE CURED PRODUCT, AND ELECTRONIC DEVICE - A two-pack curable composition set having: a first agent comprising an organopolysiloxane having a branched structure and having a vinyl group at least at an end or in a side chain, a thermally conductive filler, a silica powder, and a platinum catalyst, and having a viscosity at 25° C. at a shear rate of 10 s | 2021-12-30 |
20210407886 | Semiconductor Package - A semiconductor package is disclosed for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip, a housing lid and thermal-conductive liquid. A chip is disposed on the substrate layer and electrically coupled to the substrate layer. The chip includes at least one through silicon via (TSV). The housing lid is disposed above both the substrate layer and the chip. Also, the housing lid is coupled to the substrate layer at its edge for forming an internal space that encompasses the chip. The thermal-conductive liquid is filled within the internal space. | 2021-12-30 |
20210407887 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package. | 2021-12-30 |
20210407888 | MODULAR MICROCHANNEL THERMAL SOLUTIONS FOR INTEGRATED CIRCUIT DEVICES - A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material. | 2021-12-30 |
20210407889 | THERMAL MANAGEMENT OF GPU-HBM PACKAGE BY MICROCHANNEL INTEGRATED SUBSTRATE - Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device. | 2021-12-30 |
20210407890 | INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures. | 2021-12-30 |
20210407891 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern. | 2021-12-30 |
20210407892 | SEMICONDUCTOR MODULE - A semiconductor module includes: a semiconductor element having a first main electrode and a second main electrode; a first conductive member and a second conductive member connected to the first main electrode and the second main electrode, respectively, and placed to sandwich the semiconductor element; and a main terminal including a first main terminal continuous from the first conductive member and a second main terminal continuous from the second conductive member. The main terminal has a facing portion, a non-facing portion, a first connection portion, and a second connection portion. In a width direction, a formation position of the second connection portion overlaps with a formation position of the first connection portion. | 2021-12-30 |
20210407893 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion. | 2021-12-30 |
20210407894 | SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD - Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area. | 2021-12-30 |
20210407895 | VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES - An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level. | 2021-12-30 |
20210407896 | HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY - According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity. | 2021-12-30 |
20210407897 | PRINTED CIRCUIT BOARD - A printed circuit board includes a first wiring structure including first insulating layers and first wiring layers; a second wiring structure disposed on the first wiring structure and including second insulating layers and second wiring layers; and a third wiring structure disposed on the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer. At least a portion of at least one of the second wiring layers has a fine pitch, relatively finer than those of the first wiring layers and the third wiring layer, wherein at least a portion of one of the first wiring layers is connected to at least a portion of the third wiring layer through a first wiring via, and wherein the first wiring via penetrates at least one of the first insulating layers, the second insulating layers, and the third insulating layer. | 2021-12-30 |
20210407898 | ELECTRONIC COMPONENT AND IMAGE FORMING APPARATUS - An electronic component includes a substrate, an element mounted on a center portion of the substrate, a first terminal portion provided on the substrate at an edge of a first end portion of the substrate as seen in the element, and a second terminal portion provided on the substrate at an edge of a second end portion. The first terminal portion includes a first edge and a second edge in a direction perpendicular to a first direction from the element toward the first end portion and a length of the first edge is different from that of the second edge. The second terminal portion includes a third edge and a fourth edge in the direction and a length of the third edge is different from that of the fourth edge. | 2021-12-30 |
20210407899 | SEMICONDUCTOR MODULE - The present invention is directed to provide a semiconductor module capable of achieving miniaturization and reduced manufacturing cost while suppressing surge voltage generated when switching the semiconductor elements. A semiconductor module includes a negative terminal and a positive terminal. The negative terminal has a negative fastening portion for fastening a negative polarity-side external terminal, a negative connection portion connected to a laminated substrate, and a negative intermediate portion arranged between the negative fastening portion and the negative connection portion. The positive terminal has a positive fastening portion for fastening a positive polarity-side external terminal, positive connection portions connected to the laminated substrate, and a positive intermediate portion facing the negative intermediate portion with a predetermined gap and arranged between the positive fastening portion and the positive connection portions. | 2021-12-30 |
20210407900 | BACKSIDE CONNECTION STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure. | 2021-12-30 |
20210407901 | METHOD FOR LOW-COST, HIGH-BANDWIDTH MONOLITHIC SYSTEM INTEGRATION BEYOND RETICLE LIMIT - A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits. | 2021-12-30 |
20210407902 | HALOGEN TREATMENT FOR NMOS CONTACT RESISTANCE IMPROVEMENT - Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal. | 2021-12-30 |
20210407903 | HIGH-THROUGHPUT ADDITIVELY MANUFACTURED POWER DELIVERY VIAS AND TRACES - An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal. | 2021-12-30 |
20210407904 | PACKAGE COMPONENT, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region. | 2021-12-30 |
20210407905 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer. | 2021-12-30 |
20210407906 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES - A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode. | 2021-12-30 |
20210407907 | MULTI-HEIGHT & MULTI-WIDTH INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT STRUCTURES - Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized. | 2021-12-30 |
20210407908 | MEMORY DEVICE WITH AIR GAPS FOR REDUCING CAPACITIVE COUPLING - The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad. | 2021-12-30 |
20210407909 | INTEGRATED PHOTONICS AND PROCESSOR PACKAGE WITH REDISTRIBUTION LAYER AND EMIB CONNECTOR - Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other processors. Other embodiments may be described and/or claimed. | 2021-12-30 |
20210407910 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component. | 2021-12-30 |
20210407911 | SEMICONDUCTOR PACKAGE AND A PACKAGE-ON-PACKAGE INCLUDING THE SAME - A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level. | 2021-12-30 |
20210407912 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer. | 2021-12-30 |
20210407913 | ROUTING STRUCTURE AND METHOD OF FORMING THE SAME - The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed. | 2021-12-30 |
20210407914 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage. | 2021-12-30 |
20210407915 | PRINTED CIRCUIT BOARD COMPENSATION STRUCTURE FOR HIGH BANDWIDTH AND HIGH DIE-COUNT MEMORY STACKS - A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer. | 2021-12-30 |
20210407916 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench. | 2021-12-30 |
20210407917 | Fabric-Based Items With Electrical Component Arrays - A fabric-based item may include fabric layers and other layers of material. An array of electrical components may be mounted in the fabric-based item. The electrical components may be mounted to a support structure such as a flexible printed circuit. The flexible printed circuit may have a mesh shape formed from an array of openings. Serpentine flexible printed circuit segments may extend between the openings. The electrical components may be light-emitting diodes or other electrical devices. Polymer with light-scattering particles or other materials may cover the electrical components. The flexible printed circuit may be laminated between fabric layers or other layers of material in the fabric-based item. | 2021-12-30 |
20210407918 | PASSIVE COMPONENT EMBEDDED IN AN EMBEDDED TRACE SUBSTRATE (ETS) - Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core. | 2021-12-30 |
20210407919 | HYBRID METALLIZATION AND LAMINATE STRUCTURE - Conventional package problems may be overcome with a hybrid metallization and laminate structure that avoids warpage problems and size reduction problems. One example structure may include a metallization structure directly attached to an active side of a logic die stack in a core substrate (on one or both sides of the substrate) with laminate layers built-up on top of the metallization structures for a symmetrical package structure. | 2021-12-30 |
20210407920 | Semiconductor Devices and Methods of Manufacture - A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. An opening is formed within metallization layers over the semiconductor substrate and the semiconductor substrate, and an encapsulant is placed to fill the opening. Once the encapsulant is placed, the semiconductor substrate is singulated to separate the devices. By recessing the material of the metallization layers and forming the opening, delamination damage may be reduced or eliminated. | 2021-12-30 |
20210407921 | SUPPORT FRAME STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole. | 2021-12-30 |
20210407922 | PACKAGE STRUCTURE OF INTEGRATED PASSIVE DEVICE AND MANUFACTURING METHOD THEREOF, AND SUBSTRATE - Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar. | 2021-12-30 |
20210407923 | SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other. | 2021-12-30 |
20210407924 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad. | 2021-12-30 |
20210407925 | HYBRID CONDUCTIVE STRUCTURES - The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact. | 2021-12-30 |
20210407926 | SEMICONDUCTOR MODULE - A semiconductor module includes a main board and external terminals. A package substrate includes a core insulation layer, a conductive pattern disposed in the core insulation layer and electrically connected with the external terminals, an upper insulation pattern and a lower insulation pattern. At least one semiconductor chip is disposed on an upper surface of the package substrate and is electrically connected with the conductive pattern. A shielding plate is disposed on a molding member and lateral side surfaces of the package substrate and shields electromagnetic interference (EMI) emitted from the semiconductor chip. A shielding fence extends from an edge portion of a lower surface of the lower insulation pattern and directly contacts the upper surface of the main board. The shielding fence surrounds the external terminals and shields EMI emitted from the external terminals. A reinforcing member increases a strength of the shielding fence. | 2021-12-30 |
20210407927 | MULTI-COMPONENT MODULES (MCMs) INCLUDING CONFIGURABLE ELECTRO-MAGNETIC ISOLATION (EMI) SHIELD STRUCTURES, AND RELATED METHODS - Multi-component modules (MCMs) including configurable electromagnetic interference (EMI) shield structures, and related methods are disclosed. An EMI shield enclosing an IC or another electrical component in an MCM can protect other components within the MCM from EMI generated by the enclosed component. The EMI shield also protects the enclosed component from the EMI generated by other electrical components. An EMI shield with side-wall structures, in which vertical conductors supported by a wall medium electrically couple a lid of the EMI shield to a ground layer in a substrate, provides configurable EMI protection in an MCM. The EMI shield may also be employed to increase heat dissipation. The side-wall structures of the EMI shield are disposed on one or more sides of an electrical component and are configurable to provide a desired level of EMI isolation. | 2021-12-30 |
20210407928 | QUANTUM DEVICE AND METHOD OF MANUFACTURING THE SAME - A quantum device ( | 2021-12-30 |
20210407929 | SEMICONDUCTOR PACKAGE - A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip. The stack of second semiconductor chips has a lateral footprint greater than the lateral area of the first portion of the surface of the substrate so that at least a portion of the stack of second semiconductor chips overhangs at least one sidewall of at least one of the spacer and the first semiconductor chip, which extend between the stack of second semiconductor chips and the surface of the substrate. | 2021-12-30 |
20210407930 | SEMICONDUCTOR DEVICES COMPRISING STEPS - A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices. | 2021-12-30 |
20210407931 | CHIP ON FILM STRUCTURE AND DISPLAY DEVICE - A chip on film structure and a display device including chip on film structure, the chip on film structure including a film substrate including a body area, a plurality of traces, and a bonding area at opposite ends of the film substrate; at least one chip, the chip disposed in the body area through bonding and electrically connected to the display panel through the plurality of traces and the bonding area; and a guiding member disposed at one end of the film substrate connected to the display panel and covering the bonding area. | 2021-12-30 |
20210407932 | MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES - Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate. | 2021-12-30 |
20210407933 | ARRAY SUBSTRATE, DISPLAY PANEL, AND MANUFACTURING METHOD OF ARRAY SUBSTRATE - The present disclosure provides an array substrate, a display panel, and a manufacturing method of the array substrate. The display panel includes the array substrate. The array substrate includes a planarization layer provided with a groove surrounding a display area in a non-display area, the groove includes a bottom surface and two side inclined planes, and an included angle (taper angle) between the bottom surface and the side inclined planes ranges from 30° to 45°. When manufacturing the groove, a plurality of side inclined sub-planes are manufactured at intervals and connected to each other to form the side inclined planes. | 2021-12-30 |
20210407934 | COMPONENTS FOR MILLIMETER-WAVE COMMUNICATION - Disclosed herein are components for millimeter-wave communication, as well as related methods and systems. | 2021-12-30 |
20210407935 | SEMICONDUCTOR TRANSISTORS SUITABLE FOR RADIO-FREQUENCY APPLICATIONS - A semiconductor device is provided, which includes a substrate, an active region, source and drain regions, first and second gate structures, and a contact structure. The active region is arranged over the substrate and the source and drain regions are arranged in the active region. The first and second gate structures abut upon the active region. The first gate structure is arranged between the source and drain regions and the second gate structure is arranged between the first gate structure and the drain region. The contact structure is arranged over the active region electrically coupling the first gate structure. | 2021-12-30 |
20210407936 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREFOR - A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad ( | 2021-12-30 |
20210407937 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer that has a main surface, an electrode pad that is formed on the main surface, a rewiring that has a first wiring surface connected to the electrode pad and a second wiring surface positioned on a side opposite to the first wiring surface and being roughened, the rewiring being formed on the main surface such as to be drawn out to a region outside the electrode pad, and a resin that covers the second wiring surface on the main surface and that seals the rewiring. | 2021-12-30 |
20210407938 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a first chip including a first semiconductor substrate, a first semiconductor element on the first semiconductor substrate, a first wiring layer to be connected to the first semiconductor element, and a first pad to be connected to the first wiring layer, and a second chip including a second semiconductor substrate, a second semiconductor element on the second semiconductor substrate, a second wiring layer to be connected to the second semiconductor element, and a second pad to be connected to the second wiring layer and joined to the first pad. At least one of the first pad and the second pad includes a first metal layer to be joined to the other pad, a second metal layer having a coefficient of thermal expansion higher than that of the first metal layer, and a barrier metal layer between the first metal layer and the second metal layer. | 2021-12-30 |
20210407939 | FLIP-CHIP FLEXIBLE UNDER BUMP METALLIZATION SIZE - Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection. | 2021-12-30 |
20210407940 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad. | 2021-12-30 |
20210407941 | INTEGRATED DEVICE PACKAGES - In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive. | 2021-12-30 |
20210407942 | Packaged Semiconductor Device and Method of Forming Thereof - A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate. | 2021-12-30 |
20210407943 | BONDED MEMORY DEVICES AND METHODS OF MAKING THE SAME - A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure. | 2021-12-30 |
20210407944 | SEMICONDUCTOR DEVICE ASSEMBLY WITH SACRIFICIAL PILLARS AND METHODS OF MANUFACTURING SACRIFICIAL PILLARS - Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die. | 2021-12-30 |
20210407945 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode. | 2021-12-30 |
20210407946 | METHOD OF MANUFACTURING CIRCUIT STRUCTURE - Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided. | 2021-12-30 |
20210407947 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride. | 2021-12-30 |
20210407948 | INTEGRATED CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An integrated circuit chip includes a substrate on which a standard cell is disposed. The integrated circuit chip includes a plurality of power bumps including a plurality of first power bumps and a plurality of second power bumps, the plurality of power bumps. disposed to have a staggered arrangement in a central region of one surface of the integrated circuit chip, and connected to provide power to the standard cell; a first metal wiring disposed below the plurality of first power bumps and electrically connected to the plurality of first power bumps, at least a part of the first metal wiring overlapping the plurality of first power bumps from a plan view; and a second metal wiring horizontally separated from the first metal wiring, disposed below the plurality of second power bumps, and electrically connected to the plurality of second power bumps, at least a part of the second metal wiring overlapping the plurality of second power bumps from the plan view. The plurality of first power bumps are disposed along a first line extending in a first direction parallel to a first diagonal direction of the integrated circuit chip, and along a second line extending in a second direction parallel to a second diagonal direction of the integrated circuit chip different from the first diagonal direction, the first diagonal direction and second diagonal direction being diagonal with respect to edges of the integrated circuit chip, and the plurality of second power bumps are disposed along a third line spaced apart from the first line and extending in the first direction, and along a fourth line spaced apart from the second line and extending in the second direction. | 2021-12-30 |
20210407949 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other. | 2021-12-30 |
20210407950 | VIA WIRING FORMATION SUBSTRATE, MANUFACTURING METHOD FOR VIA WIRING FORMATION SUBSTRATE, AND SEMICONDUCTOR DEVICE MOUNTING COMPONENT - A via wiring formation substrate for mounting at least one semiconductor chip, the substrate including a support substrate, a releasable adhesive layer provided on the support substrate, a first insulating layer provided on the releasable adhesive layer, and a second insulating layer laminated on the first insulating layer, wherein the first insulating layer and the second insulating layer are provided with a via wiring formation via, the via wiring formation via enabling formation of via wirings which respectively correspond to a plurality of connection terminals of the semiconductor chip and which respectively connect the plurality of connection terminals, such that the via wiring formation via penetrates only through the first insulating layer and the second insulating layer without misalignment. | 2021-12-30 |
20210407951 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device. | 2021-12-30 |
20210407952 | LAMINATE - The present invention is a laminate including a base sheet and a metal particle-containing layer laminated on the base sheet, and including metal particles. The base sheet has a contact surface in contact with the metal particle-containing layer, and a Young's modulus of the base sheet at 23° C., which is obtained by measuring the contact surface using a nano-indentation method, is 0.01 to 10 GPa. | 2021-12-30 |
20210407953 | SOLDER MATERIAL FOR SEMICONDUCTOR DEVICE - A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, an element selected from the group consisting of: more than 0 and 1.0% by mass or less of Si, more than 0 and 0.1% by mass or less of V, 0.001 to 0.1% by mass of Ge, 0.001 to 0.1% by mass of P, and more than 0 and 1.2% by mass or less of Cu, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame. | 2021-12-30 |
20210407954 | SEMICONDUCTOR DEVICE - Semiconductor device A | 2021-12-30 |
20210407955 | SEMICONDUCTOR DEVICE WITH A LASER-CONNECTED TERMINAL - A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more. | 2021-12-30 |
20210407956 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate including a first substrate channel pad and a second substrate channel pad, a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip channel pad, and each of the second semiconductor chips includes a second chip channel pad, first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another, second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another. | 2021-12-30 |
20210407957 | ADHESIVE MEMBER AND DISPLAY DEVICE INCLUDING THE SAME - A display device includes a substrate including a conductive pad, a driving chip facing the substrate and including a conductive bump electrically connected to the conductive pad and an inspection bump which is insulated from the conductive pad, and an adhesive member which is between the conductive pad and the driving chip and connects the conductive pad to the driving chip. The adhesive member includes a first adhesive layer including a conductive ball; and a second adhesive layer facing the first adhesive layer, the second adhesive layer including a first area including a color-changing material, and a second area adjacent to the first area and excluding the color-changing material. | 2021-12-30 |
20210407958 | RADIATIVE HEAT COLLECTIVE BONDER AND GANGBONDER - A radiative heat collective bonder or gangbonder for packaging a semiconductor die stack is provided. The bonder generally includes a shroud positioned at least partially around the die stack and a radiative heat source positioned inward of the shroud and configured to emit a radiative heat flux in a direction away from the shroud. The bonder may further include a bondhead configured to contact the backside of the topmost die in the die stack and optionally include another bondhead configured to contact a substrate beneath the die stack. The radiative heat source may be configured to direct the radiative heat flux to at least a portion of the die stack to reduce a vertical temperature gradient in the die stack. One or both of the bondheads may be configured to concurrently direct a conductive heat flux into the die stack. | 2021-12-30 |
20210407959 | DIE-TO-WAFER BONDING UTILIZING MICRO-TRANSFER PRINTING - Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer. | 2021-12-30 |
20210407960 | ELECTRICAL CONNECTING STRUCTURE HAVING NANO-TWINS COPPER - Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer. | 2021-12-30 |
20210407961 | METHOD FOR TRANSFERRING CHIPS - A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state. | 2021-12-30 |
20210407962 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer. | 2021-12-30 |
20210407963 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space. | 2021-12-30 |
20210407964 | SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH IMPROVED THERMAL PERFORMANCE AND METHODS FOR MAKING THE SAME - Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies. | 2021-12-30 |
20210407965 | SEMICONDUCTOR PACKAGE HAVING A REINFORCEMENT LAYER - A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%. | 2021-12-30 |
20210407966 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a processor die, a storage module and a package substrate. The storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. The package substrate is on which the processor die and the storage module are disposed. | 2021-12-30 |
20210407967 | SLOPED INTERCONNECTOR FOR STACKED DIE PACKAGE - A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate. | 2021-12-30 |
20210407968 | DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS - A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer. | 2021-12-30 |
20210407969 | MINI LED BACKLIGHT PANEL AND BACKLIGHT MODULE - A mini light emitting diode (LED) backlight panel is provided, which includes a plurality of backlight sub-panels in a docking way. A light-filling region is disposed between the arbitrary adjacent two backlight sub-panels. Fluorescent powder or quantum dots are filled in the light-filling region. The mini LED backlight panel emits light to excite material of the light-filling region to emit light. Secondly, adopting design solutions of large and small light emitting angles in mixed arrangement on different heights of the light emitting surfaces in the mini LED backlight panel, improving brightness on the splicing position, thereby improving quality of light emitted from the mini LED backlight panel, and meanwhile is advantageous for an ultra-thin design of the backlight module. | 2021-12-30 |
20210407970 | PIXEL AND DISPLAY DEVICE HAVING THE SAME - A pixel may include a pixel circuit layer including at least one transistor and a first electrode disposed on a substrate, and a first insulating layer disposed on the at least one transistor and the first electrode, and a display element layer disposed on the pixel circuit layer, the display element layer including a second electrode electrically connected to the at least one transistor, and a plurality of light emitting elements electrically connected to each of the first and second electrodes. The first electrode and the second electrode may be disposed on different layers and may be spaced apart from each other. The plurality of light emitting elements may overlap the first and second electrodes in a plan view and a cross-sectional view. | 2021-12-30 |
20210407971 | SEMICONDUCTOR PACKAGE AND STACKED PACKAGE MODULE INCLUDING THE SAME - A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad. | 2021-12-30 |
20210407972 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member. | 2021-12-30 |
20210407973 | SYSTEM-IN-PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF - A system-in-package structure includes a carrier plate, a chip, a passive component, a first plastic package body and a second plastic package body. The chip is disposed on a first surface of the carrier plate. The passive component is disposed on a second surface of the carrier plate. The first surface of the carrier plate is disposed opposite to the second surface of the carrier plate. The first plastic package body for packaging the chip is formed on the first surface of the carrier plate. A surface of the chip that is away from the carrier plate is exposed to the first plastic package body. The second plastic package body for packaging the passive component is formed on the second surface of the carrier plate. | 2021-12-30 |
20210407974 | SPLICED DISPLAY SCREEN, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A spliced display screen, a manufacturing method thereof, and a display device are provided. The spliced display screen includes at least two display panels. Each of the display panels has a display area and a non-display area, and the display area has a main display area and a flexible display area. In two adjacent display panels, the flexible display area of one of the display panels covers the non-display area of the other one of the display panels, and an edge of the flexible display area of the one of the display panels is seamlessly abutted to an edge of the non-display area of the other one of the display panels. | 2021-12-30 |