52nd week of 2016 patent applcation highlights part 58 |
Patent application number | Title | Published |
20160379968 | HYBRID SUBTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES - Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. | 2016-12-29 |
20160379969 | Patterned Wafer and Method of Making the Same - A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space along a first direction. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. A method for making the patterned wafer is also disclosed. | 2016-12-29 |
20160379970 | DECOUPLING CAPACITOR CELL, CELL-BASED IC, AND PORTABLE DEVICE - A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring. | 2016-12-29 |
20160379971 | FINFET WITH ESD PROTECTION - In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure. | 2016-12-29 |
20160379972 | ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE - Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion. | 2016-12-29 |
20160379973 | ULTRASONIC TRANSDUCERS IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) WAFERS AND RELATED APPARATUS AND METHODS - Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer. | 2016-12-29 |
20160379974 | MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR - A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty. | 2016-12-29 |
20160379975 | LATERAL BIPOLAR SENSOR WITH SENSING SIGNAL AMPLIFICATION - An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate. | 2016-12-29 |
20160379976 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a first fin-type pattern and a second fin-type pattern formed abreast in a lengthwise direction, a first trench formed between the first fin-type pattern and the second fin-type pattern, a field insulating film partially filling the first trench, an interlayer insulating film on the field insulating film, an insulating line pattern, and a conductive pattern. An upper surface of the field insulating film is lower than an upper surface of the first fin-type pattern and an upper surface of the second fin-type pattern. The interlayer insulating film covers the first fin-type pattern and the second fin-type pattern, and includes a second trench exposing the upper surface of the field insulating film. The second trench includes an upper portion and a lower portion. The insulating line pattern fills the lower portion of the second trench, and the conductive pattern fills the upper portion of the second trench. | 2016-12-29 |
20160379977 | FIN FIELD EFFECT TRANSISTOR - A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface. | 2016-12-29 |
20160379978 | SEMICONDUCTOR DEVICE AND FABRICATING THE SAME - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 2016-12-29 |
20160379979 | INCLUDING LOW AND HIGH-VOLTAGE CMOS DEVICES IN CMOS PROCESS - A device includes a substrate, a deep well, a first well, and a second well. The deep well is formed in the substrate. The first well includes a first portion formed on the deep well and a second portion formed in the substrate. The second well is formed partially on the deep well. A first separator structure is formed on the deep well to isolate the first portion of the first well from the second well, and a second separator structure is formed on the substrate to isolate the second well and a second portion of the first well. | 2016-12-29 |
20160379980 | LOW NOISE AND HIGH PERFORMANCE LSI DEVICE - In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied. | 2016-12-29 |
20160379981 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS WITH SUPPRESSED DOPANT DIFFUSION - A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins. | 2016-12-29 |
20160379982 | Integrated Circuit Device and Method of Manufacturing the Same - An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The first-fin-type active region protrudes from a substrate in a first region of the substrate and has a first width in a first direction. The second-fin-type active region protrudes from the substrate in a second region of the substrate and has a second width in the first direction. The second width is less than the first width. The inter-region stepped portion is formed at an interface between the first region and the second region in a bottom surface, which is a portion of the substrate between the first-fin-type active region and the second-fin-type active region. | 2016-12-29 |
20160379983 | INTEGRATED CIRCUIT STRUCTURE - A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path. | 2016-12-29 |
20160379984 | Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor - A volatile memory array using vertical thyristors with gates, NMOS or PMOS, in trenches adjacent the thyristors is disclosed together with methods of fabricating the array. | 2016-12-29 |
20160379985 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an upper mold layer using a dry etching process, forming a lower electrode in the storage node hole, patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer, removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process, and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode. An etch rate of the bowing prevention layer may be substantially equal to an etch rate of the upper support layer during the dry etching process. An etch rate of the bowing prevention layer may be higher than an etch rate of the upper support layer during the first wet etching process. | 2016-12-29 |
20160379986 | REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM - A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor. | 2016-12-29 |
20160379987 | STRUCTURE WITH EMEDDED EFS3 AND FINFET DEVICE - The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device. | 2016-12-29 |
20160379988 | METHOD FOR MANUFACTURING A FINGER TRENCH CAPACITOR WITH A SPLIT-GATE FLASH MEMORY CELL - A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region. | 2016-12-29 |
20160379989 | DIFFERENTIAL ETCH OF METAL OXIDE BLOCKING DIELECTRIC LAYER FOR THREE-DIMENSIONAL MEMORY DEVICES - A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion. | 2016-12-29 |
20160379990 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer. | 2016-12-29 |
20160379991 | Semiconductor Chip and Method for Manufacturing the Same - A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size. | 2016-12-29 |
20160379992 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2016-12-29 |
20160379993 | TUNABLE CAPACITOR FOR FDSOI APPLICATIONS - The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region. | 2016-12-29 |
20160379994 | SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS - A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide. | 2016-12-29 |
20160379995 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin-film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate comprises an element lamination substrate, a passivation layer, and pixel electrode layer. The passivation layer is disposed on the element lamination substrate, and is provided with at least one via hole and a groove array, wherein the groove array includes at least two grooves. The pixel electrode layer is disposed on the passivation layer and inside the grooves, wherein the pixel electrode layer is connected to a second signal line layer through the via hole. This can reduce the cost of manufacturing the TFT array substrate, and increase the manufacturing efficiency of the TFT array substrate. | 2016-12-29 |
20160379996 | Display Substrate and Manufacturing Method Thereof, and Display Device - The present invention provides a display substrate and a manufacturing method thereof, and a display device. The display substrate comprises a base substrate, and gate lines, data lines, a gate driving circuit and a source driving circuit on the base substrate, the gate lines and the data lines define pixel units, the pixel unit comprises a thin film transistor and a pixel electrode, the data lines are connected to the source driving circuit, the display substrate further comprising gate line connection wires on the base substrate, the gate lines are connected to the gate driving circuit through the gate line connection wires, the gate driving circuit and the source driving circuit are located at edge positions on the base substrate in an extending direction of the data lines, and they are opposite to each other. The widths of the bezel in the extending direction of the gate lines are reduced. | 2016-12-29 |
20160379997 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface. | 2016-12-29 |
20160379998 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the display device includes a substrate, a first signal line formed over the substrate and a first insulating layer formed over the substrate and the first signal line. The display device also includes a second signal line formed over the first insulating layer and including an overlapping area that overlaps the first signal line, a second insulating layer formed over the second signal line and having a via hole that exposes at least a part of the overlapping area. The display device further includes an auxiliary wiring layer covering the via hole and connected to the overlapping area through the via hole. | 2016-12-29 |
20160379999 | HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE - Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation. | 2016-12-29 |
20160380000 | Semiconductor Device Structure With 110-PFET and 111-NFET Curent Flow Direction - A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned. | 2016-12-29 |
20160380001 | SELECTIVE OXIDATION FOR MAKING RELAXED SILICON GERMANIUM ON INSULATOR STRUCTURES - Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a semiconductor device includes forming a crystalline buffer layer on a substrate, forming an epitaxial semiconductor layer on the crystalline buffer layer, patterning the epitaxial semiconductor layer to form a patterned epitaxial semiconductor layer, and oxidizing a surface region of the crystalline buffer layer selective to the patterned epitaxial semiconductor layer to convert the surface region of the crystalline buffer layer to an insulating layer. The insulating layer insulates the patterned epitaxial semiconductor layer from the crystalline buffer layer. In one example structure, the substrate is a silicon substrate, the crystalline buffer layer is formed of germanium, the epitaxial semiconductor layer is formed of silicon-germanium, and the insulating layer is formed of amorphous germanium-oxide. | 2016-12-29 |
20160380002 | CONTACT FORMATION TO 3D MONOLITHIC STACKED FINFETS - A first gate structure straddles one end of a staircase fin stack that contains a first semiconductor material fin, an insulator fin, and a second semiconductor material fin, a second gate structure straddles a portion of the staircase fin stack, a third gate structure straddles another end of the staircase fin stack, and a fourth gate structure straddles a portion of only the first semiconductor fin. A first contact structure is between the first and second gate structures, a second contact structure is between the second and third gate structures, and a third contact structure is between the third and fourth gate structures. The first contact structure has a contact metal that contacts the first and second semiconductor material fins. The second contact structure has a contact metal that contacts only the second semiconductor material fin, and the third contact structure has a contact metal that contacts only the first semiconductor fin. | 2016-12-29 |
20160380003 | GATE ALL-AROUND FINFET DEVICE AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer. | 2016-12-29 |
20160380004 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor substrate includes a base substrate, a first metallic layer including a gate electrode of a thin film transistor and an island electrode spaced apart from the gate electrode on the base substrate, a semiconductor layer of which a portion thereof overlaps the gate electrode of the first metallic layer, and a second metallic layer including a source electrode and a drain electrode of the thin film transistor which are spaced apart from each other on the portion of the semiconductor layer. The source electrode of the thin film transistor overlaps the island electrode. | 2016-12-29 |
20160380005 | ARRAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE - The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided. | 2016-12-29 |
20160380006 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device ( | 2016-12-29 |
20160380007 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor overlapping with the first transistor, a capacitor overlapping with the second transistor, and a first wiring electrically connected to the capacitor. The first wiring includes a region overlapping with an electrode of the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected to one another. A channel of the first transistor includes a single crystal semiconductor. A channel of the second transistor includes an oxide semiconductor. | 2016-12-29 |
20160380008 | BACKPLANE FOR DISPLAY APPARATUS - A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area. | 2016-12-29 |
20160380009 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) array substrate and its manufacturing method are disclosed. The TFT array substrate includes a component assembly layer, a passivation layer and a pixel electrode layer. The passivation layer is disposed on the component assembly layer, and a hole and a first recess are provided on the passivation layer. The pixel electrode layer is disposed on the passivation layer and inside the first recess, and the pixel electrode layer is connected with the second signal line layer by the hole. The present invention can reduce the manufacturing cost and improve the manufacturing efficiency. | 2016-12-29 |
20160380010 | FABRICATION METHOD OF PIXEL STRUCTURE - A fabrication method of a pixel structure is provided. The fabrication method includes: forming a gate electrode, a gate insulating layer, an active layer, a pixel electrode layer and a source-drain electrode layer on a substrate, and etching the source-drain electrode layer by using a photoresist pattern to form a source electrode and a drain electrode; ashing the photoresist pattern, so as to align edges of the ashed photoresist pattern with edges of the source electrode and the drain electrode; etching a silicon oxide generated in ashing the photoresist pattern; and etching a semiconductor layer between the source electrode and the drain electrode by an etching process to form a channel. The fabrication method can remove indium-containing material remained on both sides of a source electrode and a drain electrode, and can resolve a problem that a width of a channel between the source electrode and the drain electrode is small. | 2016-12-29 |
20160380011 | METHOD OF FABRICATING DISPLAY DEVICE - A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer. | 2016-12-29 |
20160380012 | PHOTO SENSOR MODULE - The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer. | 2016-12-29 |
20160380013 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid-state image sensing element including a transistor with stable electrical characteristics (e.g., significantly low off-state current) is provided. Two different element layers (an element layer including an oxide semiconductor layer and an element layer including a photodiode) are stacked over a semiconductor substrate provided with a driver circuit such as an amplifier circuit, so that the area occupied by a photodiode is secured. A transistor including an oxide semiconductor layer in a channel formation region is used as a transistor electrically connected to the photodiode, which leads to lower power consumption of a semiconductor device. | 2016-12-29 |
20160380014 | Thermal Imaging Device - A thermal imaging device comprises a focal plane array disposed on a focal plane substrate. The focal plane array comprises a plurality of pixels grouped into sub-arrays of pixels. The device also comprises a lens array comprising a plurality of lenslets. Each of the lenslets is arranged to focus infrared rays on a respective one of the sub-arrays of pixels. The focal plane array is enclosed in a vacuum in a space between the lens array and the focal plane substrate, and a readout circuit is electrically connected to the pixels. The thermal imaging device has a small form factor and low cost while maintaining adequate performance, enabling expanded usage of thermal imaging (e.g., in security, surveillance, first responder, defense and/or automotive applications). | 2016-12-29 |
20160380015 | MOLDED SEMICONDUCTOR PACKAGE WITH SNAP LID - An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window is exposed through the aperture. A lens is supported in a threaded lens support. The threaded lens support is threaded into the aperture of the lens holder extension portion. The lens is readily adjusted relative to the image sensor by rotating the lens support. | 2016-12-29 |
20160380016 | BACKSIDE ILLUMINATION IMAGE SENSOR AND IMAGE-CAPTURING DEVICE - A backside illumination image sensor that includes a semiconductor substrate with a plurality of photoelectric conversion elements and a read circuit formed on a front surface side of the semiconductor substrate, and captures an image by outputting, via the read circuit, electrical signals generated as incident light having reached a back surface side of the semiconductor substrate is received at the photoelectric conversion elements includes: a light shielding film formed on a side where incident light enters the photoelectric conversion elements, with an opening formed therein in correspondence to each photoelectric conversion element; and an on-chip lens formed at a position set apart from the light shielding film by a predetermined distance in correspondence to each photoelectric conversion element. The light shielding film and an exit pupil plane of the image forming optical system achieve a conjugate relation to each other with regard to the on-chip lens. | 2016-12-29 |
20160380017 | METHOD OF MANUFACTURING A PLURALITY OF ISLAND-SHAPED DIPOLES HAVING SELF-ALIGNED ELECTRODES - An electronic component includes a plurality of dipoles, each comprising an island solid with a base, a first electrode arranged at the top of the island and a second electrode arranged on the base. Its manufacturing includes forming, on the base, a layer of a material capable of being etched by means of a predetermined isotropic etching, forming, over the layer of material, solid patterns made of electrically-conductive material and inert to said etching, applying the isotropic etching of the thickness of material between said solid patterns to form islands totally overlooked by said solid patterns, and depositing electrically-conductive material on top of and between the islands to form the first and second electrodes of the dipoles. | 2016-12-29 |
20160380018 | Method Of Making Low Profile Sensor Package With Cooling Feature - A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate. | 2016-12-29 |
20160380019 | ARRAY SUBSTRATE OF X-RAY SENSOR AND METHOD FOR MANUFACTURING THE SAME - An array substrate of an X-ray sensor and a method for manufacturing the same are provided, the method comprising a step of forming a thin-film transistor element and a photodiode sensor element, wherein the step of forming the thin-film transistor element comprises: forming a gate electrode on an base substrate by a mask process; depositing a gate insulating layer on the base substrate on which the gate electrode is formed; the step of forming the photodiode sensor element comprises: forming an ohmic contact layer on the base substrate through the same mask process while forming the gate electrode; forming a semiconductor layer and a transparent electrode through a mask process on the substrate on which the ohmic contact layer is formed; depositing the gate insulating layer on the base substrate on which the semiconductor layer and the transparent electrode are formed while depositing the gate insulating layer on the base substrate on which the gate electrode is formed. A gate pattern and an ohmic contact layer are formed through the same mask process, and a passivation layer substitutes a channel blocking layer to reduce the number of the mask processes and simplify the manufacturing process and improve throughput and yield of the product. | 2016-12-29 |
20160380020 | PHOTODETECTOR AND METHOD FOR MANUFACTURING PHOTODETECTOR - According to an embodiment, a photodetector includes a photo detection layer, light conversion members, and a first member. The photo detection layer includes, on a light incident surface, plural pixel regions and a surrounding region. The pixel region holds a photo detection element to detect the light. The surrounding region is a region other than the pixel regions on the light incident surface. The light conversion members are arranged to oppose the pixel regions in the photo detection layer and convert radiation to the light. Each light conversion member includes a bottom surface opposing the pixel region in the photo detection layer, a top surface opposing the bottom surface, and a lateral surface connecting the bottom and top surfaces. The first member is disposed on a portion of the surrounding region on the light incident surface and covers a portion of the lateral surface of the light conversion member. | 2016-12-29 |
20160380021 | RADIATION DETECTING DEVICE AND METHOD FOR MANUFACTURING RADIATION DETECTING DEVICE - In a radiation detecting device, a groove portion is provided in a sealing region on a photoelectric conversion substrate. The groove portion is provided in the vicinity of a phosphor layer formed on the photoelectric conversion substrate or along an outer peripheral side thereof. A moisture-proof protective layer is provided to cover the phosphor layer and the sealing region through an adhesive layer. The adhesive layer is cured when in a flowable state to function as an adhesive. In a case where the moisture-proof protective layer is adhered, the adhesive layer enters a flowable state, and thus, the adhesive layer flows into the groove portion and fills at least a part of the inside of the groove portion. | 2016-12-29 |
20160380022 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, X-RAY FLAT PANEL DETECTOR, IMAGE PICKUP SYSTEM - An array substrate and manufacturing method thereof, an X-ray flat panel detector and an image pickup system are provided. The array substrate is divided into a plurality of detection units, and each of the detection units has a first electrode ( | 2016-12-29 |
20160380023 | SEMICONDUCTOR OPTICAL DEVICE INTEGRATING PHOTODIODE WITH OPTICAL WAVEGUIDE AND METHOD OF FORMING THE SAME - A semiconductor optical device that integrates photodiodes (PDs) and optical waveguides coupling with the PDs and a method of forming the semiconductor optical device are disclosed. The optical waveguides in a portion in the lower cladding layer thereof provides a modified layer that forms a conduction barrier of the lower cladding layer. The modified layer is formed by converting the conduction type thereof or implanting protons therein. The modified layer prevents the electrical coupling between PDs through the waveguides. | 2016-12-29 |
20160380024 | IMAGE SENSOR CHIP PACKAGE AND FABRICATING METHOD THEREOF - A method for fabricating an image sensor chip package begins at providing a wafer, which includes forming a plurality of image sensor components on a substrate, forming a plurality of spacers on the substrate for separating the image sensor components, and disposing a transparent plate on the spacers. The method further includes forming a plurality of stress notches on the transparent plate. After the stress notches are formed, the transparent plate is pressed and the substrate is cut at the second chambers. The transparent plate is broken along the stress notches. | 2016-12-29 |
20160380025 | INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS - An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced. | 2016-12-29 |
20160380026 | PLANAR QUBITS HAVING INCREASED COHERENCE TIMES - An interdigitated capacitor includes a substrate and a pair of comb-like electrodes both formed on the semiconductor substrate and horizontally arranged thereon, each of the pair of comb-like electrodes including finger electrodes having a curved profile. | 2016-12-29 |
20160380027 | INJECTION PILLAR DEFINITION FOR LINE MRAM BY A SELF-ALIGNED SIDEWALL TRANSFER - A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns. | 2016-12-29 |
20160380028 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal. | 2016-12-29 |
20160380029 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, the second magnetic layer containing a material with a composition (lR | 2016-12-29 |
20160380030 | RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE - The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material. | 2016-12-29 |
20160380031 | MULTIPLE CONDUCTIVE LAYER TFT - A multiple layer pixel architecture for an active matrix display is provided having a common bus line on a metal level separate from that on which the gate electrodes of the thin-film transistors (TFTs) are formed. A multilayer electronic structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction. | 2016-12-29 |
20160380032 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes at least one first pixel configured to sense light in a visible light wavelength spectrum and a second pixel configured to sense light in an infrared light wavelength spectrum. The second pixel includes a first photoelectric device defined in the second pixel. The first photoelectric device includes an infrared light absorption layer between a first electrode and a second electrode and configured to selectively absorb light in an infrared spectrum. The second pixel may be configured to compensate the luminance sensitivity of the image sensor. The first and second pixels may be included in a unit pixel group. The image sensor may include an array of multiple unit pixel groups arranged in one or more rows and one or more columns. | 2016-12-29 |
20160380033 | FOLDABLE DISPLAY - A foldable display device according to one or more exemplary embodiments of the present invention includes: a first supporting member; a second supporting member coupled to the first supporting member and configured to be rotated with respect to the first supporting member; an ultra-elastic sheet adhered to the first supporting member and the second supporting member; and a display module adhered to the ultra-elastic sheet. | 2016-12-29 |
20160380034 | DISPLAY APPARATUS - A display apparatus comprising an anisotropic absorption layer and a display panel is disclosed. The anisotropic absorption layer is arranged at light-emitting side of the display panel. A predefined angle is formed between an absorption axis of the anisotropic absorption layer and a normal of the display panel. The anisotropic absorption layer is adapted to absorb ambient lights and transmit display lights from the display panel. The anisotropic absorption layer has a high absorptance to the ambient lights and a high transmittance to the display lights, such that the display apparatus can reduce influence of the ambient lights and improve energy usage. | 2016-12-29 |
20160380035 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Provided is an organic light emitting display device including at least two organic light emitting elements disposed adjacent to each other, respectively including an anode, an organic light emitting unit, and a cathode, and sharing at least one common layer in the organic light emitting unit. The at least one common layer includes a characteristic degradation area that reduces or minimizes an amount of leakage current generated between the at least two organic light emitting elements. | 2016-12-29 |
20160380036 | ORGANIC LIGHT EMITTING DISPLAY DEVICES - An organic light emitting display device includes a plurality of first electrodes, a pixel defining layer, a first intermediate layer, a fluorine-containing layer, an emitting layer and a second electrode. The first electrodes are spaced apart from each other on a substrate. The pixel defining layer is disposed on the substrate. The pixel defining layer partially exposes the first electrodes. The first intermediate layer is disposed on the substrate, the pixel defining layer and the exposed first electrodes. The fluorine-containing layer is formed on a portion of the first intermediate layer overlapping an upper surface of the pixel defining layer. The fluorine-containing layer includes fluorine diffused from the pixel defining layer or the first intermediate layer. The emitting layer is at least partially disposed on a portion of the first intermediate layer not including the fluorine-containing layer thereon. The second electrode is disposed on the emitting layer. | 2016-12-29 |
20160380037 | DISPLAY DEVICE - A display device includes a first pixel and a second pixel arranged in a first or a second direction, each of them has a pixel electrode, a contact hole under the pixel electrode, a bank on the pixel electrode, and an opening provided in the bank and on the pixel electrode. A first imaginary line connecting the center of the contact hole of a first pixel and the center of the contact hole of a second pixel is substantially parallel to the first direction or the second direction, a second imaginary line connecting the center of the opening of the first pixel and the center of the opening of the second pixel is substantially parallel to the first direction or the second direction, and each of straight-line sides of the openings of the plurality of pixels has an angle with respect to both of the first and the second direction. | 2016-12-29 |
20160380038 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device includes: a substrate; a pixel disposed on the substrate and including a first region that displays an image and a second region that transmits external light; a pixel circuit portion disposed in the first region and including at least one thin film transistor and at least one capacitor; a first electrode disposed in the first region and electrically connected with the pixel circuit portion; a pixel-defining layer including a first opening that exposes a portion of the first electrode and a second opening that corresponds to the second region; a second electrode facing the first electrode; an organic emission layer disposed between the first electrode and the second electrode; and a transparent wiring electrically connected with the pixel circuit portion and overlapping the second opening in a plan view. | 2016-12-29 |
20160380039 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display device has a display panel including a first subpixel, a second subpixel, a data line, and sensing lines. The sensing lines may include a vertical sensing line and a horizontal sensing line connected to the vertical sensing line. The horizontal sensing line may be formed of a source/drain metal layer present on the first substrate, and one portion thereof connected to a first electrode of a sensing transistor of the first subpixel and the other portion thereof connected to a first electrode of a sensing transistor of the second subpixel may be positioned in a region intersecting with the data line, and electrically connected by a connection electrode formed of an insulated light blocking layer below the source/drain metal layer present on the first substrate. | 2016-12-29 |
20160380040 | DISPLAY DEVICE - A display device includes a plurality of pixel electrodes, a common electrode disposed from a display area to a peripheral area continuously, a light emitting layer disposed between the plurality of pixel electrodes and the common electrode, and a plurality of auxiliary wirings electrically connecting to the common electrode and located from the display area to the peripheral area continuously. The common electrode includes overlapping areas where the common electrode is in contact with and overlaps the auxiliary wiring in the peripheral area, and includes a thick film portion in at least a portion of the overlapping areas. A thickness of the thick film portion is larger than that of an area other than the overlapping areas. | 2016-12-29 |
20160380041 | Embedded Passive Chip Device and Method of Making the Same - An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed. | 2016-12-29 |
20160380042 | Passive Chip Device and Method of Making the Same - A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed. | 2016-12-29 |
20160380043 | PROCESS-COMPATIBLE DECOUPLING CAPACITOR AND METHOD FOR MAKING THE SAME - Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. | 2016-12-29 |
20160380044 | CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - A capacitor may include a lower electrode structure, a dielectric layer on the lower electrode structure, and an upper electrode on the dielectric layer. The lower electrode structure may include first to third lower electrodes sequentially stacked, a first oxidation barrier pattern structure between the first lower electrode and the second lower electrode, and a second oxidation barrier pattern structure between the second lower electrode and the third lower electrode. The first oxidation barrier pattern structure may include first and second oxidation barrier patterns sequentially stacked on the first lower electrode, and the second oxidation barrier pattern structure may include third and fourth oxidation barrier patterns sequentially stacked on the second lower electrode. | 2016-12-29 |
20160380045 | CRYSTALLINE SEMICONDUCTOR GROWTH ON AMORPHOUS AND POLY-CRYSTALLINE SUBSTRATES - A multilayer semiconductor structure including at least in part a substrate and an III-N film layer. The substrate's constant of thermal expansion being substantially matched to the III-N film's constant of thermal expansion. The multilayer semiconductor structure may also include a crystal matching layer that has a lattice constant that substantially matches the lattice of constant of the III-N film. By not relying on the substrate for lattice matching the III-N film, the multilayer structure allows greater flexibility in the selection of an applicable substrate. | 2016-12-29 |
20160380046 | III-Nitride Power Semiconductor Device - A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only. | 2016-12-29 |
20160380047 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type located on the first electrode, a second semiconductor layer of a second conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on a portion of the second semiconductor layer, a second electrode located in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, the second electrode extending along and around an outer edge of the first semiconductor layer, and spaced from the second semiconductor layer by an insulating film, a wiring located on the third semiconductor layer and connected to the second electrode, and a third electrode connected to the second semiconductor layer and the third semiconductor layer. | 2016-12-29 |
20160380048 | METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR - A method for manufacturing an insulated gate bipolar transistor ( | 2016-12-29 |
20160380049 | COMPOUND FINFET DEVICE INCLUDING OXIDIZED III-V FIN ISOLATOR - A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer. | 2016-12-29 |
20160380050 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided as follows. A first fin-type pattern is disposed on a substrate. A first field insulating film is adjacent to a sidewall of the first fin-type pattern. A second field insulating film is adjacent to a sidewall of the first field insulating film. The first field insulating film is interposed between the first fin-type pattern and the second field insulating film. The second field insulating film comprises a first region and a second region. The first region is closer to the sidewall of the first field insulating film. A height from a bottom of the second field insulating film to an upper surface of the second region is larger than a height from the bottom of the second field insulating film to an upper surface of the first region. | 2016-12-29 |
20160380051 | FINFET DEVICES - FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures. | 2016-12-29 |
20160380052 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer. | 2016-12-29 |
20160380053 | III-V GATE-ALL-AROUND FIELD EFFECT TRANSISTOR USING ASPECT RATIO TRAPPING - A field effect transistor includes a trench in a field dielectric material on a crystalline silicon substrate and source/drain features inside the trench. The field effect transistor further includes a channel feature comprising a III-V material in the trench and spanning between the source/drain features, and gate dielectric layers and a gate feature surrounding a portion of the channel feature. | 2016-12-29 |
20160380054 | NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION - A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material. | 2016-12-29 |
20160380055 | EXTRINSIC BASE DOPING FOR BIPOLAR JUNCTION TRANSISTORS - Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure. | 2016-12-29 |
20160380056 | MULTIPLE GATE FIELD-EFFECT TRANSISTORS HAVING OXYGEN-SCAVENGED GATE STACK - A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric. | 2016-12-29 |
20160380057 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region. The undoped channel region, base dopant region, and threshold voltage setting region are disposed within the semiconductor substrate layer. The undoped channel region is disposed between the source electrode and the drain electrode, and the base dopant region and the threshold voltage setting region extend beneath the source electrode and the drain electrode. The threshold voltage setting region is disposed between the undoped channel region and the base dopant region. | 2016-12-29 |
20160380058 | FINFET DEVICES HAVING SILICON GERMANIUM CHANNEL FIN STRUCTURES WITH UNIFORM THICKNESS - Methods are provided to fabricate semiconductor devices, e.g., FinFET devices, having fin channel structures formed of silicon-germanium alloy layers with uniform thickness. For example, a method includes forming a semiconductor fin structure having sidewalls that define a first width of the semiconductor fins structure, and a hard mask layer disposed on a top surface of the semiconductor fin structure. Portions of the sidewalls are etched to form recessed sidewalls that define a thinned portion, wherein a distance between the recessed sidewalls defines a second width of the thinned portion of the semiconductor fin structure, which is less than the first width. Facetted semiconductor alloy layers are formed on the recessed sidewalls, and then anisotropically etched using the hard mask layer as an etch mask to form planarized semiconductor alloy layers of uniform thickness on the recessed sidewalls of the thinned portion of the semiconductor fin structure. | 2016-12-29 |
20160380059 | ACTIVE AREA DESIGNS FOR SILICON CARBIDE SUPER-JUNCTION POWER DEVICES - The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device. | 2016-12-29 |
20160380060 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME - A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench. | 2016-12-29 |
20160380061 | METHOD FOR MANUFACTURING TERMINATION STRUCTURE OF SEMICONDUCTOR DEVICE - A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided. | 2016-12-29 |
20160380062 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween. | 2016-12-29 |
20160380063 | Method for Producing a Semiconductor Component with Insulated Semiconductor Mesas in a Semiconductor Body - A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer. | 2016-12-29 |
20160380064 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE SAME - A thin film transistor substrate includes: a substrate; and a thin film transistor including a gate electrode on the substrate, an active layer on the gate electrode, and a source electrode and a drain electrode on the active layer. Within the thin film transistor, at least one of the source electrode and the drain electrode defines a plurality of branch electrodes thereof and a main electrode to which the plurality of branch electrodes is commonly connected. Each of the plurality of branch electrodes overlaps the gate electrode. | 2016-12-29 |
20160380065 | SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) - Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods. | 2016-12-29 |
20160380066 | SEMICONDUCTOR DEVICE AND MANUFACUTRING METHOD THEREOF - A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive. | 2016-12-29 |
20160380067 | SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR - Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer. | 2016-12-29 |