52nd week of 2011 patent applcation highlights part 21 |
Patent application number | Title | Published |
20110316582 | Semiconductor integrated circuit including a power controllable region - A semiconductor chip includes a first power supply line and a second power supply line. A first switch is coupled between the first power supply line and the second power supply line, and a second switch is coupled between the first power supply line and the second power supply line. A circuit is coupled to the second power supply line. A first control signal line is coupled to the first switch, and a second control signal line coupled to the second switch. A logic gate is coupled to the first and the second control signal lines and a terminal is coupled to the logic gate to output a signal to an outside of the semiconductor chip. | 2011-12-29 |
20110316583 | APPARATUS AND METHOD FOR OVERRIDE ACCESS TO A SECURED PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register. | 2011-12-29 |
20110316584 | FINGERPRINTED CIRCUITS AND METHODS OF MAKING AND IDENTIFYING THE SAME - A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit. | 2011-12-29 |
20110316585 | Interlock Circuit And Interlock System Including The Same - An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals. | 2011-12-29 |
20110316586 | LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL TRANSLATION USING CAPACITIVE COUPLING - A voltage level translator circuit has a digital logic circuit having a digital logic signal at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. A high-voltage driving circuit has two low-voltage input signals, two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal, two level translators, a first level translator corresponding to the high-side drive signal, and a second level translator corresponding to the low-side drive signal, the level translators including a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. | 2011-12-29 |
20110316587 | Bistable CML Circuit - A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch. | 2011-12-29 |
20110316588 | Resistor-programmable device at low voltage - A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls. | 2011-12-29 |
20110316589 | METHOD OF COMPENSATING CLOCK SKEW, CLOCK SKEW COMPENSATING CIRCUIT FOR REALIZING THE METHOD, AND INPUT/OUTPUT SYSTEM INCLUDING THE CLOCK SKEW COMPENSATING CIRCUIT - A method of compensating clock skew may include generating (2M+1) detected values by applying (2M+1) delay clock signals to (2M+1) pieces of delay data, wherein M is a natural number, determining a dominant logic value based on a comparison of a number of logic high detected values and a number of logic low detected values from among the (2M+1) detected values, determining a median delay time based on a number of the (2M+1) detected values having the dominant logic value, and adjusting a phase of a clock signal using the median delay time. | 2011-12-29 |
20110316590 | Driver Supporting Multiple Signaling Modes - A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination. | 2011-12-29 |
20110316591 | Spread Spectrum Clock System and Spread Spectrum Clock Generator - A spread spectrum clock generator includes a triangular wave generator, a digital wave modulator, a sigma delta modulator, and a selector. The triangular wave generator transforms one of the input clock signals into an original triangular wave signal, in which the input clock signals have the same frequency and phases different from each other. The digital wave modulator adjusts the waveform of the original triangular wave signal to generate an adjusted triangular wave signal and a first square wave signal according to an inputted control signal. The sigma delta modulator, electrically connected to the digital wave modulator, accumulates magnitude values of the adjusted triangular wave signal to generate a second square wave signal. The selector selects one of the input clock signals as an output clock signal based on voltage levels of the first square wave signal and the second square wave signal. | 2011-12-29 |
20110316592 | REFRESH OPERATION DURING LOW POWER MODE CONFIGURATION - A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation. | 2011-12-29 |
20110316593 | Phase Locked Loop with Startup Oscillator and Primary Oscillator - A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator. | 2011-12-29 |
20110316594 | CHIP INTERFACE - In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal. | 2011-12-29 |
20110316595 | VCO FREQUENCY TEMPERATURE COMPENSATION SYSTEM FOR PLLS - The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input. | 2011-12-29 |
20110316596 | PHASE LOCKING FOR MULTIPLE SERIAL INTERFACES - An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock. In this way, each high speed serial interface loop between the main board and the individual system boards is controllably adjusted in phase, compensating for interconnection path lengths and providing synchronism between the received signal and the common, static-phase, master reference clock which supplies all the main controller board receivers. | 2011-12-29 |
20110316597 | SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY - Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent. | 2011-12-29 |
20110316598 | APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME - A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL. | 2011-12-29 |
20110316599 | MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount. | 2011-12-29 |
20110316600 | Serial Link Receiver and Method Thereof - A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision. | 2011-12-29 |
20110316601 | Method and Device for Delaying Activation Timing of Output Device - A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a first mirror current, delaying an enable signal of the circuit system according to the first mirror current to generate a charging activation signal, providing a charging current according to the charging activation signal, and determining the activation moment of the output device according to the activation current. | 2011-12-29 |
20110316602 | SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING - Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit. | 2011-12-29 |
20110316603 | DUTY COMPENSATION CIRCUIT - A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation. | 2011-12-29 |
20110316604 | INPUT BUFFER CIRCUIT - An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal. | 2011-12-29 |
20110316605 | CIRCUIT APPARATUS AND SYSTEM - A circuit apparatus includes an output circuit that outputs a signal to a host apparatus via a bus, and an output control circuit that controls the output circuit. The output circuit has a first conductive transistor provided between an output node and a first power source node, and a second conductive transistor provided between the output node and a second power source node. In a first output mode, the output control circuit controls one of the first conductive transistor and the second conductive transistor to go to off and controls the other transistor to go to on/off, whereas in a second output mode, the output control circuit controls the first conductive transistor to go to on and the second conductive transistor to go to off or vice versa. | 2011-12-29 |
20110316606 | Power Switch Temperature Control Device and Method - An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled. | 2011-12-29 |
20110316607 | SWITCHING CONTROL CIRCUIT AND SWITCHING POWER SUPPLY CIRCUIT - A switching-control circuit, which causes a first transistor, having an input electrode to be applied with an input voltage and an output electrode connected to an inductor and a diode, to be turned on and kept on for a predetermined time period, includes: a comparison circuit to compare a feedback voltage corresponding to an output voltage with a reference voltage; a detecting circuit to detect a switching period of the first transistor; and a driving circuit to turn off a second transistor connected in parallel to the diode as well as turn on the first transistor to be kept on for the predetermined time period, and thereafter, turn off the first and second transistors, when the feedback voltage becomes lower than the reference voltage, and turn off the first transistor as well as turn on the second transistor, when the switching period becomes longer than a predetermined period. | 2011-12-29 |
20110316608 | SWITCHING ARRAY AND METHODS OF MANUFACTURING AND OPERATION - A switching array includes a plurality of switching elements electrically coupled to each other, each switching element being configured to be switched between conducting and non-conducting states. The switching array also includes at least one parasitic minimizing circuitry electrically coupled to the plurality of switching elements and configured to provide near zero electrical voltage and current across and through each of the plurality of switching elements during switching of the plurality of switching elements between the conducting and non-conducting states. | 2011-12-29 |
20110316609 | BIPOLAR JUNCTION TRANSISTOR TURN ON-OFF POWER CIRCUIT - An on-off power circuit connecting a voltage source to a digital system. The on-off power having a turn-on signal source, a control bipolar junction transistor, a switching bipolar junction transistor, a turn-off bipolar junction transistor, and a turn-off signal source. The circuit is activated by a turn-on signal and deactivated by a turn-off signal. | 2011-12-29 |
20110316610 | TRANSMISSION GATE CIRCUITRY FOR HIGH VOLTAGE TERMINAL - A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area. | 2011-12-29 |
20110316611 | CONTROL CORD FOR HEADSETS AND AUXILIARY DEVICES - A cord-based controller for an auxiliary device, such as a headset, is provided for use with a portable electronic device. A pressure-sensitive, and preferably bendable, material such as a piezoelectric pressure sensor is placed within or on an or cord of a headphone lead, such as by wrapping it within the outer shielding of the cord. A self-powered controlling sensor is arranged to control the electronic device using a generated control signal. The controlling sensor comprises a sensor material. The control signal is generated by deformation of the sensor material independent of power supplied to the headset and independent of power supplied to the portable electronic device. This is achieved without requiring a separate housing for the controller, which typically protrudes from the cord. A plurality of control sensor elements can be provided, each producing a different control signal voltage transmitted along a single control signal electrical. | 2011-12-29 |
20110316612 | SEMICONDUCTOR CARRIER WITH VERTICAL POWER FET MODULE - A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET. | 2011-12-29 |
20110316613 | MICROPROCESSOR APPARATUS AND METHOD FOR SECURING A PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations. | 2011-12-29 |
20110316614 | APPARATUS AND METHOD FOR TAMPER PROTECTION OF A MICROPROCESSOR FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. | 2011-12-29 |
20110316615 | INTEGRATED CIRCUIT - An integrated circuit, wherein a voltage-adjustable power supply circuit ( | 2011-12-29 |
20110316616 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR CONTROLLING POWER SUPPLY - A semiconductor integrated circuit includes a plurality of circuit regions, at least one power source switch that switches between two states of supplying power or not supplying power to at least one of the plurality of circuit regions, a power source control circuit that controls the at least one power source switch, a clamp scan chain having a plurality of flip-flops to which an output from the at least one circuit region to another region is input, and a clamp data control circuit that sets the plurality of flip-flops of the clamp scan chain to a predetermined output state. | 2011-12-29 |
20110316617 | METHOD AND APPARATUS FOR FULL CLOCK CYCLE CHARGE PUMP OPERATION - A charge pump comprises at least one charge pump cell and control logic. The at least one charge pump cell is configured to receive a power supply voltage and provide a pump output voltage higher than the power supply voltage. The control logic is configured to receive an oscillator signal and a level detector enable signal, provide at least one cell clock signal, based on the oscillator signal, to the at least one charge pump cell, control the at least one pump cell to charge while the level detector enable signal is asserted, and control the at least one pump cell to continue to charge after the level detector enable signal is deasserted and until a full pulse cycle of the oscillator signal is completed. | 2011-12-29 |
20110316618 | SUB-STAGE FOR A CHARGE PUMP - A sub-stage ( | 2011-12-29 |
20110316619 | POWER SUPPLY VOLTAGE MONITOR CIRCUIT - According to one embodiment, a power supply voltage monitor circuit includes a constant voltage circuit, a level shift circuit, a clamping circuit, a first differential circuit, and a second differential circuit. The first differential circuit include a differential unit receiving a constant current supplied from a current source and outputting an output voltage in accordance with a potential difference between a first input voltage obtained by subjecting the second constant voltage to resistive division and a second input voltage obtained by subjecting the power supply voltage to resistive division, and an output unit outputting a rectangular signal in accordance with the output voltage of the differential unit. The second differential circuit turns off the current source of the differential unit depending on a potential difference between the first constant voltage and the first input voltage to thereby control the output operation of the output unit, in a case where the clamping circuit does not fix the first constant voltage. On the other hand, The second differential circuit turns on the current source of the differential unit depending on a potential difference between the clamping voltage and the first input voltage. | 2011-12-29 |
20110316620 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 2011-12-29 |
20110316621 | LOW INPUT BIAS CURRENT CHOPPING SWITCH CIRCUIT AND METHOD - A chopper-stabilized circuit ( | 2011-12-29 |
20110316622 | ELECTRONIC CIRCUIT - An electronic circuit includes an amplifier that amplifies an input signal, a control circuit configured to generate a control signal by averaging an output signal of the amplifier based on a time constant, a first time constant control circuit configured to generate a first time constant control signal based on the control signal, the first time constant control signal changing the time constant of the control circuit to a second time constant from a first time constant smaller than the second time constant, a second time constant control circuit configured to generate a second time constant control signal by averaging the output signal of the amplifier based on a third time constant between the first time constant and the second time constant, the second time constant control signal changing the time constant of the control circuit to the first time constant from the second time constant, and a bypass circuit bypassing the input signal of the amplifier based on the control signal. | 2011-12-29 |
20110316623 | METHOD FOR AMPLIFYING A SIGNAL BY A POWER AMPLIFIER, POWER AMPLIFIER SYSTEM, DEVICE, COMPUTER PROGRAM PRODUCT, AND DIGITAL STORAGE MEDIUM THEREOF - The invention relates to a method for amplifying a carrier signal (CS | 2011-12-29 |
20110316624 | Transformer Structures For A Power Amplifier (PA) - In one embodiment, the present invention includes a transformer formed on a semiconductor die. Such transformer may have multiple coils, including first and second coils. Each coil may have segments that in turn are formed on a corresponding metal layer of the semiconductor die. The segments of a given coil are coupled to each other, and the first and second coils can be interdigitated with each other. | 2011-12-29 |
20110316625 | MIXED-SIGNAL TRANSMISSION CIRCUIT FOR SWITCHING POWER AMPLIFIERS - The invention relates to an upstream unit ( | 2011-12-29 |
20110316626 | D-CLASS AMPLIFIER - A D-class amplifier includes: a bridge circuit adapted to drive an inductive load; a power supply voltage detection section outputting a quantized power supply voltage signal indicating a power supply voltage fed to the bridge circuit; and a gain-controlled PWM section adjusting a gain in response to the quantized power supply voltage signal, amplifying the input signal in response to the gain, generating a PWM signal from the amplified input signal, and feeding the PWM signal to the bridge circuit. The power supply voltage detection section includes: an error integration section generating a quantized signal by integrating a difference between the power supply voltage and the quantized power supply voltage signal; and a digital filter removing high frequency components of the quantized signal to output the quantized power supply voltage signal. The gain-controlled PWM section controls the gain such that variations of the power supply voltage are cancelled. | 2011-12-29 |
20110316627 | DYNAMIC CONSTANT POWER AMPLIFIER - A switching amplifier including a voltage sensor circuit connected to a high voltage supply rail for measuring the power supply voltage. A current sensor circuit is connected to the high voltage supply rail for measuring the power supply current. An error amplifier is connected to the switching amplifier and receives one or more values based on the measurements taken by the voltage sensor and current sensor, and the error amplifier produces an error signal when a predetermined power limit is exceeded. A signal limiting circuit is connected to the error amplifier and the switching amplifier and limits the output power to rated power at any rated load impedance when the error amplifier produces the error signal. This switching amplifier is capable of automatically limiting output power at rated power into all rated load impedances, and dynamically reacts to the frequency-dependant impedance of a typical audio system. | 2011-12-29 |
20110316628 | COMPLIMENTARY SINGLE-ENDED-INPUT OTA-C UNIVERSAL FILTER STRUCTURES - A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source. | 2011-12-29 |
20110316629 | OFFSET CANCELLATION FOR DIFFERENTIAL CIRCUITS - An offset cancellation circuit for canceling an offset voltage in an amplifier is provided herein. The offset cancellation circuit includes a current source configured to provide an offset current, a switching stage comprising first and second switches, and a cascode stage. The cascode stage comprises a first cascode device configured to receive the offset current from the first switch and inject the offset current into a first differential end of the amplifier, and a second cascode device configured to receive the offset current from the second switch and inject the offset current into a second differential end of the amplifier. Offset voltages are common to many differential circuits as a result of mismatch. The injection of current by the offset cancellation circuit can reduce or eliminate an offset voltage, while the cascode stage can prevent parasitic capacitance associated with the offset cancellation circuit from creating further mismatch. | 2011-12-29 |
20110316630 | PUSH-PULL LINEAR HYBRID CLASS H AMFLIER - Several push-pull linear hybrid class H amplifiers are disclosed. A split power rail provides a positive supply rail and a negative supply rail in response to a power supply control voltage. A push-pull amplifier stage is powered by the positive and negative supply rails. The amplifier stage receives an input signal and provides a corresponding amplified output signal. A power supply control circuit provides the power supply control voltage in response to the smaller of the positive and negative supply rails, and the input signal. | 2011-12-29 |
20110316631 | LNA CIRCUIT FOR USE IN A LOW-COST RECEIVER CIRCUIT - A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal. | 2011-12-29 |
20110316632 | OPTICAL COMMUNICATION DEVICE - An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP | 2011-12-29 |
20110316633 | AMPLIFYING DEVICE - In an amplifying device, an amplification unit includes a first amplifier which amplifies a signal and a second amplifier which amplifies a signal when the signal has a predetermined level or more. A detector detects a temperature change. A calculation unit calculates an adjacent channel leakage power ratio of an output signal output from the amplification unit based on detection of the temperature change of the detector. A controller controls gate biases of the first and second amplifiers based on the adjacent channel leakage power ratio calculated by the calculation unit. | 2011-12-29 |
20110316634 | HIGH SPEED LOW POWER MULTIPLE STANDARD AND SUPPLY OUTPUT DRIVER - A multi-mode driver and method therefore includes a plurality of amplifiers, an adjustable load block, and adjustable current supply circuitry that selectively adjusts current magnitudes supplied to at least one of the plurality of amplifiers. The multi-mode driver can operate in a KR mode with a higher voltage supply, an SR4 mode with the higher voltage supply, and an SFI mode with a lower voltage supply. To support these modes, the multi-mode driver selectively operates a plurality of amplifiers, adjusts current magnitudes supplied to the amplifiers, and selectively adjusts an adjustable load. Thus, the multi-mode driver is operable to selectively and efficiently produce high swing and low swing output signals and to efficiently operate with any one of a plurality of supplies. The driver includes selectable loads and parallel-coupled amplifier devices that are selected based on mode. | 2011-12-29 |
20110316635 | TRIPLET TRANSCONDUCTOR - To reduce a knee voltage of a Darlington amplifier, a negative voltage is applied by a depletion mode FET between the emitter of one amplifying transistor and the base of another amplifying transistor to provide a reduced potential, which reduces the knee voltage of the Darlington amplifier. Reducing the knee voltage of the Darlington amplifier decreases the size of a saturation region thereby increasing the linearity of the Darlington amplifier. | 2011-12-29 |
20110316636 | DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT - A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage. | 2011-12-29 |
20110316637 | AMPLIFIER MODULE WITH MULTIPLE OPERATING MODES - An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches. | 2011-12-29 |
20110316638 | DELAY-LINE SELF-OSCILLATOR - An electrical, magnetic or electromagnetic delay line self oscillator is described with a delay line arrangement, an oscillator control circuitry, and a frequency selection impedance connecting the delay line arrangement and the oscillator control circuitry and presenting an impedance to the delay line arrangement. The oscillator control circuitry includes an amplifier, a non linear amplitude control element (N-LACE) such as an active device with a negative differential conductance that provides an output amplitude has a negative second derivative with respect to an input signal, and a driver. The modal characteristics of electromagnetic delay lines can thus be exploited across a wide range of instrumentation applications, and a means is provided to enhance the achievable functionality and/or performance of the instrumentation without the need for expensive additional electrical hardware or electronics. | 2011-12-29 |
20110316639 | DIGITAL VCO CALIBRATION METHOD AND APPARATUS - A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication. | 2011-12-29 |
20110316640 | GATE PULSE MODULATION CIRCUIT AND SLOPING MODULATION METHOD THEREOF - Exemplary gate pulse modulation circuit and sloping modulation method applied thereto are provided. The gate pulse modulation circuit has an output terminal and includes a voltage modulation circuit and a comparator control circuit. The voltage modulation circuit is electrically coupled between a gate power supply voltage and a second voltage and subjected to the control of a sloping control signal to perform a sloping operation and then output a sloped voltage signal. The comparator control circuit includes a comparing unit and a switching unit. First and second input terminals of the comparing unit respectively are electrically coupled to a node and a first voltage. During the voltage modulation circuit performing the sloping operation, a magnitude relationship between a voltage on the node and the first voltage decides on-off states of the switching unit and thereby decides the moment of the first voltage delivered to the output terminal. | 2011-12-29 |
20110316641 | RADIO FREQUENCY DEVICE - A radio frequency device is disclosed, which includes an isolation substrate, a ground layer, a first signal end, a second signal end, a radio frequency circuit, and an impedance unit. The isolation substrate includes a first plane and a second plane. The ground layer is disposed on the second plane of the isolation substrate for providing grounding. The first signal end is formed on the first plane of the isolation substrate. The second signal end is formed on the first plane of the isolation substrate and coupled to the ground layer. The radio frequency circuit is disposed on the first plane of the isolation substrate and coupled to the first signal end. The impedance unit is disposed on the first plane of the isolation substrate and coupled to the first signal end and the second signal end. | 2011-12-29 |
20110316642 | MODULE - A module includes a substrate including an IC disposed on an upper surface side thereof. The IC includes a modulation circuit unit arranged to modulate a baseband signal into an RF signal and a demodulation circuit unit arranged to demodulate an RF signal into a baseband signal. The substrate includes a first wiring layer provided on the upper surface side, a second wiring layer disposed on a lower surface side of the first wiring layer, and an insulator layer disposed between the first wiring layer and the second wiring layer. A baseband signal-use wiring pattern is provided in the first wiring layer, an RF signal-use wiring pattern is provided in the second wiring layer, and on one surface of the insulator layer, a substantially flat-plate ground electrode pattern is arranged to cover substantially an entire surface. At least a balun is provided in the second wiring layer and defined by the RF signal-use wiring pattern, and when viewed in a top view, at least a portion of the RF signal-use wiring pattern defining the balun is arranged on an upper surface side of the second wiring layer so as to surround a connecting wiring electrically connecting an RF terminal of the IC and a balanced-side terminal of the balun to each other. | 2011-12-29 |
20110316643 | THIN FILM BALUN - A thin film balun of the present invention comprises: an unbalanced transmission line UL including a first line portion L | 2011-12-29 |
20110316644 | CIRCUIT BOARD WITH JUMPER STRUCTURE - A circuit board with jumper structure is disclosed. The circuit board includes a substrate, a ground layer, a first signal transmission line, and a second signal transmission line. The ground layer is formed on a second plane of the substrate. The first signal transmission line is formed on a first plane of the substrate, and coupled to a first signal end and a second signal end. A first signal transmitted on the first signal transmission line in a combination method of a microstrip line to co-planar waveguide transition and a co-planar waveguide to microstrip line transition. The second signal transmission line is formed on the second plane of the substrate, and coupled to a third signal end and a fourth signal end. A second signal is transmitted on the second signal transmission line in the co-planar waveguide transmission. | 2011-12-29 |
20110316645 | STEP ATTENUATOR APPARATUS - A step attenuator apparatus is provided, having an attenuation ratio which is switchable according to a control signal. Multiple variable attenuators are connected in series. Each variable attenuator includes a first terminal, a second terminal, multiple paths having different attenuation ratios, a first switch that can be connected to one end of a desired path selected from among the multiple paths, and a second switch that can be connected to the other end of a desired path selected from among the multiple paths. When a control signal is an instruction to set the step attenuator apparatus to a disconnected state, a control unit connects the first switch of the first-stage variable attenuator to one of the multiple paths, and connects the second switch of the first-stage variable attenuator to a different one of the multiple paths. | 2011-12-29 |
20110316646 | SANDWICH STRUCTURE FOR DIRECTIONAL COUPLER - A sandwich strip coupled coupler implemented in a multi-layer substrate, such as a multi-layer printed circuit board. In one example, the sandwich strip coupled coupler includes a main arm having a first main arm section and a second main arm section disposed above the first main arm section, the first and second main arm sections being electrically connected together, and a coupled arm disposed between the first and second main arm sections, the first main arm section, the coupled arm and the second main arm section forming a sandwich structure. | 2011-12-29 |
20110316647 | ELASTIC WAVE BRANCHING FILTER - A reception filter includes a first and second longitudinally coupled resonator-type surface acoustic wave filter portions and a surface acoustic wave resonator. The first and second longitudinally coupled resonator-type surface acoustic wave filter portions each include at least three IDT electrodes. The surface acoustic wave resonator includes one IDT electrode connected to at least one of the at least three IDT electrodes. The reception filter is arranged such that a ratio of a capacitance of the surface acoustic wave resonator to a capacitance of each of the at least one of the at least three IDT electrodes included in the longitudinally coupled resonator-type surface acoustic wave filter portion, the at least one of the at least three IDT electrodes being electrically connected to the one IDT electrode of the surface acoustic wave resonator, is in the range of about 1.9 to about 2.5. | 2011-12-29 |
20110316648 | ELASTIC-WAVE LADDER FILTER - An elastic-wave ladder filter significantly reduces loss within a passband while also increasing the passband and attenuation. The elastic-wave ladder filter includes a series arm that connects an input end and an output end and a parallel arm that connects the series arm and a ground potential. The series arm includes at least three series arm resonators connected to each other in series. The resonant frequencies of the at least three series arm resonators differ from each other. An aspect ratio of the series arm resonator having the lowest resonant frequency is larger than an average of the aspect ratios of all the series arm resonators when the aspect ratio is defined as a ratio of an overlap width of electrode fingers of a series arm resonator to a number of pairs of the electrode fingers. | 2011-12-29 |
20110316649 | Reactance Filter Having a Steep Edge - A reactance filter includes a series branch that connects a signal input to a signal output. At least one parallel branch branches off from the series branch with respect to ground. A parallel resonator is arranged in each parallel branch. Two or more series resonators are connected in series in the series branch. A capacitor is connected in parallel with one of the series resonators in the series branch. | 2011-12-29 |
20110316650 | BAND STOP FILTER - The present invention relates to a band stop filter comprising: a resonating bar; a housing on the inside of which is formed a receiving space where the resonating bar is positioned, and which is made in a stepped form such that at least one part of an upper-end part is narrower than a lower-end part in terms of the internal width of the receiving space during the formation of the receiving space; a lower cover which has the resonating bar fitted thereto, is joined to the lower part of the housing and, when so joined, is assembled such that the resonating bar is inserted into the receiving space, and which forms the floor surface of the receiving space; and a hermetic-sealing cover which is provided within a recess pre-made in the housing in such a way as to couple with a resonator formed by the receiving space and the resonating bar on the inside of the receiving space, and is designed to hermetically seal the recess in the housing where a transmission line has been provided. | 2011-12-29 |
20110316651 | BAND STOP FILTER OF COMPOSITE RIGHT/LEFT HANDED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - Provided are a band stop filter of a CRLH structure and a manufacturing method thereof. A band stop filter of a CRLH structure according to an exemplary embodiment of the present invention includes a microstrip transmission line formed on a substrate; a right handed material (RHM) region including a first stub and a first capacitor connected to the microstrip transmission line in parallel and stopping a signal of a first frequency band passing through the microstrip transmission line; and a left handed material (LHM) region further provided between the first stub and the first capacitor to block a signal of a second frequency band passing through the microstrip transmission line. | 2011-12-29 |
20110316652 | MULTIBAND RESONATOR AND MULTIBAND-PASS FILTER - An multiband resonator of the present invention includes a dielectric substrate including three or more dielectric layers, a ground conductor, a main-line conductor, a sub-line conductor, a sub open stub, a main open stub, a short-circuit conductor, a main through conductor, and a sub through conductor. The short-circuit conductor electrically connects one end of the main-line conductor to one end of the sub-line conductor and to the ground conductor. The main through conductor electrically connects the other end of the main-line conductor to one end of the main open stub that is aligned with that other end of the main-line conductor. The sub through conductor electrically connects the other end of the sub-line conductor to one end of the sub open stub that is aligned with that other end of the sub-line conductor. | 2011-12-29 |
20110316653 | TUNABLE BANDPASS FILTER - Tunable bandpass filters are provided. In one embodiment, the invention relates to a tunable bandpass filter including a dielectric substrate having a first surface opposite to a second surface, a conductive ground plane disposed on the first surface, a microstrip conductive trace pattern disposed on the second surface, the trace pattern defining a phase velocity compensation transmission line section including a series of spaced alternating T-shaped conductor portions, at least one varactor diode coupled to a first T-shaped conductor portion of the series of T-shaped conductor portions and to the conductive ground plane, and bias control circuitry coupled to the first T-shaped conductor portion, wherein the bias control circuitry is configured to control the at least one varactor diode. | 2011-12-29 |
20110316654 | SYSTEM AND METHOD FOR TUNING-CAPACITOR-ARRAY SHARING - A system and method for sharing a switched capacitor array (SCA) by two tuning circuits are disclosed. In a multiple-band radio receiver, there is a need to use multiple tuning circuits for signals in different bands. The tuning circuit typically comprised an adjustable capacitance device and other tuning components, where the adjustable capacitance device is often implemented in SCA. The present invention discloses a system and method comprising n sections of capacitor elements where each capacitor element comprises a capacitor and switches to selectively connect the capacitor to one of the tuning circuit. Consequently, the SCA can be shared by the two tuning circuits. The control bits for the switched may be provided from a programmable control register. | 2011-12-29 |
20110316655 | Toggle Switch With Magnetic Mechanical And Electrical Control - A switch includes magnets that provide both mechanical actuation of the switch as well as electrical operation of the switch. A system controller detects a state of the switch and controls operation of one or more systems in a structure based on the state of the switch. The system controller can detect the state of the switch by detecting a position of a magnet of the switch. | 2011-12-29 |
20110316656 | COIL ASSEMBLY FOR GUIDING A MAGNETIC OBJECT IN A WORKSPACE - A coil assembly for guiding a magnetic object, such as an endoscopy capsule, in a workspace, wherein the magnetic object exhibits a magnetic dipole, includes different versions of coil assemblies having a number of individual coils and corresponding activation units for feeding current to the respective coils. The coil arrangement can have exactly eleven individual coils and eight power amplifiers, nine individual coils and seven power amplifiers, eight individual coils with six or seven power amplifiers, six individual coils with five power amplifiers, and five individual coils with five power amplifiers. | 2011-12-29 |
20110316657 | Three Dimensional Wire Bond Inductor and Transformer - A three-dimensional inductor or transformer for an electronic packaging system that includes a plurality of conductive traces and a plurality of conductive wire bonds. The traces are located in a single layer, and each have a first and second pad. Each of the wire bonds couples the second pad of one trace to the first pad of another trace. The trace and wire bonds create a continuous conductive path from the first pad of a first trace to the second pad of a last trace. Passing a current from the first trace to the last trace creates an electromagnetic field between the single layer and the wire bonds. The transformer includes two independent and electromagnetically coupled inductors that can be interleaved. The continuous conductive path can be solenoid-shaped. A shielding layer can also be included that blocks the substrate from the electromagnetic field of the inductor or transformer. | 2011-12-29 |
20110316658 | THIN TYPE COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - A thin type common mode filter includes an insulating flexible substrate, a first magnetic material layer, a first coil leading layer, a coil main body multi-layer, a second coil leading layer, and a second magnetic material layer. The first coil leading layer is formed on a first surface of the flexible substrate, and the first coil leading layer is formed on a second surface of the flexible substrate opposite to the first surface. The coil main body multi-layer, the second coil leading layer, and the second magnetic material layer are sequentially stacked on the first coil leading layer. | 2011-12-29 |
20110316659 | TRANSFORMER TESTING - A method of testing a transformer prior to installation in a high-pressure environment wherein the transformer comprises a transformer core comprising a stack of a plurality laminations, is provided. The method comprises applying a mechanical compression force to the stack, the force being at least equivalent to the ambient pressure of the high-pressure environment; and testing the electrical efficiency of the transformer. | 2011-12-29 |
20110316660 | MULTILAYER STRUCTURE USEFUL FOR ELECTRICAL INSULATION - A multilayer structure contains
| 2011-12-29 |
20110316661 | UNSATURATED POLYESTER RESIN COMPOSITION FOR COIL ADHESION - It is an objective of the present invention to provide a highly adhesive unsaturated polyester resin composition for fixing or immobilizing coils. There is provided an unsaturated polyester resin composition for adhesion of a coil, which includes the ingredients of: A) an unsaturated polyester resin and/or a vinyl ester resin; B) a monomer including a vinyl group as a polymerizable substituent at at least one end thereof; C) an isocyanate; and D) a polymerization initiator. | 2011-12-29 |
20110316662 | WINDING ARRANGEMENT FOR A TRANSFORMER OR FOR A THROTTLE - A winding arrangement for a transformer or for a reactor is provided. The winding arrangement includes an annular winding cover part disposed on the front face of a winding, wherein a side surface of the winding cover part overlaps a front surface of the winding, wherein the annular winding cover part is designed to be magnetically conductive at least in a partial area and comprises a convex side surface facing away from the winding. | 2011-12-29 |
20110316663 | METHOD AND APPARATUS FOR PROVIDING ENERGY-AWARE CONNECTION AND CODE OFFLOADING - An apparatus for enabling provision of energy-aware connection and code offloading may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code may be configured, with the processor, to cause the apparatus to perform at least monitoring, at a client terminal, communications or processes associated with at least two applications of the client terminal, determining whether a trigger condition associated with the communications or processes monitored is met based at least on a directed graph defining a plurality of triggers for different applications and corresponding inputs and outputs associated with each respective trigger, and determining whether to direct an operational adjustment with respect to at least one of the communications or processes monitored based at least on profile information in response to the trigger condition being met. A corresponding method and computer program product are also provided. | 2011-12-29 |
20110316664 | REMOTE CONTROL FOR SOUND SYSTEM - A remote control for a sound system includes a first type of wireless system for transmitting commands for controlling operation of a sound output device. The remote control also includes a second type of wireless system for wirelessly transmitting signals that represent sounds created by a first human voice to a first portable audio storage device which can be electrically temporarily connected to the sound output device. | 2011-12-29 |
20110316665 | PERSONAL WRITING DEVICE WITH USER RECOGNITION CAPABILITIES AND PERSONAL INFORMATION STORAGE - Systems and method for a handheld biometrically secured user input device are described. A biometric authentication device may be coupled with a handheld enclosure, the biometric authentication device capable of collecting user authentication information from a user to authenticate the user's identity. A computer-readable storage device may be coupled with the handheld enclosure for storing confidential financial information of the user, wherein access to the confidential financial information is granted only after the user's identity has been authenticated. A sensor may be coupled with the handheld enclosure, capable of capturing the user's handwriting. Also, a communication device may be configured to transmit information gathered with the sensor to a computer system. | 2011-12-29 |
20110316666 | INFORMATION DEVICE, COMPUTER PROGRAM PRODUCT AND METHOD THEREOF - According to one embodiment, an information device is provided with a display screen and a camera that face the same direction. The information device includes a determination module and an output control module. The determination module determines whether face recognition information obtained from image data of the face of a user captured by the camera matches registered face recognition information of a user to which a message is received. The output control module displays the message for the user when the face recognition information obtained from the image data matches the registered face recognition information. The output control module stacks the message when the face recognition information obtained from the image data does not match the registered face recognition information. | 2011-12-29 |
20110316667 | MESH NETWORK DOOR LOCK - Systems and methods are disclosed for sending a code from a mesh network key and wirelessly communicating the code with one or more mesh network appliances over a mesh network such as ZigBee; receiving the code over the mesh network by a mesh network lock controller; and providing access to the secured area upon authenticating the code. | 2011-12-29 |
20110316668 | Method and Apparatus to Facilitate Message Transmission and Reception Via Wireline Using Different Transmission Characteristics - Upon providing ( | 2011-12-29 |
20110316669 | APPARATUS FOR AUTOMATICALLY CHANGING STATE OF VEHICLE CLOSURE - An apparatus for changing the state of a vehicle closure is disclosed. The apparatus includes a primary mobile unit, a secondary mobile unit, and a detection device. The detection device is operable to automatically detect whether the primary mobile unit is within a first range of the detection device, and whether the secondary mobile unit is within a second range of the detection device. The apparatus further includes a controller operable to change the state of the vehicle closure when the detection device detects that the secondary mobile unit is within the second range while the primary mobile unit is detected within the first range. | 2011-12-29 |
20110316670 | BIOMETRIC KIT AND METHOD OF CREATING THE SAME - A biometric kit and method of using the same includes the collection and verification of photographs, friction ridge detail, DNA profile, and dental radiographs of an individual along with a personal information profile. The collected and verified data is converted to a digital format and stored | 2011-12-29 |
20110316671 | CONTENT TRANSFER SYSTEM AND COMMUNICATION TERMINAL - A communication terminal including an interface that receives an input requesting a reservation to record content; a control unit that acquires image data corresponding to a user of the communication terminal; a recording reservation unit that generates recording reservation information based on the input and the image data; and a communication unit that transmits the recording reservation information to a server, and receives, from the server, content based on the recording reservation information. | 2011-12-29 |
20110316672 | MOBILE COMMUNICATION BASED TAGGING - A plurality of tags can be generated by a user using the mobile electronic device and is associated with the current location of the mobile electronic device. A message can include metadata associated with the current location and at least a subset of tags from the plurality of tags. The message can be transmitted to a first system over a mobile communication network. The message received from the mobile electronic device can be stored in a repository of the first system. The first system can identify the current location of the mobile electronic device using the message. The system can parse the subset of tags and can maps the parsed subset of tags with the current location. | 2011-12-29 |
20110316673 | RFID TAG AND METHOD RECEIVING RFID TAG SIGNAL - Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal. | 2011-12-29 |
20110316674 | ASSET TRACKING SYSTEM INCLUDING A TAG CONTROLLER - A plurality of tags communicates a plurality of messages to a reader device. A message collector at the reader device collects at least a subset of the received messages, and provides the collected messages to a set of logical readers. The message collector and the logical readers filter the collected messages based on configuration information provided by an associated application, and provide tag event information to the application based on the filtered messages. The reader device can be configured based on customized configuration information, so that the tag event information provided to an application is customized for that application. | 2011-12-29 |
20110316675 | APPARATUS FOR COMMUNICATING WTIH RFID TAG - The disclosure discloses an apparatus comprising: an apparatus antenna; a signal transmitting portion configured to transmit a response request signal; an information obtainment portion configured to obtain tag identification information of the RFID tag circuit element; an identification information storage portion configured to store the tag identification information obtained; a calculation portion configured to calculate a duplicated obtainment ratio by the number of redundantly obtained pieces of information of a current obtainment result of the tag identification information to a past obtainment result of the tag identification information stored in the identification information storage portion and by the obtainment result; a comparison portion configured to compare the duplicated obtainment ratio with a threshold value; and a communication control portion configured to execute communication control of widening or narrowing a communication range in the case that the duplicated obtainment ratio is less than or exceeds the threshold value. | 2011-12-29 |
20110316676 | APPARATUS AND METHOD FOR MANAGING POWER-CONSTRAINED WIRELESS DEVICES - A method of interrogating a set of tags with an interrogator is provided. The method includes defining a duration of a wake-up superframe that matches that of a wake-up cycle of the tags; defining an integer number of time periods within the duration of the wake-up superframe such that each time that one of the set of tags wakes is within one of the time periods of the wake-up superframe, the tags waking within a particular time period defining a group of tags; providing a first wake-up signal in a first time period to wake a first group of the tags; and providing a second wake-up signal in a second time period wake a second group of the tags. | 2011-12-29 |
20110316677 | Method and System for Intra-Chip Waveguide Communication - Methods and systems for configuring one or more electrical waveguides in an integrated circuit by adjusting a geometry of the one or more electrical waveguides, and communicating one or more electrical signals between components within the integrated circuit via the one or more electrical waveguides. The geometry of the one or more electrical waveguides may be configured by adjusting a length of the one or more electrical waveguides utilizing switches in the integrated circuit. The switches may include CMOS transistors. The one or more signals may include a microwave signal and a low frequency digital control signal that configures the microwave signal. The electrical waveguides may include metal and/or semiconductor layers deposited on and/or embedded within the integrated circuit. | 2011-12-29 |
20110316678 | Radiant electromagnetic energy management - A device provides a radiant electromagnetic energy output. During standby operation of the device, the output is provided at one or more frequencies selected to dissipate excess power through atmospheric absorption. Circuitry is included to tune the output of the device to a second frequency different than the first frequency for various directed energy applications that make use of the excess power. The circuitry can be arranged to further utilize frequency agility for power dissipation, to provide different operating modes involving a radiant output, or the like. | 2011-12-29 |
20110316679 | APPARATUS AND METHOD FOR PROXIMITY BASED INPUT - In accordance with an example embodiment of the present invention, a method is provided for controlling display operations in an electronic device. The electronic device provides an input mode, in which a first function is associated with a hovering input and a second function is associated with a touch input to an input surface. A three-dimensional virtual user interface item is displayed, and in response to detecting an input object within a guard range in relation to the input surface, the virtual user interface item is adapted to alert the user to avoid unintentionally touching the input surface. | 2011-12-29 |
20110316680 | Method for Operating an Access Arrangement - In a method for operating an access arrangement (ZA) for a vehicle (FZ), access to the vehicle can be obtained by a mobile identification transmitter (IDG). With this method, first an ambient brightness around the vehicle is determined. Furthermore, the presence of an authorized mobile identification transmitter in an approach region (ANB, ANB | 2011-12-29 |
20110316681 | SHAPE MEMORY POLYMER-BASED HAPTIC DEVICES - A haptic device includes a shape memory polymer member. A plurality of user interface locations is defined on the shape memory polymer member and a plurality of activation elements is located proximate to the plurality of user interface locations. The plurality of user interface locations of the shape memory polymer are activated in response to a stimulus from the plurality of activation elements to alter at least one physical property of the shape memory polymer at the plurality of user interface locations. Additionally, a plurality of control devices configured for adjusting a variable of a system is located proximate to the plurality of user interface locations such that, one of the plurality of control devices may be adjusted when a user touches a corresponding one of the plurality of user interface locations. | 2011-12-29 |