52nd week of 2018 patent applcation highlights part 65 |
Patent application number | Title | Published |
20180374718 | METHOD OF RECONSTITUTED SUBSTRATE FORMATION FOR ADVANCED PACKAGING APPLICATIONS - Embodiments of the present disclosure generally describe methods for minimizing the occurrence and the extent of die shift during the formation of a reconstituted substrate in fan-out wafer level packaging processes. Die shift is a process defect that occurs when a die (device) moves from its intended position within a reconstituted substrate during the formation thereof. Generally, the methods disclosed herein include depositing a device immobilization layer and/or a plurality of device immobilization beads over and/or adjacent to a plurality of singular devices (individual dies), and the carrier substrate they are positioned on, before forming a reconstituted substrate with an epoxy molding compound. The device immobilization layer and/or the plurality of device immobilization beads immobilize the plurality of singular devices and prevents them from shifting on the carrier substrate during the molding process. | 2018-12-27 |
20180374719 | SYSTEMS AND METHODS OF GAP CALIBRATION VIA DIRECT COMPONENT CONTACT IN ELECTRONIC DEVICE MANUFACTURING SYSTEMS - An electronic device manufacturing system includes a motion control system for calibrating a gap between surfaces of process chamber or loadlock components by moving those component surfaces into direct contact with each other. The component surfaces may include a surface of a substrate and/or a substrate support and a surface of process delivery apparatus, which may be, e.g., a pattern mask and/or a plasma or gas distribution assembly. The motion control system may include a motion controller, a software program executable by the motion controller, a network, one or more actuator drivers, a software program executable by the one or more actuator drivers, one or more actuators, and one or more feedback devices. Methods of calibrating a gap via direct contact of process chamber or loadlock component surfaces are also provided, as are other aspects. | 2018-12-27 |
20180374720 | GAS EXHAUST PLATE AND PLASMA PROCESSING APPARATUS - A gas exhaust plate capable of improving a confinement effect of plasma while achieving sufficient conductance is provided. The gas exhaust plate is provided between a sidewall of a processing vessel of a plasma processing apparatus and a mounting table provided within the processing vessel, and is configured to separate a processing space in which a processing is performed by a plasmarized gas from a gas exhaust space which is adjacent to the processing space and through which a gas generated by the processing is exhausted. The gas exhaust plate includes a porous metal sheet. | 2018-12-27 |
20180374721 | FILM FORMING APPARTUS - A supply part includes a first partition, a second partition under the first partition, a third partition under the second partition, a first flow path between the first partition and the second partition allowing a first gas to be introduced therein, a second flow path between the second partition and the third partition allowing a second gas to be introduced therein, a first piping extending from the second partition to reach below the third partition and being communicated with the first flow path, a second piping extending from the third partition to reach below the third partition and being communicated with the second flow path, and a convex portion provided on an outer circumferential surface of the first piping or an inner circumferential surface of the second piping protruding from one of the outer circumferential surface and the inner circumferential surface toward the other one. | 2018-12-27 |
20180374722 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus capable of achieving a uniform plasma space therein is provided. The plasma processing apparatus includes a processing vessel, a mounting table, a shield member, a shutter for an opening configured to be moved up and down, a first driving unit and a second driving unit. The processing vessel has a sidewall, and the sidewall is provided with a transfer path through which a processing target object is carried-in/carried-out. The mounting table is provided within the processing vessel. The shield member is provided along an inner surface of the sidewall to surround the mounting table and provided with an opening facing the transfer path. The first driving unit is configured to move the shutter up and down. The second driving unit is configured to move the shutter in a forward-backward direction with respect to the shield member. | 2018-12-27 |
20180374723 | APPARATUS AND METHOD FOR ETCHING ONE SIDE OF A SEMICONDUCTOR SUBSTRATE - An apparatus for etching one side of a semiconductor layer, including at least one etching tank for receiving an electrolyte, a first electrode, which is arranged to make electrical contact with the electrolyte located in the etching tank during use, at least a second electrode, which is arranged to make indirect or direct electrical contact with the semiconductor layer, at least one electric current source, which is electrically conductively connected to the first and the second electrode to produce an etching current, and at least one transport apparatus for transporting the semiconductor layer relative to the etching tank in such a way that substantially only an etching side of the semiconductor layer that is to be etched can be wetted by the electrolyte located in the etching tank during use. The current source is formed as a variable current source, and that the apparatus has a controller for controlling the variable current source, wherein the apparatus is designed such that the etching current can be changed automatically by the controller during the etching operation. A method for etching one side of a semiconductor layer is also provided. | 2018-12-27 |
20180374724 | ELECTROSTATIC CHUCK WITH INDEPENDENT ZONE COOLING AND REDUCED CROSSTALK - An electrostatic chuck is described with independent zone cooling that leads to reduced crosstalk. In one example, the chuck includes a puck to carry a substrate for fabrication processes, and a cooling plate fastened to and thermally coupled to the ceramic puck, the cooling plate having a plurality of different independent cooling channels to carry a heat transfer fluid to transfer heat from the cooling plate. | 2018-12-27 |
20180374725 | SIDE STORAGE PODS, EQUIPMENT FRONT END MODULES, AND METHODS FOR PROCESSING SUBSTRATES - Electronic device processing systems including side storage pods are described. One electronic device processing system has a side storage pod having a first chamber configured to receive a side storage container; a panel having a panel opening; the panel configured to be coupled between a side storage container and an equipment front end module; a side storage container received in the first chamber; and an exhaust conduit configured to be coupled to the side storage container received and extending to an exterior of the first chamber. | 2018-12-27 |
20180374726 | METHOD OF INSPECTING GAS SUPPLY SYSTEM - In one embodiment, a gas supply line is connected to a chamber of a substrate processing apparatus. A vaporizer is connected to the gas supply line. A flow rate controller is connected to the gas supply line in parallel with the vaporizer through a secondary valve. A primary valve is provided on a primary side of the flow rate controller. A method of the embodiment includes supplying a processing gas to the chamber from the vaporizer through the gas supply line in a state in which the primary valve is closed, the secondary valve is opened, and an exhaust device is operated to set a pressure of the chamber to a predetermined pressure and determining a time-average value of a measurement value obtained by a pressure sensor of the flow rate controller while the supplying the processing gas is performed. | 2018-12-27 |
20180374727 | METHOD OF INSPECTING GAS SUPPLY SYSTEM - In one embodiment, a vaporizer is connected to a chamber of a substrate processing apparatus through a gas supply line and a gas introduction port. An exhaust device is connected to the gas supply line. The substrate processing apparatus includes a pressure sensor that obtains a measurement value of a pressure of the gas supply line. A method according to the embodiment includes supplying a processing gas to the chamber from the vaporizer through the gas supply line, and monitoring a change of the measurement value obtained by the pressure sensor in a state in which supply of the processing gas to the gas supply line is stopped. | 2018-12-27 |
20180374728 | FLUID MONITORING SYSTEM AND METHOD FOR SEMICONDUCTOR FABRICATION TOOLS - A system and method provide for monitoring and controlling fluid flow in semiconductor manufacturing apparatuses. The method and system include a vortex flow meter coupled to a digital readout that displays the measured flow rate and trip point. The flow meter display includes input devices used to adjust the trip point. The system and method provide for sending signals via a custom relay to the semiconductor manufacturing apparatus which is adapted to terminate a processing operation or change the fluid flow if the trip point is tripped. The system and method also provide for sending an electrical signal to a computer by way of a data acquisition unit and a converter. The converter converts the signal to a communication protocol consistent with the computer network and provides fluid flow information and trip point data as a function of time to the computer which then displays such data graphically. | 2018-12-27 |
20180374729 | WAFER JIG WITH IDENTIFICATION MARK - Disclosed herein is a wafer jig with an identification mark for use in inspecting the function of an identification mark reading mechanism for reading an identification mark on a device wafer. The wafer jig includes a wafer piece cut from a region of a device wafer where an identification mark is formed, and a circular plate having the same diameter as the device wafer. The wafer piece is fixed to the circular plate such that the identification mark on the wafer piece is positionally aligned with the identification mark on the device wafer. | 2018-12-27 |
20180374730 | BOWING SEMICONDUCTOR WAFERS - This specification describes methods for processing semiconductor wafers, methods for loading semiconductor wafers into wafer carriers, and semiconductor wafer carriers. The methods and wafer carriers can be used for increasing the rigidity of wafers, e.g., large and thin wafers, by intentionally bowing the wafers to an extent that does not break the wafers. In some examples, a method for processing semiconductor wafers includes loading each semiconductor wafer into a respective semiconductor wafer slot of a semiconductor wafer carrier, horizontally bowing each semiconductor wafer, and moving the semiconductor wafer carrier into a processing station and processing the semiconductor wafers at the processing station while the semiconductor wafers are loaded into the semiconductor wafer carrier and horizontally bowed. | 2018-12-27 |
20180374731 | WAFER STORAGE CONTAINER - The present invention relates to a wafer storage container, more particularly, relates to a wafer storage container comprising a storage chamber forming an independent space separated from the wafer storage container, and a plurality of gas chambers communicating with the storage chamber, so that the gases are being supplied or exhausted through the area of the side surfaces of the storage chamber via the gas chambers in order to remove the fumes remaining on the surface of a wafer stored inside the wafer storage container efficiently, | 2018-12-27 |
20180374732 | APPARATUS FOR TRANSPORTATION OF A SUBSTRATE, APPARATUS FOR VACUUM PROCESSING OF A SUBSTRATE, AND METHOD FOR MAINTENANCE OF A MAGNETIC LEVITATION SYSTEM - An apparatus for transportation of a substrate is provided. The apparatus includes a vacuum chamber having a chamber wall configured to separate a vacuum side from an atmospheric side and a magnetic levitation system configured for a contactless levitation of a substrate carrier in the vacuum chamber. The magnetic levitation system includes at least one magnetic device configured for providing a magnetic force acting on the substrate carrier during transportation of the substrate carrier in the vacuum chamber along a transportation path and at least one holding unit configured to hold the at least one magnetic device being accessible from the atmospheric side. | 2018-12-27 |
20180374733 | INDEXABLE SIDE STORAGE POD APPARATUS, HEATED SIDE STORAGE POD APPARATUS, SYSTEMS, AND METHODS - In some embodiments, a side storage pod of an equipment front end module is provided that includes (1) an outer enclosure having a sealing surface configured to couple to the equipment front end module; (2) a side storage pod chamber having a body with a plurality of vertically-spaced storage members each configured to support a substrate; and (3) an indexer operable to vertically move the side storage pod chamber so that different subgroups of storage members are accessible by a load-unload robot in the equipment front end module. In other embodiments, a heated side storage pod is provided enabling degassing of substrates stored therein. Methods for processing substrates are described, as are numerous other aspects. | 2018-12-27 |
20180374734 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE HOLDER AND MOUNTING TOOL - A substrate processing apparatus, includes: a substrate holder including at least one support column to which a mounting part on which a substrate is mounted is attached and at least one auxiliary support column to which the mounting part is not attached, wherein the substrate holder is configured such that a diameter of the auxiliary support column is smaller than a diameter of the support column, and wherein the substrate holder is configured such that when the substrate is held by the mounting part, an end portion of the substrate and each of the support column is spaced apart from each other by a predetermined length. | 2018-12-27 |
20180374735 | SUBSTRATE FIXING DEVICE - A substrate fixing device includes a baseplate, an adhesive layer on the baseplate, and an electrostatic chuck on the adhesive layer. The adhesive layer includes a first layer and a second layer. The second layer is between the first layer and the electrostatic chuck. The thermal conductivity of the first layer is higher in a stacking direction in which the baseplate, the adhesive layer, and the electrostatic chuck are stacked than in a plane direction perpendicular to the stacking direction. The thermal conductivity of the second layer is higher in the plane direction than in the stacking direction. | 2018-12-27 |
20180374736 | ELECTROSTATIC CARRIER FOR DIE BONDING APPLICATIONS - Embodiments of the disclosure relate to the use of an electrostatic carrier for securing, transporting and assembling dies on a substrate. In one embodiment, an electrostatic carrier includes a body having a top surface and a bottom surface, at least a first bipolar chucking electrode disposed within the body, at least two contact pads disposed on the bottom surface of the body and connected to the first bipolar chucking electrode, and a floating electrode disposed between the first bipolar chucking electrode and the bottom surface. In another embodiment, a die-assembling system includes the electrostatic carrier configured to electrostatically secure a plurality of dies, a carrier-holding platform configured to hold the electrostatic carrier, a die input platform and a loading robot having a range of motion configured to pick the plurality of dies from the die input platform and place them on the electrostatic carrier. | 2018-12-27 |
20180374737 | HIGH TEMPERATURE HEAT PLATE PEDESTAL - An assembly, which in one form is a pedestal, includes an upper member, a lower member bonded to the upper member, and a thermal phase diffuser disposed between the upper member and the lower member within a hermetically sealed volume. The thermal phase diffuser diffuses heat by way of a phase change of a working fluid within the hermetically sealed volume. The assembly/pedestal is capable of operating at high temperatures, in excess of 1000° C., with a high degree of temperature uniformity, and in one form is an aluminum nitride (AlN) material. | 2018-12-27 |
20180374738 | CHIP MOUNTING APPARATUS AND METHOD USING THE SAME - A chip mounting method includes providing a first substrate including a light transmissive substrate having first and second surfaces, a sacrificial layer provided on the first surface, and a plurality of chips bonded to the sacrificial layer, obtaining first mapping data by testing the chips, the first mapping data defining coordinates of normal chips and defective chips among the chips, disposing a second substrate below the first surface, disposing the normal chips on the second substrate by radiating a first laser beam to positions of the sacrificial layer corresponding to the coordinates of the normal chips, based on the first mapping data, to remove portions of the sacrificial layer thereby separating the normal chips from the light transmissive substrate, and mounting the normal chips on the second substrate by radiating a second laser beam to a solder layer of the second substrate. | 2018-12-27 |
20180374739 | SUBSTRATE HOLDING MEMBER - A substrate holding member includes a base, and a plurality of convex parts formed at an upper surface of the base and configured to hold a substrate at top surfaces thereof. Each convex part has a root portion extending from the upper surface of the base, and a top portion formed on the root portion and including the top surface. In each convex part, a cross-sectional area of the root portion is larger than a cross-sectional area of the top portion. At least a portion including the top surface of the top portion is formed of a holding member made of a material having a greater Young's modulus than a material forming the base. The respective holding members are spaced apart from each other. | 2018-12-27 |
20180374740 | Substrate Support and Substrate Processing Apparatus - Described herein is a technique capable of preventing a susceptor made of quartz from being damaged by contacting a reflector deformed by thermal expansion. A substrate support according to the technique may include an upper susceptor made of quartz; a lower susceptor made of quartz; and a reflector reflecting heat and made of a metal in a planar shape. A lower surface of the upper susceptor is bonded with an upper surface of the lower susceptor such that the reflector is interposed therebetween, a first recess accommodating the reflector is provided at the upper surface of the lower susceptor, and a portion of the lower surface of the upper susceptor facing the first recess is roughened. | 2018-12-27 |
20180374741 | Method for Forming an Alignment Mark - Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process. | 2018-12-27 |
20180374742 | Systems and Methods for a Semiconductor Structure Having Multiple Semiconductor-Device Layers - A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included. The bottom surface of the SOI substrate is bonded to the patterned top surface of the first semiconductor device layer via the bonding surface. | 2018-12-27 |
20180374743 | ETCHING METHOD - An etching method of silicon-containing oxide film is provided. The etching method includes a first step of forming an etching pattern on the silicon-containing oxide film by etching the silicon-containing oxide film using a first plasma generated from a first gas supplied to the processing vessel, according to a pattern of a mask layered on the silicon-containing oxide film, and a second step of removing a reaction product adhering to vicinity of an opening of the etching pattern and to the mask using a second plasma generated from a second gas supplied to the processing vessel, by applying a first high frequency electric power for generating plasma and a second high frequency electric power for generating bias voltage. | 2018-12-27 |
20180374744 | FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE - Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole. | 2018-12-27 |
20180374745 | Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings - Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner. | 2018-12-27 |
20180374746 | DIFFUSION BARRIER LAYER FORMATION - A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma. | 2018-12-27 |
20180374747 | SELF-FORMING BARRIER PROCESS - A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a copper layer in a feature on the substrate, the copper layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the copper layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the copper layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the copper layer. | 2018-12-27 |
20180374748 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 2018-12-27 |
20180374749 | MECHANICALLY STABLE COBALT CONTACTS - A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal. | 2018-12-27 |
20180374750 | Methods Of Producing Fully Self-Aligned Vias And Contacts - Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line. | 2018-12-27 |
20180374751 | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby - A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. | 2018-12-27 |
20180374752 | SEMICONDUCTOR STRUCTURES - Semiconductor structure is provided. An exemplary semiconductor structure includes a semiconductor substrate including fin structures. The fin structures include a plurality of first fin structures having a first width and a plurality of second fin structures. The second fin structure has a second width at a lower potion and a third width at an upper portion, and the second width is greater than each of the first width and the third width. The semiconductor structure includes a first isolation film formed on the semiconductor substrate and between adjacent fin structures. The first isolation film has a top surface lower than the fin structures. The upper portion of each second fin structure having the third width passes through the top surface of the first isolation film. | 2018-12-27 |
20180374753 | STACKED ELONGATED NANOSHAPES OF DIFFERENT SEMICONDUCTOR MATERIALS AND STRUCTURES THAT INCORPORATE THE NANOSHAPES - Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively. | 2018-12-27 |
20180374754 | METHOD OF FORMING OXIDE LAYER FOR FINFET DEVICE - A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals, wherein the nitrogen-based radicals are distributed along a sidewall and over a top surface of the upper portion of the fin with respective different concentrations; and forming an oxide layer over the upper portion of the fin using a thermal oxidation process. | 2018-12-27 |
20180374755 | FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF - FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure. | 2018-12-27 |
20180374756 | FINFET DEVICES - FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures. | 2018-12-27 |
20180374757 | SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE - A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure. | 2018-12-27 |
20180374758 | VERTICAL FIELD EFFECT TRANSISTORS - Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. | 2018-12-27 |
20180374759 | BOUNDARY SPACER STRUCTURE AND INTEGRATION - The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure. | 2018-12-27 |
20180374760 | SEMICONDUCTOR DEVICE AND METHOD - A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping. | 2018-12-27 |
20180374761 | INTEGRATING AND ISOLATING NFET AND PFET NANOSHEET TRANSISTORS ON A SUBSTRATE - Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide. | 2018-12-27 |
20180374762 | METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE - A method for fabricating an array substrate, an array substrate, and a display device are disclosed. The method includes forming a whole layer of opaque film on a substrate; treating the film to form a transparent region and an opaque region in the film, wherein the opaque region corresponds with a channel region of an active layer; and forming a thin film transistor on the film which has been treated. In the method, prior to forming the thin film transistor, the whole layer of opaque film is formed to comprise the transparent region and the opaque region. When other films are deposited on the whole layer of film, no difference in height occurs, and this further avoids various defects due to difference in height. | 2018-12-27 |
20180374763 | POWER SWITCHING SYSTEM FOR ESC WITH ARRAY OF THERMAL CONTROL ELEMENTS - A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches. | 2018-12-27 |
20180374764 | WAFER PROCESSING EQUIPMENT HAVING CAPACITIVE MICRO SENSORS - Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a particle monitoring device for particle detection includes several capacitive micro sensors mounted on a wafer substrate to detect particles under all pressure regimes, e.g., under vacuum conditions. In an embodiment, one or more capacitive micro sensors is mounted on a wafer processing tool to measure material deposition and removal rates in real-time during the wafer fabrication process. Other embodiments are also described and claimed. | 2018-12-27 |
20180374765 | SEMICONDUCTOR PATTERN FOR MONITORING OVERLAY AND CRITICAL DIMENSION AT POST-ETCHING STAGE AND METROLOGY METHOD OF THE SAME - A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other. | 2018-12-27 |
20180374766 | WAFER AND METHOD FOR PROCESSING A WAFER - A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening. | 2018-12-27 |
20180374767 | PACKAGE FOR ELECTRONIC COMPONENT STORAGE, ELECRONIC DEVICE, AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a seal ring having a metal brazing material layer on one surface of a base material containing KOVAR and a metal plating layer on the other surface, ensuring that the seal ring can prevent generation of a stain on the surface of a metal plating layer and excellent airtightness of an electronic component housing package can be achieved. The present invention has attained the object above by a seal ring which is an annular sealing ring having a nickel layer on the first surface of a base material containing KOVAR (iron-nickel-cobalt alloy) and a metal brazing material layer on the second surface opposite the first surface, wherein the thickness of the nickel layer is from 0.1 to 20 μm. | 2018-12-27 |
20180374768 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semiconductor chip and the spacer; and a second bond provided between the spacer and the substrate. | 2018-12-27 |
20180374769 | ELECTRONIC DEVICE INCLUDING REDISTRIBUTION LAYER PAD HAVING A VOID - An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer. | 2018-12-27 |
20180374770 | ELECTRICAL ASSEMBLY - An electrical assembly including a primary electrical component having a semiconductor device, a primary heat sink having the primary electrical component mounted thereon to provide a heat sink for said primary electrical component, a secondary electrical component electrically connected or coupled with the primary electrical component, a secondary heat sink having the secondary electrical component mounted thereon to provide a heat sink for said secondary electrical component, wherein the primary heat sink and the secondary heat sink are physically releasably couplable to one another and, when coupled, the primary and secondary heat sinks are thermally coupled by abutment of heat transfer surfaces of the primary and secondary heat sinks. | 2018-12-27 |
20180374771 | COMPLIANT HEAT SINK - A compliant heat sink for transporting heat away from at least one electronic component, the heat sink includes a body, where the body includes a flexible element thermally contacting at least one electronic component. The heat sink further includes a cavity located in the body, where the cavity is at least partially covered by the flexible element. The heat sink further includes a raised member of the body coupled to the flexible element, where a portion of the raised member partially extends into the cavity. The heat sink further includes a guiding structure of the body coupled in the cavity of the body, wherein the guiding structure is adapted for guiding the movement of the raised member in a moving direction. | 2018-12-27 |
20180374772 | SEMICONDUCTOR DEVICE - Provided is a technique for preventing warps of cooling plates due to a contraction of a joining material, thereby preventing a reduction in cooling performance of a semiconductor device. The semiconductor device includes the following: a first cooling plate; a second cooling plate facing the first cooling plate; a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and a case containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip. The semiconductor chip is mounted in a semiconductor-chip mounting part between the first cooling plate and the second cooling plate. The case is provided with a portion corresponding to the semiconductor-chip mounting part and to surroundings thereof. The portion has an up-and-down width greater than an up-and-down width of the remaining portions of the case. | 2018-12-27 |
20180374773 | HEAT SINK AND ELECTRONIC COMPONENT DEVICE - A heat sink may include: a flat plate portion; a first protruding portion which is formed on an outer peripheral portion of the flat plate portion so as to surround a central portion of the flat plate portion and which protrudes in a thickness direction of the flat plate portion; an extending portion which extends outward from the flat plate portion; and a second protruding portion which is formed on the extending portion such that the first protruding portion is positioned between the second protruding portion and the central portion of the flat plate and which protrudes in the thickness direction of the flat plate portion. | 2018-12-27 |
20180374774 | SEMICONDUCTOR DIE ASSEMBLY HAVING HEAT SPREADER THAT EXTENDS THROUGH UNDERLYING INTERPOSER AND RELATED TECHNOLOGY - A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations. | 2018-12-27 |
20180374775 | Electrical Device Having a Covering Material - An electrical device includes an electrical component that is at least partially covered by a covering material that includes a cement material. The covering material also includes particles having a first material and fibers having a second material. The first material and the second material each possess a higher coefficient of thermal conductivity than the cement of the cement material. | 2018-12-27 |
20180374776 | MULTIPLE-CHIP PACKAGE WITH MULTIPLE THERMAL INTERFACE MATERIALS - A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die. | 2018-12-27 |
20180374777 | HEAT DISSIPATION MODULE - A heat dissipation module configured to dissipate heat from a heat source of an electronic device is provided. The heat dissipation module includes a heat pipe, a plurality of fins, and a fan. One end of the heat pipe is in thermal contact with the heat source. The fins are stacked up to be combined with one another and structurally propped against another end of the heat pipe. The fins form a plurality of flow inlets and a plurality of flow outlets. The fan is disposed at the flow inlets, and air flow generated by the fan flows in via the flow inlets and flows out via the flow outlets. A portion of the fin at the flow outlet forms a bending, and a pitch between any adjacent fins at the bending is less than 1 mm to be qualified to achieve a safety certification. | 2018-12-27 |
20180374778 | FLOW PATH MEMBER AND SEMICONDUCTOR MODULE - A flow path member may include silicon nitride ceramics. The flow path member may have an inlet port, an outlet port, and a flow path connected to the inlet port and the outlet port inside the flow path member. A plurality of needle-shaped crystals may be arranged on a surface of the flow path where the needle-shaped crystals intersect each other. | 2018-12-27 |
20180374779 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction. | 2018-12-27 |
20180374780 | PROCESS FOR MANUFACTURING A FLIP CHIP SEMICONDUCTOR PACKAGE AND A CORRESPONDING FLIP CHIP PACKAGE - A process for manufacturing a semiconductor flip chip package and a corresponding flip chip package. The process comprises associating conducting bump pads to a face corresponding to an active side of one or more electronic dice, flipping the one or more electronic dice so that said face corresponding to an active side of one or more electronic dies is facing a leadframe carrying contacting pads in correspondence of said conducting bump pads, bonding said contacting pads to said conducting bump pads and encasing said one or more electronic dice in a casing by a molding operation. The process includes providing a leadframe having contacting pads presenting a recessed surface in correspondence of the position of said conducting bump pads. | 2018-12-27 |
20180374781 | LEAD PACKAGE AND METHOD FOR MINIMIZING DEFLECTION IN MICROELECTRONIC PACKAGING - Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package. | 2018-12-27 |
20180374782 | LEAD FRAME - A lead frame includes: a plurality of units each including a first lead portion and a second lead portion arranged in a first direction, wherein the units are arranged in the first direction and in a second direction perpendicular to the first direction, and the first lead portion and the second lead portion of each unit are adjacent, in the second direction, to the first lead portion and the second lead portion of an adjacent one of the units that is adjacent in the second direction; a plurality of first suspension portions; and a plurality of connecting portions. Each of the first suspension portions connects, in the second direction, the first lead portions of units that are adjacent to each other in the second direction. | 2018-12-27 |
20180374783 | INTEGRATED CIRCUIT PACKAGE WITH MULTI-DIE COMMUNICATION - An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller. | 2018-12-27 |
20180374784 | PACKAGE FOR AN ELECTRONIC COMPONENT, ELECTRONIC COMPONENT AND ELECTRONIC ARRANGEMENT - A package for an electronic component includes a housing and a leadframe embedded in the housing. The leadframe includes a first section, a second section and a third section which are electrically isolated from one another. The first section and the second section each include an L-shape. | 2018-12-27 |
20180374785 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D | 2018-12-27 |
20180374786 | FEEDTHROUGH ASSEMBLIES AND METHODS OF FORMING SAME - Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can include a non-conductive substrate and a feedthrough. The feedthrough can include a via from an outer surface to an inner surface of the non-conductive substrate, a conductive material disposed in the via, and an external contact disposed over the via on the outer surface of the non-conductive substrate. The external contact can be electrically coupled to the conductive material disposed in the via. And the external contact can be hermetically sealed to the outer surface of the non-conductive substrate by a bond surrounding the via. In one or more embodiments, the bond can be a laser bond. | 2018-12-27 |
20180374787 | SEMICONDUCTOR DEVICE - To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view. | 2018-12-27 |
20180374788 | SEMICONDUCTOR DEVICE - According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween. | 2018-12-27 |
20180374789 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE STRUCTURE - A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals. | 2018-12-27 |
20180374790 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE STRUCTURE - A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals. | 2018-12-27 |
20180374791 | BURIED POWER RAILS - Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail. | 2018-12-27 |
20180374792 | LAYOUT TECHNIQUE FOR MIDDLE-END-OF-LINE - In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact. | 2018-12-27 |
20180374793 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: first, second, and third tiers formed on a substrate, wherein the first tier is formed over the substrate, the second tier is formed over the first tier, and the third tier is formed over the second tier, wherein the second tier comprises a first interconnection line that is configured to transmit a signal, and wherein a portion of the first tier disposed directly under the first interconnection line of the second tier lacks any interconnection lines and a portion of the third tier disposed directly above the first interconnection line of the second tier lacks any interconnection lines. | 2018-12-27 |
20180374794 | SEMICONDUCTOR DEVICE AND AMPLIFIER CIRCUIT - In order to easily sort failures due to short circuit between wires in an inductor, a semiconductor device includes a plurality of inductors (first inductor, second inductor) formed in a plurality of wiring layers. In each of the wiring layers, the metal layer of the first inductor and the metal layer of the second inductor respectively extend around the peripheral region from the inner periphery to the outer periphery in the same direction. The metal layer of the first inductor and the metal layer of the second inductor are arranged so as to be adjacent to each other. | 2018-12-27 |
20180374795 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M | 2018-12-27 |
20180374796 | ELECTRONIC DEVICES WITH YIELDING SUBSTRATES - In accordance with certain embodiments, a light-emitting element composed of one or more discrete units configured for light emission is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the light-emitting element or non-coplanarity of the semiconductor die contacts. | 2018-12-27 |
20180374797 | INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME - An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided. | 2018-12-27 |
20180374798 | SEMICONDUCTOR DEVICE HAVING EMI SHIELDING STRUCTURE AND RELATED METHODS - An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package. In another embodiment, the electrical connection is made through the substrate. | 2018-12-27 |
20180374799 | ELECTRONIC CIRCUIT PACKAGE USING COMPOSITE MAGNETIC SEALING MATERIAL - Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, an electronic component mounted on a surface of the substrate, and a composite molding member having conductivity that covers the surface of the substrate so as to embed the electronic component and that is connected to the power supply pattern. The composite molding member includes a resin material and a first filler blended in the resin material and containing 32 to 39 wt. % of a metal material composed mainly of Ni in Fe. | 2018-12-27 |
20180374800 | EMBEDDED VIBRATION MANAGEMENT SYSTEM - Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by forming an array of vibration absorbing structures, placing the array proximate to a leadframe comprising two-legged supported leads, placing a semiconductor device above the leadframe, and encapsulating the semiconductor device and the leadframe. Each vibration absorbing structure may comprise a mass element formed on a material with lower density than that of the mass element. The array may be placed on a top, a bottom, or both surfaces of the leadframe. Sections of the array may be placed symmetrically with respect to the semiconductor device. The vibration absorbing structures may be cubic in shape and may be enclosed in an encapsulating material. The two-legged supported leads may be formed by bending metal strips with holes. The vibration absorbing structures may be exposed to the exterior of the semiconductor package. | 2018-12-27 |
20180374801 | Wafer Level Package (WLP) and Method for Forming the Same - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure. | 2018-12-27 |
20180374802 | INDUCTOR STRUCTURE MOUNTED ON PCB BOARD AND VOLTAGE REGULATOR MODULE HAVING THE SAME - The present disclosure discloses an inductor structure mounted on a PCB board and a voltage regulator module having the same. The inductor structure includes inductor cores and inductor windings. The PCB board is provided with at least one hollow part, and the hollow part comprises a plurality of through holes spaced apart. The legs of the inductor cores are correspondingly inserted into the through holes at the corresponding positions of the hollow part, wherein any two adjacent through holes of the plurality of through holes have a spacer therebetween for use as the inductor winding of the inductor structure, and the thickness of the spacer is less than the thickness of the PCB board. | 2018-12-27 |
20180374803 | WIRING SUBSTRATE - A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure. | 2018-12-27 |
20180374804 | GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION LINES ROUTED THROUGH PACKAGE DEVICES - A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device. | 2018-12-27 |
20180374805 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element. | 2018-12-27 |
20180374806 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed. | 2018-12-27 |
20180374807 | System and Method for an Improved Interconnect Structure - Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm. | 2018-12-27 |
20180374808 | Semiconductor Package - A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. | 2018-12-27 |
20180374809 | INTEGRATED CIRCUIT SYSTEM WITH CARRIER CONSTRUCTION CONFIGURATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure. | 2018-12-27 |
20180374810 | BONDING PADS WITH THERMAL PATHWAYS - Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate. | 2018-12-27 |
20180374811 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME - At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path. | 2018-12-27 |
20180374812 | METHOD OF FORMING SOLDER BUMPS - A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer. | 2018-12-27 |
20180374813 | ASSEMBLY COMPRISING HYBRID INTERCONNECTING MEANS INCLUDING INTERMEDIATE INTERCONNECTING ELEMENTS AND SINTERED METAL JOINTS, AND MANUFACTURING PROCESS - An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided. | 2018-12-27 |
20180374814 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease. | 2018-12-27 |
20180374815 | BONDING WIRE FOR SEMICONDUCTOR DEVICE - A bonding wire for a semiconductor device, which is suitable for on-vehicle devices bonding wire, has excellent capillary wear resistance and surface flaw resistance while ensuring high bonding reliability and further satisfies overall performance including ball formability and wedge bondability, the bonding wire including: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer, in which the bonding wire for semiconductor device contains Ni, a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. %, the Pd coating layer is 0.015 to 0.150 μm in thickness, and the Cu surface layer is 0.0005 to 0.0070 μm in thickness. | 2018-12-27 |
20180374816 | BONDING WIRE FOR SEMICONDUCTOR DEVICES - The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape. | 2018-12-27 |
20180374817 | SEMICONDUCTOR APPARATUS - According to the present invention, a semiconductor apparatus includes a semiconductor device, a case surrounding the semiconductor device, a spring terminal including a first connection portion extending to a top surface of the case, and a second connection portion provided on the top surface of the case and a control substrate provided on the second connection portion, wherein the first connection portion is connected to the semiconductor device, the second connection portion includes a first end connected to an end of the first connection portion, and a second end opposite to the first end, the second connection portion being a flat plate and having an elastic force using the first end as a supporting point, the second end contacts the control substrate with an elastic force, and the second connection portion has a constriction structure having a notch formed in a side surface along a longitudinal direction. | 2018-12-27 |