52nd week of 2012 patent applcation highlights part 47 |
Patent application number | Title | Published |
20120329218 | METHOD FOR MANUFACTURING SEMICONDUCTOR FIELD EFFECT TRANSISTOR - The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs. | 2012-12-27 |
20120329219 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate. | 2012-12-27 |
20120329220 | Method of Improving Memory Cell Device by Ion Implantation - Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer. | 2012-12-27 |
20120329221 | Semiconductor Device Having an Enhanced Well Region - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region. | 2012-12-27 |
20120329222 | PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME - A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element. | 2012-12-27 |
20120329223 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - In a semiconductor storage device a select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction. | 2012-12-27 |
20120329224 | METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of forming a fine pattern and a method of manufacturing a semiconductor device. The method of forming a fine pattern includes: forming a hard mask layer on a to-be-etched layer; forming on the hard mask layer a first mask pattern including a plurality of elongated openings that are arranged at predetermined intervals in a first direction and a second direction different from the first direction and are offset from each other in adjacent columns in the second direction; forming on the hard mask layer a second mask pattern including at least two linear openings that each pass through the elongated openings in the adjacent columns and extend in the first direction; forming a hard mask pattern by etching the hard mask layer by using the second mask pattern as an etch mask; and etching the to-be-etched layer by using the hard mask pattern. | 2012-12-27 |
20120329225 | POWER MOS DEVICE FABRICATION - Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug. | 2012-12-27 |
20120329226 | LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES - There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation. | 2012-12-27 |
20120329227 | Formation of Field Effect Transistor Devices - A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks. | 2012-12-27 |
20120329228 | METHOD FOR FORMING A STRAINED SEMICONDUCTOR CHANNEL - The invention relates to a method of forming a strained semiconductor channel. According to the invention, a strained channel is formed after the annealing of source/drain, by which it does not only avoid the strained semiconductor channel from being exposed to the high-temperature source/drain annealing process, but also avoid a loss of the semiconductor layer since it reduces the number of processing steps that the strained semiconductor channel has to experience. Besides, because the etching rate of the ion implantation region is significantly greater than the etching rate of the surrounding portion of the relaxed layer into which no ions are implanted, the etching depth can be easily controlled. | 2012-12-27 |
20120329229 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer. | 2012-12-27 |
20120329230 | FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS - A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å. | 2012-12-27 |
20120329231 | Semiconductor Processing Methods, And Methods Of Forming Isolation Structures - Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline. | 2012-12-27 |
20120329232 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 2012-12-27 |
20120329233 | WAFER TREATMENT METHOD AND FABRICATING METHOD OF MOS TRANSISTOR - A wafer treatment method includes the following steps. A wafer is provided, wherein the wafer includes a substrate, a first oxide layer located on a front side of the substrate and a second oxide layer located on a back side of the substrate. An etching process is performed to entirely remove the first oxide layer. A fabricating method of a MOS transistor applying the wafer treatment method is also provided. | 2012-12-27 |
20120329234 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A COBALT SILICIDE - A method includes forming a gate over a substrate having a semiconductor layer comprising silicon. The gate has a sidewall spacer on sides of the gate. The gate has a gate length less than or equal to 50 nanometers. The gate is formed of polysilicon. A cobalt layer is formed on a top of the gate and the sidewall spacer. A titanium nitride layer is formed on the cobalt layer. The titanium nitride layer has a thickness over the gate in a range of 10 to 14 nanometers. An anneal is performed to form a cobalt silicide layer on the top of the gate and leave cobalt on the sidewall spacer. An etchant is applied that etches cobalt and titanium nitride selective to cobalt silicide to the titanium nitride layer. The cobalt is on the sidewall spacer and the cobalt silicide layer. An anneal is performed to increase conductivity of the cobalt silicide layer. | 2012-12-27 |
20120329235 | WET ETCH AND CLEAN CHEMISTRIES FOR MoOx - A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoO | 2012-12-27 |
20120329236 | METHOD OF MANUFACTURING DEVICE - A method of manufacturing a device includes: forming a fifth insulating film on a semiconductor substrate having a peripheral circuit region and a memory cell region in which a contact pad is formed; forming a second sacrifice film in the memory cell region in which the fifth insulating film is formed; forming, after the forming of the second sacrifice, a second insulating film in the peripheral circuit region on the semiconductor substrate to have a sidewall coming into contact with the second sacrifice film; forming a third insulating film to cover an upper surface of the second sacrifice film and an upper surface of the second insulating film; forming a hole penetrating through the third insulating film, the second sacrifice film and the fifth insulating film in the memory cell region; forming a lower electrode in the hole; and removing all of the second sacrifice film. | 2012-12-27 |
20120329237 | Memory Device - A phase-change memory device includes a first insulator having a hole therethrough, a first electrode that conforms at least partially to the hole, a phase-change material in electrical communication with the first electrode, and a second electrode in electrical communication with the phase-change material. When current is passed from the first electrode to the second electrode through the phase-change material, at least one of the first and second electrodes remains unreactive with the phase change material. | 2012-12-27 |
20120329238 | Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 2012-12-27 |
20120329239 | METHODS OF FABRICATING A SEMICONDUCTOR IC HAVING A HARDENED SHALLOW TRENCH ISOLATION (STI) - Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed. | 2012-12-27 |
20120329240 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor. | 2012-12-27 |
20120329241 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates. | 2012-12-27 |
20120329242 | METHOD FOR REPROCESSING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING REPROCESSED SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SOI SUBSTRATE - A method suitable to reprocess a semiconductor substrate is provided. A semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer is provided in a peripheral portion of the semiconductor substrate is subjected to etching treatment for removing the insulating layer and to etching treatment for removing the damaged semiconductor region selectively with a non-damaged semiconductor region left using a mixed solution including nitric acid, a substance dissolving a semiconductor material included in the semiconductor substrate and oxidized by the nitric acid, a substance controlling a speed of oxidation of the semiconductor material and a speed of dissolution of the oxidized semiconductor material, and nitrous acid, in which the concentration of the nitrous acid is higher than or equal to 10 mg/l and lower than or equal to 1000 mg/l. Through these steps, the semiconductor substrate is reprocessed. | 2012-12-27 |
20120329243 | PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE EMPLOYING A TEMPORARY BOND - The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate. | 2012-12-27 |
20120329244 | Capping Coating for 3D Integration Applications - A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits. | 2012-12-27 |
20120329245 | Group III Nitride Crystal and Method for Producing the Same - A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates | 2012-12-27 |
20120329246 | ETCHING A LASER-CUT SEMICONDUCTOR BEFORE DICING A DIE ATTACH FILM (DAF) OR OTHER MATERIAL LAYER - Semiconductor die break strength and yield are improved with a combination of laser dicing and etching, which are followed by dicing an underlying layer of material, such as die attach film (DAF) or metal. A second laser process or a second etch process may be used for dicing of the underlying layer of material. Performing sidewall etching before cutting the underlying layer of material reduces or prevents debris on the kerf sidewalls during the sidewall etching process. A thin wafer dicing laser system may include either a single laser process head solution or a dual laser process head solution to meet throughput requirements. | 2012-12-27 |
20120329247 | LASER PROCESSING METHOD - For modulating laser light for forming a modified region SD | 2012-12-27 |
20120329248 | METHOD OF CUTTING SEMICONDUCTOR SUBSTRATE - Multiphoton absorption is generated, so as to form a part which is intended to be cut | 2012-12-27 |
20120329249 | METHODS OF PROCESSING SUBSTRATES - Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force. | 2012-12-27 |
20120329250 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device wherein the space between semiconductor elements that are three-dimensionally mounted can be filled easily and securely. The method of manufacturing a semiconductor device of the present invention includes preparing a semiconductor wafer with a plurality of members for connection formed on both first and second surfaces; preparing a laminated film including a dicing sheet with a pressure-sensitive adhesive layer laminated on a base material, and a curable film that is laminated on the pressure-sensitive adhesive layer and has a thickness equivalent to or more than the height of the member for connection on the first surface; pasting the curable film of the laminated film to the semiconductor wafer while facing the curable film to the first surface so that the members for connection are not exposed to the pressure-sensitive adhesive layer; and dicing the semiconductor wafer to form a semiconductor element. | 2012-12-27 |
20120329251 | DOPED ELONGATED SEMICONDUCTORS, GROWING SUCH SEMICONDUCTORS, DEVICES INCLUDING SUCH SEMICONDUCTORS AND FABRICATING SUCH DEVICES - A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications. | 2012-12-27 |
20120329252 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate with an active region, a gate line disposed on the active region, an epitaxial pattern disposed on the semiconductor substrate beside the gate line, the epitaxial pattern including a semiconductor material different from the semiconductor substrate, and a capping pattern disposed on the epitaxial pattern. The capping pattern may improve contact with contact plug and may reduce variation in mean ion depths of an associated field effect transistor. | 2012-12-27 |
20120329253 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires. | 2012-12-27 |
20120329254 | Method for Forming Antimony-Based FETs Monolithically - An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer. | 2012-12-27 |
20120329255 | OUT-OF-PLANE MEMS RESONATOR WITH STATIC OUT-OF-PLANE DEFLECTION - A method of forming a microelectromechanical systems (MEMS) device includes forming an electrode on a substrate. The method includes forming a structural layer on the substrate. The structural layer is disposed about a perimeter of the electrode and has a residual film stress gradient. The method includes releasing the structural layer to form a resonator coupled to the substrate. The residual film stress gradient deflects a first portion of the resonator out of a plane defined by a surface of the electrode. | 2012-12-27 |
20120329256 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ION IMPLANTER - According to an embodiment, a method of manufacturing a semiconductor device is provided. This method of manufacturing a semiconductor device sets a first voltage to be applied to an electrode configured to extract an ion beam from an ion source, and a second voltage to be applied to a decelerator through which an ion beam extracted from the ion source is to pass, on the basis of a second impurity profile which is formed in a substrate by neutral particles included in the ion beam. | 2012-12-27 |
20120329257 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, the method including forming a front face structure of a semiconductor device on a first main face of a semiconductor substrate, grinding a second main face of the semiconductor substrate and reducing the semiconductor substrate in thickness to a thickness equal to or less than 100 μm, ion implanting a dopant into the second main face of the semiconductor substrate of reduced thickness, and activating the dopant by irradiating the second main face with laser light and performing laser annealing while the semiconductor substrate of reduced thickness is heated. | 2012-12-27 |
20120329258 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH - Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width. | 2012-12-27 |
20120329259 | METHOD FOR FABRICATING METAL-OXIDE- SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed. | 2012-12-27 |
20120329260 | GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance. | 2012-12-27 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 2012-12-27 |
20120329262 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES - A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper. | 2012-12-27 |
20120329263 | METHOD OF FORMING A BOND PAD DESIGN FOR IMPROVED ROUTING AND REDUCED PACKAGE STRESS - A method for the fabrication of a semiconductor chip, comprises forming one or more semiconductor devices on a substrate; forming a passivation layer on the substrate; forming a plurality of bond pads on the passivation layer; and forming a plurality of under-bump metallurgy (UBM) layers on respective ones of the plurality of bond pads, wherein at least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center of the chip to the periphery thereof. | 2012-12-27 |
20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 2012-12-27 |
20120329265 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 2012-12-27 |
20120329266 | LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning. | 2012-12-27 |
20120329267 | Interconnect structures and methods for back end of the line integration - A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. | 2012-12-27 |
20120329268 | METHOD OF MAKING A SEMICONDUCTOR DEVICE - An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized. | 2012-12-27 |
20120329269 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 2012-12-27 |
20120329270 | SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material. | 2012-12-27 |
20120329271 | DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION - A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform. | 2012-12-27 |
20120329272 | METHOD FOR FORMING SMALL DIMENSION OPENINGS IN THE ORGANIC MASKING LAYER OF TRI-LAYER LITHOGRAPHY - A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon. | 2012-12-27 |
20120329273 | HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS - In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature. | 2012-12-27 |
20120329274 | METHOD OF FABRICATING A CELL CONTACT AND A DIGIT LINE FOR A SEMICONDUCTOR DEVICE - The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line. | 2012-12-27 |
20120329275 | BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS - A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. | 2012-12-27 |
20120329276 | METHOD FOR MANUFACTURING A THROUGH HOLE ELECTRODE SUBSTRATE - To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer. | 2012-12-27 |
20120329277 | TWO-SIDED SEMICONDUCTOR STRUCTURE - Deep via trenches and deep marker trenches are formed in a bulk substrate and filled with a conductive material to form deep conductive vias and deep marker vias. At least one first semiconductor device is formed on the first surface of the bulk substrate. A disposable dielectric capping layer and a disposable material layer are formed over the first surface of the bulk substrate. The second surface, located on the opposite side of the first surface, of the bulk substrate is polished to expose and planarize the deep conductive vias and deep marker vias, which become through-substrate vias and through-substrate alignment markers, respectively. At least one second semiconductor device and second metal interconnect structures are formed on the second surface of the bulk substrate. The disposable material layer and the disposable dielectric capping layer are removed and first metal interconnect structures are formed on the first surface. | 2012-12-27 |
20120329278 | DISPENSER FOR CHEMICAL-MECHANICAL POLISHING (CMP) APPARATUS, CMP APPARATUS HAVING THE DISPENSER, AND CMP PROCESS USING THE CMP APPARATUS - A dispenser for a chemical-mechanical polishing (CMP) apparatus, includes a delivery arm disposed over a polishing pad of a CMP apparatus, at least a slurry delivery groove formed in the delivery arm and extending along a length of the delivery arm, and a plurality of first openings connected to the slurry delivery groove. | 2012-12-27 |
20120329279 | CMP Slurry/Method for Polishing Ruthenium and Other Films - A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates. | 2012-12-27 |
20120329280 | METHOD FOR FORMING PHOTORESIST PATTERNS - A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index. | 2012-12-27 |
20120329281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A shape defect in a transfer pattern formed over the major surface of a substrate is prevented by using an immersion exposure method. When exposure light is radiated onto a resist, immersion water is held in a first immersion area between each of the lower surfaces of an optical element of a projection optical system and a nozzle portion, and a resist; and when a focus, optical system alignment, or the like, is regulated, the immersion water is held in a second immersion area between each of the lower surfaces of the optical element of the projection optical system and the nozzle portion, and the upper surface of a measurement stage. A transverse spread of the immersion water held in the first immersion area is made smaller than that of the immersion water held in the second immersion area. | 2012-12-27 |
20120329282 | METHOD AND MATERIAL FOR FORMING A DOUBLE EXPOSURE LITHOGRAPHY PATTERN - Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension. | 2012-12-27 |
20120329283 | MULTIPLE GAS PLASMA FORMING METHOD AND ICP SOURCE - Different gases are separately exposed to RF energy in different zones in inlets to a processing chamber. Plasma is activated in the gases in each of the zones separately and the activated gases are then introduced into the plasma processing chamber where they may undergo mutual interaction within a processing zone. Control of the active species distribution within the processing chamber is provided by control of the energizing of the gases in the separate inlet zones before they are combined in the processing zone. An ICP source energizes gas in each zone through an antenna having one or more conductors, each of which is coupled to a plurality of the zones. This allows gases to be brought together in their active states, rather than being combined and then activated, and allows the same or different parameters to be applied in different inlet zones. | 2012-12-27 |
20120329284 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND METHOD FOR REDUCING MICROROUGHNESS OF SEMICONDUCTOR SURFACE - Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved. | 2012-12-27 |
20120329285 | GATE DIELECTRIC LAYER FORMING METHOD - A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas. | 2012-12-27 |
20120329286 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - A semiconductor device manufacturing method includes: accommodating a substrate in a processing chamber; and supplying a silicon-based gas and an amine-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. The forming of the film including silicon and carbon includes: supplying the silicon-based gas and the amine-based gas into the processing chamber and confining the silicon-based gas and the amine-based gas in the processing chamber; maintaining a state in which the silicon-based gas and the amine-based gas are confined in the processing chamber, and exhausting an inside of the processing chamber. | 2012-12-27 |
20120329287 | LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT - A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CH | 2012-12-27 |
20120329288 | Method and System for Pre-heating of Semiconductor Material for Laser Annealing and Gas Immersion Laser Doping - A fiber laser system enables a method for treating a semiconductor material by preheating a wafer for laser annealing and gas immersion laser doping by a laser source. A long wave length fiber laser having a Gaussian or similar profile is applied in a full-width ribbon beam across an incident wafer. Preferably the wavelength is greater than 1 μm (micron) and preferably a Yb doped fiber laser is used. The process is performed in a suitable environment which may include doping species. The process ensures the temperature gradient arising during processing does not exceed a value that results in fracture of the wafer while also reducing the amount of laser radiation required to achieve controlled surface melting, recrystallization and cooling. | 2012-12-27 |
20120329289 | Method and System for Forming Patterns with Charged Particle Beam Lithography - In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (β | 2012-12-27 |
20120329290 | Substrate Placement Stage, Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device - Provided is a substrate placement stage or substrate processing apparatus which can suppress thermal deformation of the substrate placement stage when the substrate placement stage on which a substrate is placed is heated in a process chamber. The substrate placement stage includes: a heating element; a first member surrounding the heating element; and a second member covering a surface of the first member and including a placing surface for placing a substrate thereon, wherein the first member is made of a first material containing ceramics and aluminum, and the second member is made of a second material containing ceramics and aluminum, a content of the ceramics in the second material being lower than that of the first material. | 2012-12-27 |
20120329291 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS - A substrate holder has two holder constituting bodies, each having a plurality of columns arranged on an imaginary circle, and substrate holding sections that hold circumferential portions of respective substrates. The holder constituting bodies hold the substrates so that either their front surfaces or their back surfaces face upward with a substrate having an upward facing front and a substrate having an upward facing rear being alternately arranged in a vertical direction. At least one of the holder constituting bodies moves in the vertical direction to change the positions of the holder constituting bodies relative to each other. A distance between a first pair of vertically adjacent substrates with their respective front surfaces facing each other is set to ensure treatment uniformity, and to be larger than a distance between a second pair of vertically adjacent substrates with their respective back surfaces facing each other. | 2012-12-27 |
20120329292 | MULTIPLE-APPLICATION ATTACHMENT MECHANISM FOR CONSUMER ELECTRONIC DEVICES - A portable computing device may include a set of magnetic elements and a set of electrical contacts. An electronic device may include a sensor may also include a set of magnetic elements and a set of electrical contacts. The portable computing device may attach to the electronic device using the set of magnetic elements and may exchange data with the electronic device using the set of electrical contacts. A power source may also include a set of magnetic elements and a set of electrical contacts. The power source may couple with the portable computing device using the set of magnetic elements and may provide power to the portable computing device using the electrical contacts. | 2012-12-27 |
20120329293 | MAGNETIC CONNECTION CABLE - A magnetic connection cable is composed of a main body and two magnets mounted to the main body. The main body includes a first end portion and a second end portion opposite to the first end. The two magnets are mounted to the first and second end potions separately. The first and second end portions of the magnetic connection cable can magnetically attract each other for convenient storage and effective reduction of the size of the connection cable in storage to overcome the drawback of the prior art. Besides, the connection cable of the present invention with the magnetic attraction can function as a general magnetic fastener for fastening an object, like paper, to the surface of a magnetically attractable object. | 2012-12-27 |
20120329294 | POWER CONNECTORS AND ELECTRICAL CONNECTOR ASSEMBLIES AND SYSTEMS HAVING THE SAME - A power connector including a connector housing having an interior cavity and a mating face. The connector housing is configured to be mounted to a circuit board. The power connector also includes a contact assembly that has anode and cathode contacts that are configured to electrically engage power contacts of a mating connector. The contact assembly also includes anode and cathode terminals that are disposed in the interior cavity. The anode and cathode terminals are electrically coupled to the anode and cathode contacts, respectively, and are configured to be electrically coupled to the circuit board. The power connector also includes a power cable that has substantially flat anode and cathode conductive layers that are surrounded by an insulative jacket. The anode and cathode conductive layers are electrically coupled to the anode and cathode contacts, respectively, and are electrically parallel to the anode and cathode terminals, respectively. | 2012-12-27 |
20120329295 | High Performance Compliant Wafer Test Probe - An electrical connection includes a first electrical contact made of electrically conductive material. The first electrical contact is formed with a depression therein. Also included are a deformable pad, having a Young's modulus of less than 1,000,000 psi, which bears on the first contact; and a second electrical contact, made of electrically conductive material, which contacts the first electrical contact and is at least partially received into the depression. The deformable pad at least partially causes at least one lateral force on the first electrical contact, so as to induce the first electrical contact to make an electrical connection with the second electrical contact. An array of such contacts is also contemplated, as is an array of cantilevered contacts, which may or may not have depressions, and which are supported by at least one elastomeric pad, having a Young's modulus of less 72,500 psi. | 2012-12-27 |
20120329296 | ELECTRIC JUNCTION BOX - An electric junction box to prevent stress from working at a junction of conductive pattern of a connector terminal mounted on a printed wiring board and curtail its size, comprises, a printed wiring board, a connector including a terminal connected with a conductive pattern on the printed wiring board, and a connector housing accommodating the terminal, and a cover adapted to receive the printed wiring board therein and including a hole disposed on an outer wall of the cover and passing the connector therethrough. The lower cover is provided with a support adapted to overlap with a part of an edge of the connector housing surrounding the terminal, and position the part between the printed wiring board and the support. | 2012-12-27 |
20120329297 | TERMINAL AND CONNECTOR ASSEMBLY - A connector assembly is provided with a body that extends along a lateral length with a longitudinal height defined by a first body surface and an opposing second body surface. A locking terminal extends through the body and includes an elongate blade having a distal end for electrically connecting to a mating connector and a proximal end adapted to electrically connect to an electronic component with an aperture. At least one tab extends lengthwise from an intermediate portion of the blade and extends through the electronic component aperture. A projection extends outward from the tab such that the projection interferes with the aperture during insertion of the tab therethrough for deforming the tab. After insertion, the tab returns from the deformation and engages the projection to the electronic component for retaining the tab within the aperture. | 2012-12-27 |
20120329298 | ELECTRICAL CONNECTOR - An electrical connector is provided including a connector sub-assembly having a stamped and formed outer contact. A dielectric insert is positioned within the outer contact. A center contact extends through the dielectric insert. A ground contact tab extends from the connector sub-assembly and is configured to ground to a substrate. The ground contact tab is configured for one of through-hole mounting or surface mounting to the substrate. An interface housing receives the connector sub-assembly. A rear housing is coupled to the interface housing. The connector sub-assembly is captured between the interface housing and the rear housing. The rear housing is coupled to the substrate to secure the interface housing to the substrate. The rear housing is configured for one of through-hole mounting or surface mounting to the substrate. | 2012-12-27 |
20120329299 | CONNECTOR AND CONNECTOR ASSEMBLY - A female connector (F) is formed such that a block-shaped terminal accommodating portion ( | 2012-12-27 |
20120329300 | ELECTRICAL CONNECTOR - An electrical connector including a housing having an opening through which a flat circuit device is inserted into the housing, conductive contacts arranged on the housing, a conductive shell provided with a holding member for engaging with the flat circuit device to hold the same, and a releasing member provided on the housing with a manipulatable portion and a pressing portion for engaging with the holding member, wherein the manipulatable portion is formed to be movable in a direction along which the conductive contacts are arranged and the pressing portion is operative to move for pressing the holding member so as to cause the same to disengage from the flat circuit device when the manipulatable portion is moved in the direction along which the conductive contacts are arranged under a condition wherein the holding member is put in engagement with the flat circuit device to hold the same. | 2012-12-27 |
20120329301 | CARD EDGE CONNECTOR HAVING IMPROVED EJECTOR - A card edge connector ( | 2012-12-27 |
20120329302 | ELECTRICAL CONNECTOR - An electrical connector comprises a first connector element ( | 2012-12-27 |
20120329303 | WATERPROOF SOCKET AND ILLUMINATION APPARATUS - A waterproof socket includes a socket body having an insertion hole to which a lamp pin protruding from an end cap of a straight tube lamp is inserted, a first internal sleeve making contact with the socket body, and a second internal sleeve. The socket body includes a body-side rotation restraint portion engaging with a sleeve-side rotation restraint portion formed in the first internal sleeve to restrain the first internal sleeve from rotating about a center axis of the straight tube lamp. The first internal sleeve includes a first position restraint portion and the second internal sleeve includes a second position restraint portion engaging with the first position restraint portion to restrain the second internal sleeve from rotating about the center axis while allowing the second internal sleeve to move in an axial direction of the straight tube lamp. | 2012-12-27 |
20120329304 | RELEASABLE ELECTRICAL CONNECTOR ADAPTOR AND ASSEMBLY - Disclosed is an electrical connector adaptor, an electrical assembly, and a process of connecting an electrical assembly. The electrical connector adaptor includes a housing, a mechanical latch positioned on the housing, terminals arranged and disposed within the housing, and a terminal retention device configured to retain the terminals within the housing. The mechanical latch is configured to releasably secure the housing to a first electrical connector. The electrical connector adaptor permits electrical connection between the first electrical connector and a second electrical connector, the first electrical connector and the second electrical connector being otherwise incompatible. | 2012-12-27 |
20120329305 | ACTUATOR FOR A CONNECTOR - A cable connector is provided including a cable end to couple to a cable, and a mating end to couple to a corresponding connector. A latch is positioned proximate to the mating end to secure the cable connector to the corresponding connector. The latch is moveable between an open position and a closed position. An actuator is provided to move the latch between the open position and the closed position. The actuator includes a biasing end that engages the latch. The actuator also includes an operating end extending from the cable end to receive an opening force that moves the biasing end to operate the latch. The operating end has an upper tab and a lower tab. The upper tab extends along an upper portion of the cable. The lower tab extends along a lower portion of the cable. | 2012-12-27 |
20120329306 | CARD CONNECTOR - A card connector includes a main housing having a base portion, a pair of side walls and a bottom wall connecting with said base portion and side walls thereby defining a receiving cavity therebetween. A multiple groups of contact sets comprise contacting portions projecting into the receiving cavity. A metallic shell covers a top side of the main housing and defines an insertion opening together with the main housing at a front end thereof. A pair of guiders are floatably assembled on the bottom wall and respectively located beside the side walls. Each guider has a spring member disposed thereunder. A pair of locking devices are located at opposite sides of the insertion opening. Each locking device has a stopping section detachably supporting the guider under so as to prevent unmated card to be inserted. | 2012-12-27 |
20120329307 | CONNECTOR - A connector includes a movable contact part formed of an insulating material, an electrically conductive movable terminal part, and an electrically conductive fixed terminal part. The movable terminal part and the fixed terminal part are caused to come into contact by the movable terminal part being pressed via the movable contact part by an electrically conductive plug electrode terminal of another connector after the plug electrode terminal inserted into a jack terminal opening part of the connector comes into contact with the movable terminal part, so that the plug electrode terminal and the fixed terminal part are electrically connected via the movable terminal part. | 2012-12-27 |
20120329308 | CONNECTOR TERMINAL - A connector terminal includes a main body having at least one contact section extended from a first end of the main body; a first cable connecting unit horizontally located above an opposite second end of the main body; and a second cable connecting unit vertically extended from an end of the first cable connecting unit in a direction opposite to the main body. With the above structure, the connector terminal can be used with either a 90-degree connector or a 180-degree connector, and to electrically connect cables to the 90-degree connector via the first cable connecting unit or to the 180-degree connector via the second cable connecting unit. Therefore, the connector terminal provides good applicability, and the costs for manufacturing and storing connector terminals can be reduced. | 2012-12-27 |
20120329309 | Solar Insulation Displacement Connector - In one embodiment, a solar insulation displacement connector (IDC) is described. The example solar IDC includes a base configured with at least one pathway. The pathway may include a plurality of ridges. At least one pathway is configured with at least one conductive cutter. The conductive cutter is formed from a conductive material (e.g., copper, silver, gold, nickel, brass). The example solar IDC includes a cover configured to hold a wire in the at least one pathway when the cover is affixed to the base of the solar IDC. The solar IDC is configured to be mechanically connected to a conductor of the wire by the at least one conductive cutter. The at least one conductive cutter is configured to cut an insulation of the wire. An inverter is operably connected to the solar IDC. The example solar IDC and the inverter are fabricated as a unit. | 2012-12-27 |
20120329310 | Electrical Device with Power Cord Insert - An electrical device including an electrical power cord secured to a base of the electrical device by using a plug having a pair of resilient prongs. The plug is inserted into an opening in the base to secure a strain reliever on an end of the electrical power cord into the opening. The resilient prongs flex towards each other when the plug is inserted into the opening. The prongs return to their original positions after passing through the opening and seat the plug in the opening. When seated, the plug secures the strain reliever into the opening thereby securing the electrical power cord to the base. | 2012-12-27 |
20120329311 | CABLE CONNECTOR WITH BUSHING ELEMENT - A cable connector for receiving a cable includes a substantially tubular connector body having a central bore extending therethrough, a forward end, and a cable receiving end. A gland nut is coupled to the cable receiving end of the connector body, wherein the gland nut is axially movable from a first position relative to the connector body to a second position relative to the connector body. A substantially tubular bushing element is secured between the gland nut and the connector body, wherein the bushing element comprises a tubular body for receiving the cable therethrough. The tubular body of the bushing element includes a flexible portion and a semi-rigid portion, wherein the flexible portion comprises a first hardness to seal the flexible portion to the cable and the semi-rigid portion comprises a second hardness to securely fix the cable relative to the bushing element. | 2012-12-27 |
20120329312 | CONNECTOR - A connector includes an electric cable, an electric connecting portion that includes a case body in a rectangular shape and a circuit board, and has, on the circuit board, a line connecting portion electrically connected to a line of the electric cable, and a cable fixing portion to which the electric cable is fixed, a flat-type connector case that has a housing space housing the electric connecting portion and the electric cable, an opening in which the case body is integrally mounted, and an extension hole from which the electric cable is extended into the housing space, and is fixed to an intermediate portion of the electric cable, and a slide member that is slidably disposed in the housing space, and includes, on one surface side, a cable bending shape defining portion that defines a bending shape of the electric cable which is housed in the housing space. | 2012-12-27 |
20120329313 | PORTABLE ELECTRONIC DEVICE WITH INTERFACE - An interface assembly includes a connector housing and a light emitting element. The connector housing defines a opening. The light emitting element is retained to the connector housing and illuminates the opening. | 2012-12-27 |
20120329314 | ROTATING CONNECTOR DEVICE - A rotary connector device includes a stator, a rotator rotatable relative to the stator, a base ring arranged between the stator and the rotator, a flexible flat cable ( | 2012-12-27 |
20120329315 | JUMPER AND JUMPER TERMINAL ARRANGEMENT - A jumper for a connecting terminal arrangement ( | 2012-12-27 |
20120329316 | CABLE ASSEMBLY WITH A FLOATING CONNECTOR - A cable assembly ( | 2012-12-27 |
20120329317 | CONNECTION STRUCTURE OF CRIMPING TERMINAL TO ELECTRICAL WIRE - An upper side of the distal end of an electric wire is covered with cover members made of water-absorbing resin layers in which impermeable layers are formed on the inner surface sides abutting on a conductor before crimping previously so as to include at least a portion having the possibility of exposing the conductor of the electric wire to the outside when a conductor crimping part and a sheath crimping part of a crimping terminal are respectively crimped to the conductor and the portion having an insulating sheath of the distal end of the electric wire, and conductor crimping pieces and sheath crimping pieces are crimped onto the cover members and thereby, the cover members are held by the conductor crimping pieces and the sheath crimping pieces with an exposed portion of the conductor covered. | 2012-12-27 |