52nd week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140374746 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING SAME - A thin film transistor (TFT) includes a gate, a drain, a source, an insulating layer, a metal oxide layer, and an etch stopper layer. The metal oxide layer includes a source area, a drain area, and a channel area. The source is electrically coupled to the source area and the drain is electrically coupled to the drain area. Oxygen ions are implanted into the channel area via a surface treatment process to make an oxygen concentration of the channel area be greater than an oxygen concentration of each of the source area and the drain area. | 2014-12-25 |
20140374747 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with excellent charge retention characteristics, a transistor including a thick gate insulating film to achieve low leakage current is additionally provided such that its gate is connected to a node for holding charge. The node is composed of this additional transistor and a transistor using an oxide semiconductor in its semiconductor layer including a channel formation region. Charge corresponding to data is held at the node. | 2014-12-25 |
20140374748 | LIGHT EMITTING DIODES HAVING ZINC OXIDE FIBERS OVER SILICON SUBSTRATES - Semiconductor devices useful as light emitting diodes or power transistors are provided. The devices produced by depositing a Zn—O-based layer comprising nanostructures on a Si-based substrate, with or without a metal catalyst layer deposited therebetween. Futhermore, a pair of adjacent p-n junction forming layers is deposited on the ZnO-based layer, where one of the pair is an n-type epitaxial layer, and the other is a p-type epitaxial layer. One or more epxitaxial layers may, optionally, be deposited between the ZnO-based layer and the pair of adjacent p-n junction forming layers. | 2014-12-25 |
20140374749 | MANGANESE OXIDE THIN FILM AND OXIDE LAMINATE - The present invention provides a thin film or laminate which ensures switching capabilities by phase transition of Mott transition at room temperature. An embodiment of the present invention provides a manganese oxide thin film | 2014-12-25 |
20140374750 | THIN FILM TRANSISTOR AND DISPLAY PANEL INCLUDING THE SAME - Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor. | 2014-12-25 |
20140374751 | THIN FILM TRANSISTOR AND DISPLAY PANEL INCLUDING THE SAME - Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor. | 2014-12-25 |
20140374752 | PERPENDICULAR MAGNETIZATION STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes a storage layer which has magnetization perpendicular to its film surface and which retains information by a magnetization state of a magnetic substance, a magnetization pinned layer having magnetization perpendicular to its film surface which is used as the basis of the information stored in the storage layer, an interlayer of a non-magnetic substance provided between the storage layer and the magnetization pinned layer, and a cap layer which is provided adjacent to the storage layer at a side opposite to the interlayer and which includes at least two oxide layers. The storage element is configured to store information by reversing the magnetization of the storage layer using spin torque magnetization reversal generated by a current passing in a laminate direction of a layer structure including the storage layer, the interlayer, and the magnetization pinned layer. | 2014-12-25 |
20140374753 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING SAME - A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode. | 2014-12-25 |
20140374754 | SEMICONDUCTOR DEVICE - A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device. | 2014-12-25 |
20140374755 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - Provided is an oxide semiconductor film which has more stable electric characteristics and essentially consists of indium zinc oxide. In addition, provided is a highly reliable semiconductor device which has stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film essentially consisting of indium zinc oxide has a hexagonal crystal structure in which the a-b plane is substantially parallel to a surface of the oxide semiconductor film and a rhombohedral crystal structure in which the a-b plane is substantially parallel to the surface of the oxide semiconductor film. | 2014-12-25 |
20140374756 | SEMICONDUCTOR DEVICE, POWER DIODE, AND RECTIFIER - An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer. | 2014-12-25 |
20140374757 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANUFACTURING THE SAME - A circuit board includes a first metal pattern which includes a marking and a first solder resist, a semiconductor memory element mounted on a circuit board, a connection terminal, and a mold resin covering the semiconductor memory element. The semiconductor memory device displays information through the marking which is formed by laser processing on the first metal pattern in areas where the test terminal and the electrode terminal are not provided and the semiconductor memory element is sealed with a mold resin. | 2014-12-25 |
20140374758 | System for Wafer-Level Phosphor Deposition - System for wafer-level phosphor deposition. A method for phosphor deposition on a semiconductor wafer that has a plurality of LED dies includes the operations of covering the semiconductor wafer with a selected thickness of photo resist material, removing portions of the photo resist material to expose portions of the semiconductor wafer so that electrical contacts associated with the plurality of LED dies remain unexposed, and depositing phosphor on the exposed portions of the semiconductor wafer. | 2014-12-25 |
20140374759 | BACKPLANE OF FLAT PANEL DISPLAY AND METHOD OF MANUFACTURING THE SAME - Provided are a backplane for a flat panel display device and a method of manufacturing the backplane. The method of manufacturing the backplane for a flat panel display device includes forming an insulation substrate on a glass substrate, forming a protection layer on the insulation substrate, the protection layer including a first opening exposing a portion of the insulation substrate, forming a first hole in the insulation substrate by removing the portion of the insulation substrate exposed by the first opening, and forming a transistor on the protection layer, the transistor including an active layer, a gate electrode, a source electrode, and a drain electrode. The insulation substrate may include a transistor area including the transistor, and a non-transistor area excluding the transistor and including the first hole. | 2014-12-25 |
20140374760 | PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE - An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly. | 2014-12-25 |
20140374761 | Structure, Method for Manufacturing Structure, and illuminating structure of Thin Film Transistor - A structure, a method for manufacturing a structure, and an illuminating structure of a thin film transistor are disclosed. In the method, a substrate is provided, and a patterned first conductor layer is formed on the substrate. A patterned semiconductor layer, a patterned insulation layer, and a patterned second conductor layer are formed after forming the patterned first conductor layer, in which the patterned insulation layer contacts with the patterned second conductor layer. A first permeation barrier layer which covers the patterned second conductor layer and the patterned insulation layer is formed. | 2014-12-25 |
20140374762 | CIRCUIT INCLUDING FOUR TERMINAL TRANSISTOR - An electrical circuit includes a substrate and a plurality of transistors. The plurality of transistors includes a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. A second electrically insulating material layer conforms to the reentrant profile of the gate and in positioned on at least a portion of the first electrically insulating material layer. A semiconductor material ayer conforms to and is in contact with the second electrically insulating material layer. | 2014-12-25 |
20140374763 | TFT-DRIVEN DISPLAY DEVICE - A TFT-driven display device includes an upper substrate and a lower substrate facing each other, multiple TFTs disposed on a side of the lower substrate facing the upper substrate, and a metal layer disposed on a side of the upper substrate facing to the lower substrate. The metal layer includes a portion that does not overlap with the active layer of the TFTs in a light transmission direction, or the metal layer includes portions overlapping with the active layer of the TFTs in the light transmission direction, the overlapping portions have a pattern width less than a pattern width of other portions that do not overlap with the active layer. In the TFT-driven display device, a photo leakage current caused by the light reflected by the metal may be reduced, because no portion of the metal layer is provided in the position opposed to the active layer of the TFTs located on a TFT array substrate. | 2014-12-25 |
20140374764 | THIN FILM TRANSISTOR ARRAY PANEL AND A METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film. transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors. | 2014-12-25 |
20140374765 | Gate Stack for Normally-Off Compound Semiconductor Transistor - A normally-off compound semiconductor transistor includes a heterostructure body and a gate stack on the heterostructure body. The heterostructure body includes a source, a drain spaced apart from the source, and a channel for connecting the source and the drain. The channel includes a first two-dimensional charge carrier gas of a first polarity arising in the heterostructure body due to piezoelectric effects. The gate stack controls the channel in a region of the heterostructure body under the gate stack. The gate stack includes at least one III-nitride material which gives rise to a second two-dimensional charge carrier gas of a second polarity opposite the first polarity in the gate stack or in the heterostructure body under the gate stack due to piezoelectric effects. The second two-dimensional charge carrier gas counter-balances polarization charges in the first two-dimensional charge carrier gas so that the channel is disrupted under the gate stack. | 2014-12-25 |
20140374766 | BI-DIRECTIONAL GALLIUM NITRIDE SWITCH WITH SELF-MANAGED SUBSTRATE BIAS - A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp. | 2014-12-25 |
20140374767 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode (LED) structure includes a substrate, an LED element, a reverse current protection element, a third conductor, and a fourth conductor. The LED element includes a first N-type semiconductor layer, a first lighting layer, a first P-type semiconductor layer, a first transparent conductive layer, a first electrode, and a second electrode. The reverse current protection element is located on the substrate and surrounds the LED element. The reverse current protection element includes a stack layer, a first conductor, and a second conductor. The stack layer is formed on the substrate by sequentially stacking a second N-type semiconductor layer, a second lighting layer, and a second P-type semiconductor layer. The third conductor is electrically connected to the first conductor and the second electrode. The fourth conductor is electrically connected to the second conductor and the first electrode. | 2014-12-25 |
20140374768 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 2014-12-25 |
20140374769 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas. | 2014-12-25 |
20140374770 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. A stem is connected to the element securing member, and a cap is secured to the stem. The cap covers the semiconductor element and the element securing member. The stem and the element securing member are made of the same material. | 2014-12-25 |
20140374771 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm. | 2014-12-25 |
20140374772 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. | 2014-12-25 |
20140374773 | VERTICAL POWER TRANSISTOR WITH BUILT-IN GATE BUFFER - A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise. | 2014-12-25 |
20140374774 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer | 2014-12-25 |
20140374775 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD FOR ELECTRONIC COMPONENT - A first metal film, of which major component is copper, is formed on a surface of a conductive portion which becomes a front surface electrode of a semiconductor element. A second metal film of which major component is silver is formed on a surface of the first metal film. A metal plate, which electrically connects the conductive portion and the other members (e.g. a circuit pattern of an insulated substrate) is bonded with a surface of the second metal film via a bonding layer containing silver particles. The second metal film does not contain nickel which decreases the bonding strength between the second metal film and the bonding layer containing silver particles. With the above configuration, an electronic component having a high bonding strength, excellent heat resistance and radiation performance, and a manufacturing method for the electronic component can be provided. | 2014-12-25 |
20140374776 | OPTICAL-COUPLING SEMICONDUCTOR DEVICE - The optical-coupling semiconductor device includes: a primary support plate and a secondary support plate facing each other and spaced apart a predetermined distance; a light emitting device situated on the primary support plate; and a light receiving device including a light receiving surface to receive light from a light emitting surface of the light emitting device. The light emitting device is situated on a surface facing the secondary support plate of the primary support plate so that the light emitting surface is oriented toward the secondary support plate. The light receiving device is situated on a surface facing the primary support plate of the secondary support plate so that the light receiving surface faces the light emitting surface of the light emitting device. The light emitting device is on the light receiving surface of the light receiving device. | 2014-12-25 |
20140374777 | LIGHT EMITTING DEVICE AND OPTICAL DEVICE - A light emitting device is capable of enhancing the radiant intensity on a single direction. The light emitting device includes a substrate and an LED chip bonded to the substrate, wherein the substrate has a first cavity formed thereon having a first bottom surface for disposing the LED chip and a first lateral connecting to the first bottom surface, and the substrate has a second cavity formed thereon having a second bottom surface for bonding the metal wire and a second lateral connecting to the second bottom surface; and the first lateral has a notch formed thereon, which connects to the second bottom surface and the second lateral, and an area of the second bottom surface of the second cavity is smaller than that of the first bottom surface of the first cavity. | 2014-12-25 |
20140374778 | Optical Assembly - An optical assembly configured to emit electromagnetic radiation comprises first and second electroluminescent semiconductor components positioned adjacent to each other. The first electroluminescent semiconductor component is transparent to electromagnetic radiation generated by the second electroluminescent semiconductor component, and the second electroluminescent semiconductor component is transparent to electromagnetic radiation generated by the first electroluminescent semiconductor component. The first electroluminescent semiconductor component and the second electroluminescent semiconductor component are configured to actuate independently of each other. | 2014-12-25 |
20140374779 | LIGHT-EMITTING DEVICE AND LIGHT-EMITTING ARRAY - A light-emitting device includes a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes a first surface, a second surface opposite to the first surface, a first portion connecting to the first surface, and a second portion connecting to the first portion; an opening penetrating the first portion from the first surface and having a first width; a depression connecting to the opening and penetrating the second semiconductor layer, the active layer, and the second portion of the first semiconductor layer, wherein the depression includes a second width greater than the first width, and the depression includes a bottom to expose the second surface, and an electrode located in the depression and corresponding to the opening. | 2014-12-25 |
20140374780 | LIGHT EMITTING DEVICE FOR ILLUMINATING PLANTS - A spectrally adapted light emitting device for illuminating plants includes at least one semiconductor light-emitting diode (LED), at least one light conversion element for down-converting a portion of light emitted at the first wavelength to at least a second wavelength between 600 nm-680 nm, and at least one scattering device to diffuse light within the light emitting device. The at least one LED is configured to emit at least a first wavelength between 400 nm and 480 nm. The spectral light output from the spectrally adapted light emitting device is bi-modal with wavelengths in a range of 400 nm and 800 nm including a first local maximum between 400 nm and 480 nm and a second local maximum between 600 nm-680 nm with a local minimum between the first local maximum and the second local maximum. | 2014-12-25 |
20140374781 | LIGHT EMITTING DEVICE MANUFACTURING METHOD AND LIGHT EMITTING DEVICE - To improve efficiency when manufacturing a light emitting device formed using a mask to form regions corresponding to pixels on a substrate, provided is a method including, after forming a pattern on a substrate with a first light emitting material that emits light of a first spectrum, through a first opening and one or more second openings of a mask, moving the mask in a longitudinal direction of the first opening by a distance that is less than the width of the first opening in the longitudinal direction of the first opening and greater than or equal to the width of the one or more second openings in the longitudinal direction of the first opening, and then forming a pattern with a second light emitting material that emits light of a second spectrum, through the first opening and the one or more second openings of the mask. | 2014-12-25 |
20140374782 | LIGHTING SYSTEM - It is an object of the present invention to provide a lighting system having favorable luminance uniformity in a light-emitting region when the lighting system has large area. According to one feature of the invention, a lighting system comprises a first electrode, a second electrode, a layer containing a light-emitting substance formed between the first electrode and the second electrode, an insulating layer which is formed over a substrate in a grid form and contains a fluorescence substance, and a wiring formed over the insulating layer. The insulating layer and the wiring are covered with the first electrode so that the first electrode and the wiring are in contact with each other. | 2014-12-25 |
20140374783 | Optical Device Integrated with Driving Circuit and Power Supply Circuit, Method for Manufacturing Optical Device Substrate Used Therein, and Substrate Thereof - The present invention relates to an optical device integrated with a driving circuit and a power supply circuit, a method for manufacturing an optical device substrate used therein, and a substrate thereof, which are capable of reducing the overall size and facilitating the handling and management thereof by mounting a plurality of optical elements, driving circuits thereof, and power supply circuits thereof on a single substrate for an optical device having a vertical insulating layer. The objective of the present invention is to provide the optical device integrated with the driving circuit and the power supply circuit, the method for manufacturing the optical device substrate used therein, and the substrate thereof which are capable of reducing the overall size and facilitating the handling and the management thereof by mounting the plurality of optical elements, the driving circuits thereof, and the power supply circuits thereof on the single substrate for the optical device having the vertical insulating layer. | 2014-12-25 |
20140374784 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device includes a light emitting structure below a substrate, in which at least one first contact area and at least one second contact area are defined. A plurality of layers having mutually different refractive indexes is provided below the light emitting structure. | 2014-12-25 |
20140374785 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS INCLUDING THE SAME - Disclosed herein is a light emitting device exhibiting improved current spreading. The disclosed light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type and second conductivity type semiconductor layers, a first electrode disposed on the first conductivity type semiconductor layer, and a second electrode disposed on the second conductivity type semiconductor layer. The light emitting structure includes a mesa etching region where the second conductivity type semiconductor layer, active layer, and first conductivity type semiconductor layer are partially etched, thereby exposing a portion of the first conductivity type semiconductor layer. The first electrode is disposed on the exposed portion of the first conductivity type semiconductor layer. A first electrode layer is disposed between the second conductivity type semiconductor layer and the second electrode. A second electrode layer is disposed between portions of the first electrode layer spaced from each other at opposite sides of the mesa etching region. | 2014-12-25 |
20140374786 | MOULDED LENS FORMING A CHIP SCALE LED PACKAGE AND METHOD OF MANUFACTURING THE SAME - A wafer-scale process is described that simultaneously encapsulates LED dies, forms lenses over the LED dies, and forms a chip scale package for said dies. An array of LED dies ( | 2014-12-25 |
20140374787 | ENCAPSULATING SHEET, PRODUCING METHOD OF OPTICAL SEMICONDUCTOR DEVICE, OPTICAL SEMICONDUCTOR DEVICE, AND LIGHTING DEVICE - An encapsulating sheet, encapsulating an optical semiconductor element, includes a first layer which contains a phosphor and a second layer which contains a phosphor, is laminated on the first layer, and encapsulates the optical semiconductor element. The ratio of the volume of the phosphor in the first layer to that of the phosphor in the second layer is 90:10 to 55:45. | 2014-12-25 |
20140374788 | LIGHT EMITTING DEVICE - Provided is a light emitting device. The light emitting device includes: a plurality of lead frame units spaced apart from each other, each of the lead frame units being provided with at least one fixing space perforating a body thereof in a vertical direction; a light emitting diode chip mounted on one of the lead frame units; and a molding unit that is integrally formed on top surfaces of the lead frame units and in the fixing spaces to protect the light emitting diode chip. | 2014-12-25 |
20140374789 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal. | 2014-12-25 |
20140374790 | Structure of a Trench MOS Rectifier and Method of Forming the Same - A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n− drift epitaxial layer, a plurality of MOS structure formed on the substrate either in discrete islands or in rows. Asides the MOS gates there are source regions formed under the mesas. A top metal served as an anode is then formed on the resulted front surface connecting the MOS gates and the adjacent source regions. | 2014-12-25 |
20140374791 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region. | 2014-12-25 |
20140374792 | METHOD FOR MANUFACTURING A VERTICAL BIPOLAR TRANSISTOR COMPATIBLE WITH CMOS MANUFACTURING METHODS - The present disclosure relates to a method for manufacturing a bipolar transistor, the method comprising steps of: forming a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer, forming a first P-doped well, in the second region, producing a collector region of second and third wells by means of P doping in the first region, the second well being in contact with the first well below the trench, producing an N-doped base well on the collector region, on the wafer surface, forming a CMOS transistor gate on the first region delimiting a first region and a second region, forming a P+-doped collector contact region and a P+-doped emitter region, respectively in the first well and in the first region, and forming an N+-doped base contact region in the second region. | 2014-12-25 |
20140374793 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE | 2014-12-25 |
20140374794 | POWER SEMICONDUCTOR WITH A SI CHIP AND A WIDEBAND CHIP HAVING MATCHED LOSS AND AREA RATIOS - A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted. | 2014-12-25 |
20140374795 | SEMICONDUCTOR SYSTEM FOR A CURRENT SENSOR IN A POWER SEMICONDUCTOR - A semiconductor system for a current sensor in a power semiconductor includes: on a substrate, a multiple arrangement of transistor cells having an insulated gate electrode, whose emitter terminals are connected in a first region via a first conductive layer to at least one output terminal and whose emitter terminals are connected in a second region via a second conductive layer to at least one sensor terminal, which is situated outside of a first cell region boundary, which encloses the transistor cells of the first region and the second region, a trench structure belonging to the first cell region boundary being developed between the transistor cells of the second region and the sensor terminal. | 2014-12-25 |
20140374796 | SEMICONDUCTOR STRUCTURE WITH ASPECT RATIO TRAPPING CAPABILITIES - A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance. | 2014-12-25 |
20140374797 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material. | 2014-12-25 |
20140374798 | Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication - Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures. | 2014-12-25 |
20140374799 | FIN TUNNEL FIELD EFFECT TRANSISTOR (FET) - A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided. | 2014-12-25 |
20140374800 | OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. | 2014-12-25 |
20140374801 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate. | 2014-12-25 |
20140374802 | BIPOLAR TRANSISTOR WITH MASKLESS SELF-ALIGNED EMITTER - Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes. | 2014-12-25 |
20140374803 | DRIVING METHOD OF A SEMICONDUCTOR DEVICE - A horizontal scanning period is divided into n parts (n is a natural number), so that horizontal scanning can be performed (n×y) times in one frame period. That is, n signals can be outputted from each pixel, and storage times of the n signals are different from one another. Then, since a signal suited to the intensity of light irradiated to each pixel can be selected, information of an object can be accurately read. | 2014-12-25 |
20140374804 | Micromechanical Sensor Apparatus having a Movable Gate and Corresponding Production Method - A micromechanical sensor apparatus having a movable gate includes a field effect transistor that has a movable gate, which is separated from a channel region by a cavity. The channel region is covered by a gate insulation layer. | 2014-12-25 |
20140374805 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess. | 2014-12-25 |
20140374806 | FOUR TERMINAL TRANSISTOR - A transistor includes a substrate, a first electrically conductive material layer positioned on the substrate, and a first electrically insulating material layer is positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. A second electrically insulating material layer conforms to the reentrant profile of the gate and in positioned on at least a portion of the first electrically insulating material layer. A semiconductor material layer conforms to and is in contact with the second electrically insulating material layer. | 2014-12-25 |
20140374807 | METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING - Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation. | 2014-12-25 |
20140374808 | SEMICONDUCTOR COMPONENT WITH TRENCH GATE - The present invention relates to a semiconductor component ( | 2014-12-25 |
20140374809 | PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS - An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed. | 2014-12-25 |
20140374810 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers. | 2014-12-25 |
20140374811 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES - Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region. | 2014-12-25 |
20140374812 | DEVICE INCLUDING ACTIVE FLOATING GATE REGION AREA THAT IS SMALLER THAN CHANNEL AREA - A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area. | 2014-12-25 |
20140374813 | SONOS Stack With Split Nitride Memory Layer - A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described. | 2014-12-25 |
20140374814 | Embedded Memory and Methods of Forming the Same - An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer. | 2014-12-25 |
20140374815 | Memory Devices with Floating Gate Embedded in Substrate - An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack. | 2014-12-25 |
20140374816 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film ( | 2014-12-25 |
20140374817 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes: a semiconductor pillar stretched perpendicularly to a substrate; a plurality of memory cells stacked along the semiconductor pillar; a bit line coupled with a first end of the semiconductor pillar; a first source line coupled with one of the first end and a second end of the semiconductor pillar; a second source line disposed over the bit line and the first source line; a first switch having a first end coupled with the first source line and a second end coupled with a first voltage supplier, and controlling whether to supply a first voltage to the first source line; and a second switch having a first end coupled with the first source line and a second end coupled with the second source line, and controlling whether or not to supply a second voltage supplied from the second source line to the first source line. | 2014-12-25 |
20140374818 | Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same - A structure of trench VDMOS transistor comprises an n− epi-layer/n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments. | 2014-12-25 |
20140374819 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD | 2014-12-25 |
20140374820 | DUAL TRENCH MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - A dual trench MOS transistor comprises of the following elements. A plurality of trenches are formed in an n− epitaxial layer on a heavy doped n+ semiconductor substrate and spaced to each other by one mesa. Each the trench has a trench oxide layer formed on a bottom and sidewalls thereof. A first polysilicon layer is formed in the trenches. A plurality of recesses are formed in the mesas and spaced to each other with one sub-mesa. Each the recess has a recess oxide layer formed on a bottom and sidewalls thereof. A second polysilicon layer for serving as a gate is formed in the recesses. The mesas are implanted to have implanted areas at two side of the gate. The implanted areas and the first polysilicon layer are applied to serve as the source. The rear surface of the substrate is served as the drain. | 2014-12-25 |
20140374821 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region ( | 2014-12-25 |
20140374822 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction. | 2014-12-25 |
20140374823 | ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 2014-12-25 |
20140374824 | MOSFET WITH INTEGRATED SCHOTTKY DIODE - Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-12-25 |
20140374825 | Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches - Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another. | 2014-12-25 |
20140374826 | Vertical Gate LDMOS Device - Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region. | 2014-12-25 |
20140374827 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain. | 2014-12-25 |
20140374828 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base. | 2014-12-25 |
20140374829 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin. | 2014-12-25 |
20140374830 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern. | 2014-12-25 |
20140374831 | Embedded SRAM and Methods of Forming the Same - A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes. | 2014-12-25 |
20140374832 | BEOL SELECTIVITY STRESS FILM - The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance. | 2014-12-25 |
20140374833 | Memory Arrays - The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions. | 2014-12-25 |
20140374834 | GERMANIUM STRUCTURE, GERMANIUM FIN FIELD EFFECT TRANSISTOR STRUCTURE AND GERMANIUM COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR STRUCTURE - A germanium (Ge) structure includes a substrate, a Ge layer and at least a Ge spatial structure. The Ge layer is formed on the substrate, and a surface of the Ge layer is a Ge {110} lattice plane. The Ge spatial structure is formed in the Ge layer and includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. Because Ge {111} surface channels have very high electron mobility, this Ge spatial structure may be applied for fabricating high-performance Ge semiconductor devices. | 2014-12-25 |
20140374835 | METAL GATE SEMICONDUCTOR DEVICE - A semiconductor device including a first gate structure associated with a first type of transistor and a second gate structure of a second type of transistor. The first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer and a fill layer on the second metal layer. The second type of work function is different than the first type of work function. The second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer. | 2014-12-25 |
20140374836 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY - An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. | 2014-12-25 |
20140374837 | SEMICONDUCTOR DEVICE - A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin. | 2014-12-25 |
20140374838 | FinFETs with Nitride Liners and Methods of Forming the Same - An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region. | 2014-12-25 |
20140374839 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER - A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins. | 2014-12-25 |
20140374840 | SEMICONDUCTOR DEVICES USING MOS TRANSISTORS WITH NONUNIFORM GATE ELECTRODE STRUCTURES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width. | 2014-12-25 |
20140374841 | FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE - A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively. | 2014-12-25 |
20140374842 | Semiconductor Device with Self-Charging Field Electrodes - A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, and a field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and having an opening, and at least one of a field stop region and a generation region. The semiconductor device further includes a coupling region of a second doping type complementary to the first doping type. The coupling region is electrically coupled to the device region and coupled to the field electrode. | 2014-12-25 |
20140374843 | REPLACEMENT METAL GATE TRANSISTOR - A replacement metal gate transistor is described. Various examples provide a replacement metal gate transistor including a trench, a first sidewall and a second sidewall. A layer is disposed in the trench where the layer has a bottom section disposed on a bottom of the trench and sidewall sections disposed on the first and second sidewalls, wherein the sidewall sections of the layer are at least 50% thinner than the bottom section of the layer. | 2014-12-25 |
20140374844 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 2014-12-25 |
20140374845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a semiconductor substrate and extending in a first direction and a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, where the width of the metal gate electrode and the width of the metal gate pad are larger than the width of the metal gate line. | 2014-12-25 |