52nd week of 2008 patent applcation highlights part 47 |
Patent application number | Title | Published |
20080318391 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device that may include steps of forming a pad oxide layer and an insulating layer on a semiconductor substrate; and then performing a first etching process on the semiconductor device to form an insulating layer pattern exposing a portion of the pad oxide layer in a trench area; and then performing a second etching process with respect to the pad oxide layer by using the insulating layer pattern as a mask; and then performing a blanket ion implantation process with respect to the insulating layer pattern and the exposed portion of the pad oxide layer to form an ion layer in the semiconductor substrate; and then performing a third etching process with respect to the semiconductor substrate to simultaneously form a pad oxide layer pattern and a trench in the semiconductor substrate; and then forming an insulating layer on the semiconductor substrate including the trench; and then performing a planarization process with respect to the semiconductor substrate including the insulating material and removing the pad oxide layer pattern and the insulating layer pattern, thereby forming an isolation layer in the trench. | 2008-12-25 |
20080318392 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the uncovered inner wall of the trench; removing the first dielectric layer; and forming a second dielectric layer to cover the trench and form a void inside the trench. | 2008-12-25 |
20080318393 | Method for Manufacturing Semiconductor Device - There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole. | 2008-12-25 |
20080318394 | Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device - A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an insulating layer on the single crystal semiconductor substrate to which the plasma treatment is performed; bonding the single crystal semiconductor substrate to the substrate having the insulating surface with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate using the ion doped layer as a separation surface. As a result, a semiconductor substrate in which a defect in an interface between the single crystal semiconductor layer and the insulating layer is reduced can be provided. | 2008-12-25 |
20080318395 | METHODS AND SYSTEMS FOR IMAGING AND CUTTING SEMICONDUCTOR WAFERS AND OTHER SEMICONDUCTOR WORKPIECES - Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes. | 2008-12-25 |
20080318396 | Grooving Bumped Wafer Pre-Underfill System - A method of forming a semiconductor device includes providing a bumped wafer. A plurality of grooves is formed in an active surface of the bumped wafer. A pre-underfill layer is disposed over the active surface, filling the plurality of grooves. A first adhesive layer is mounted to the pre-underfill layer, and a back surface of the bumped wafer is ground. A second adhesive layer is mounted to the back surface of the bumped wafer. The first adhesive layer is peeled from the active surface of the bumped wafer, or the second adhesive layer is mounted to the first adhesive layer. The bumped wafer is singulated into a plurality of segments by cutting the bumped wafer along the plurality of grooves. | 2008-12-25 |
20080318397 | Junction Diode with Reduced Reverse Current - A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process. | 2008-12-25 |
20080318398 | Method for manufacturing crystalline semiconductor film and semiconductor device - There is provided a method for manufacturing a crystalline semiconductor film. An insulating film is formed over a substrate; an amorphous semiconductor film is formed over the insulating film; a cap film is formed over the amorphous semiconductor film; the amorphous semiconductor film is scanned and irradiated with a continuous wave laser beam or a laser beam with a repetition rate of greater than or equal to 10 MHz, through the cap film; and the amorphous semiconductor film is melted and crystallized. At that time, an energy period in a length direction in a laser beam spot of the laser beam is 0.5 μm to 10 μm, preferably, 1 μm to 5 μm; an energy distribution in a width direction in a laser beam spot of the laser beam is a Gaussian distribution; and the amorphous semiconductor film is scanned with the laser beam so as to be irradiated with the laser beam for a period of greater than or equal to 5 microseconds and less than or equal to 100 microseconds per region. | 2008-12-25 |
20080318399 | PLASMA DOPING METHOD - A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. | 2008-12-25 |
20080318400 | Method for manufacturing SIC semiconductor device - A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small. | 2008-12-25 |
20080318401 | Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device - A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type . By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region. | 2008-12-25 |
20080318402 | SEMICONDUCTOR DEVICE HAVING A RECESS CHANNEL AND METHOD FOR FABRICATING THE SAME - Provided is a semiconductor device having recess channel, comprising a semiconductor substrate having first and second trenches disposed to cross each other on both sides of an active region among adjoining regions between an active region and element-isolation films; a gate insulation film disposed on the semiconductor substrate of the active region; a first gate line disposed on the gate insulation film, and crossing the active region and overlapping with the first trench; and a second gate line disposed on the gate insulation film, and crossing the active region while overlapping with the second trench. | 2008-12-25 |
20080318403 | METHOD FOR FABRICATING SEMICONDUCTOR TRANSISTOR - A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching. | 2008-12-25 |
20080318404 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode. | 2008-12-25 |
20080318405 | METHOD OF FABRICATING GATE STRUCTURE - A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure. | 2008-12-25 |
20080318406 | SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level. | 2008-12-25 |
20080318407 | Method for Forming Storage Electrode of Semiconductor Memory Device - In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed. | 2008-12-25 |
20080318408 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a Si-containing compound; and subjecting the primary reactant to dehydration condensation to form a silicon oxide film on the surface of the processed portion. | 2008-12-25 |
20080318409 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD FOR ETCHING THE SAME - A method for manufacturing a dual damascene structure includes forming a wiring layer over a substrate, forming an inorganic insulating film over the wiring layer, forming a via hole in the inorganic insulating film using a first resist pattern with an opening as an etching mask, removing the first resist pattern, forming an organic insulating film on the inorganic insulating film and in the via hole, forming a hard mask on the organic insulating film, forming a hard mask pattern using a second resist pattern with an opening on the hard mask as an etching mask, forming a wiring groove by etching the organic insulating film using the second resist pattern and the hard mask pattern as etching masks until the organic insulating film inside the via hole is eliminated and simultaneously eliminating the second resist pattern, and implanting a conductive substance into the via hole and wiring groove. | 2008-12-25 |
20080318410 | METHOD OF FORMING METAL ELECTRODE OF SYSTEM IN PACKAGE - A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer having high viscosity at a lower portion of the through hole in order to seal the lower portion thereof, and forming a through electrode by filling copper in the through hole. There is an effect of efficiently forming a through electrode having a large depth corresponding to the height of stacked semiconductor devices in the system in package. Filling copper in a through hole having a large depth-to-width ratio may be efficiently done by OSP coating, electrolysis copper plating, and electro Cu plating processes. | 2008-12-25 |
20080318411 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask | 2008-12-25 |
20080318412 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming an interlayer insulating film over a wiring layer, forming an opening in the interlayer insulating film, performing a first plasma treatment using a gas including hydrogen or ammonia, performing a second plasma treatment with a gas including fluorocarbon after the first plasma treatment. | 2008-12-25 |
20080318413 | METHOD FOR MAKING AN INTERCONNECT STRUCTURE AND INTERCONNECT COMPONENT RECOVERY PROCESS - A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer. | 2008-12-25 |
20080318414 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of the seed layer be removed through an annealing process using H | 2008-12-25 |
20080318415 | INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF - A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure. | 2008-12-25 |
20080318416 | METHOD OF IMPROVING INTERCONNECTION BETWEEN ALUMINUM AND COPPER IN SEMICONDUCTOR METAL LINE PROCESS - A method for enhancing an aluminum-copper interconnection in a semiconductor metal line process. In order to solve a reduction in wafer yield due to copper segregation resulting from a time delay during a metal deposition process, copper precipitates are re-solidified into the aluminum film through a quench process of performing annealing on the wafer at a predetermined temperature for a predetermined time correlating to the time delay. | 2008-12-25 |
20080318417 | METHOD OF FORMING RUTHENIUM FILM FOR METAL WIRING STRUCTURE - A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate. | 2008-12-25 |
20080318418 | Process for Forming Continuous Copper Thin Films Via Vapor Deposition - A process for preparing a multi-layer substrate is described herein. In one embodiment, the process provides a multi-layer substrate comprising a first layer and a second layer where the process comprises the steps of providing the first layer comprising a barrier area and a copper area; and depositing the second layer comprising copper onto the first layer wherein the depositing provides the second layer comprising a first thickness ranging from about 20 Angstroms to about 2,000 Angstroms onto the barrier area and a second thickness ranging from about 0 Angstroms to about 1,000 Angstroms onto the copper area in the first layer wherein the first thickness is greater than the second thickness. | 2008-12-25 |
20080318419 | CHARGE DISSIPATION OF CAVITIES - Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates. | 2008-12-25 |
20080318420 | TWO STEP CHEMICAL MECHANICAL POLISH - In one embodiment, a method includes providing two structures with a spacing therebetween over a semiconductor substrate, providing a conformal first layer over the two structures and within the space therebetween, depositing a conformal protective layer over the first layer, planarizing the protective layer until a top surface of the first layer is exposed, and planarizing the first layer and the protective layer until a top surface of the two structures is exposed and a portion of the protective layer is between the two structures. | 2008-12-25 |
20080318421 | METHODS OF FORMING FILMS OF A SEMICONDUCTOR DEVICE - There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual. | 2008-12-25 |
20080318422 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas). | 2008-12-25 |
20080318423 | PROCESS FOR PRODUCING METAL OXIDE FILMS AT LOW TEMPERATURES - A process for producing metal oxide thin films on a substrate by the ALD method comprises the steps of bonding no more than about a molecular monolayer of a gaseous metal compound to a growth substrate, and converting the bonded metal compound to metal oxide. The bonded metal compound is converted to metal oxide by contacting it with a reactive vapour source of oxygen other than water, and the substrate is kept at a temperature of less than 190° C. during the growth process. By means of the invention it is possible to produce films of good quality at low temperatures. The dielectric thin films having a dense structure can be used for passivating surfaces that do not endure high temperatures. Such surfaces include, for example, organic films in integrated circuits and polymer films such as in organic electroluminescent displays and organic solar cells. Further, when a water-free oxygen source is used, surfaces that are sensitive to water can be passivated. | 2008-12-25 |
20080318424 | Photoresist residue remover composition and semiconductor circuit element production process employing the same - A photoresist residue remover composition is provided that removes a photoresist residue formed by a resist ashing treatment after dry etching in a step of forming, on a substrate surface, wiring of any metal of aluminum, copper, tungsten, and an alloy having any of these metals as a main component, the composition including one or two or more types of inorganic acid and one or two or more types of inorganic fluorine compound. There is also provided a process for producing a semiconductor circuit element wherein, in a step of forming wiring of any metal of aluminum, copper, tungsten, and an alloy having any of these metals as a main component, the photoresist residue remover composition is used for removing a photoresist residue formed by a resist ashing treatment after dry etching. | 2008-12-25 |
20080318425 | SEMICONDUCTOR DEVICE PRODUCTION METHOD - The purpose of the present invention is to stabilize the polishing film thickness during the overpolishing following the removal of barrier metal in Cu-CMP (chemical mechanical polishing). To this end, a table in which the relationship between wire perimeter and overpolishing process polishing rate is created. The polishing time is calculated based on the wire perimeter in determining the overpolishing time after the removal of barrier metal in Cu-CMP to stabilize the overpolishing film thickness. | 2008-12-25 |
20080318426 | WAFER RECYCLING METHOD - A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer. | 2008-12-25 |
20080318427 | CHEMICAL MECHANICAL POLISHING AQUEOUS DISPERSION PREPARATION SET, METHOD OF PREPARING CHEMICAL MECHANICAL POLISHING AQUEOUS DISPERSION, CHEMICAL MECHANICAL POLISHING AQUEOUS DISPERSION, AND CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing aqueous dispersion preparation set including: a first composition which includes colloidal silica having an average primary particle diameter of 15 to 40 nm and a basic compound and has a pH of 8.0 to 11.0; and a second composition which includes poly(meth)acrylic acid and an organic acid having two or more carbonyl groups other than the poly(meth)acrylic acid and has a pH of 1.0 to 5.0. | 2008-12-25 |
20080318428 | Method for Achieving Uniform Chemical Mechanical Polishing In Integrated Circuit Manufacturing - A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile memory integrated circuit. A second film, which is a sacrificial film formed using a second material, such as silicon oxide, is then provided over the first film. Partial removal of the second film is carried out using chemical mechanical polishing until a portion of the first film is exposed using a first slurry that is selective to the first material. Thereafter, the remaining layer of the second film is removed, along with planarization of the surface, using a second slurry that is highly selective, i.e., has a selectivity of the first film to the second film that is greater than a predetermine value (e.g., 16:1). | 2008-12-25 |
20080318429 | Fabrication method of semiconductor integrated circuit device - An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A cleaning gas converted into plasma in a plasma gas generator is introduced into a chamber to remove an unnecessary film deposited over the interior wall of the chamber or electrode. By an RF power source adjusted to low output from the film formation time, a high frequency voltage is applied to a lower electrode and an upper electrode. This voltage is detected by an RF sensor and amplified by an electronic module. The voltage thus amplified by the electronic module is input to a termination controller. The termination controller automatically judges the termination of cleaning when the voltage thus input becomes substantially constant at a predetermined voltage or greater. | 2008-12-25 |
20080318430 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING POROUS LOW DIELECTRIC CONSTANT LAYER FORMED FOR INSULATION BETWEEN METAL LINES - The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers. | 2008-12-25 |
20080318431 | Shower Plate and Plasma Treatment Apparatus Using Shower Plate - A shower plate for plasma processing, which is formed by a plurality of pipes. A pipe includes a porous material member disposed along the pipe, which has a predetermined porosity with respect to a material gas, and which has an outwardly convex shape, and a metal member faced to the porous material member and that forms a material gas flow path in combination with the porous material member. A nozzle structure capable of releasing the material gas with a spread can be realized. | 2008-12-25 |
20080318432 | REACTOR WITH HEATED AND TEXTURED ELECTRODES AND SURFACES - A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing. | 2008-12-25 |
20080318433 | Plasma confinement rings assemblies having reduced polymer deposition characteristics - Plasma confinement ring assemblies are provided that include confinement rings adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to avoid polymer deposition on those surfaces. The plasma confinement rings include thermal chokes adapted to localize heating at selected portions of the rings that include the plasma exposed surfaces. The thermal chokes reduce heat conduction from those portions to other portions of the rings, which causes selected portions of the rings to reach desired temperatures during plasma processing. | 2008-12-25 |
20080318434 | SYSTEMS AND METHODS FOR OSCILLATING EXPOSURE OF A SEMICONDUCTOR WORKPIECE TO MULTIPLE CHEMISTRIES - Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried. | 2008-12-25 |
20080318435 | Composition for etching a metal hard mask material in semiconductor processing - An etching solution for a metal hard mask. The etching solution comprises a mixture of a dilute HF (hydrofluoric acid) and a silicon containing precursor. The etching solution also comprises a surfactant agent, a carboxylic acid, and a copper corrosion inhibitor. The etching solution is selectively toward etching the metal hard mask material (e.g., Titanium) while suppressing Tungsten, Copper, oxide dielectric material, and carbon doped oxide. | 2008-12-25 |
20080318436 | Antireflective Coating Material - Antireflective coatings comprising (i) a silsesquioxane resin having the formula (PhSiO (3-x)/2 (OH) x) mHSiO (3-x)/2 (OH) x) n (MeSiO (3-x)/2 (OH) x) p where Ph is a phenyl group, Me is a methyl group, x has a value of 0, 1 or 2; m has a value of 0.01 to 0.99, n has a value of 0.01 to 0.99, p has a value of 0.01 to 0.99, and m+n+p=1; (ii) a polyethylene oxide fluid; and (iii) a solvent; and a method of forming said antireflective coatings on an electronique device. | 2008-12-25 |
20080318437 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE UTILIZING LOW DIELECTRIC LAYER FILLING GAPS BETWEEN METAL LINES - A semiconductor device is manufactured by forming a low dielectric constant layer on a semiconductor substrate which is formed with metal lines; implementing primary ultraviolet treatment of the low dielectric constant layer; forming a capping layer on the low dielectric constant layer having undergone the primary ultraviolet treatment; and implementing secondary ultraviolet treatment of the low dielectric constant layer including the capping layer. | 2008-12-25 |
20080318438 | Method for manufacturing sic semiconductor device - A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed to a carbon layer; annealing the SiC layer to activate the impurity with covering the SiC layer with the carbon layer; removing the carbon layer; and performing a sacrifice oxidation process. The performing the sacrifice oxidation process includes: forming a sacrifice oxide film; and removing the sacrifice oxide film. The forming the oxide film is performed after the performing the sacrifice oxidation process. | 2008-12-25 |
20080318439 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method. | 2008-12-25 |
20080318440 | POROUS ORGANOSILICATE LAYERS, AND VAPOR DEPOSITION SYSTEMS AND METHODS FOR PREPARING SAME - The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks. | 2008-12-25 |
20080318441 | PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES - A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure. | 2008-12-25 |
20080318442 | Semiconductor device manufacturing method and substrate processing apparatus - The present invention has an object of providing a substrate processing apparatus and a semiconductor device manufacturing method that can prevent adverse effects on electrical characteristics and provide a thinner EOT. | 2008-12-25 |
20080318443 | Plasma enhanced cyclic deposition method of metal silicon nitride film - The present invention relates to a method for forming a metal silicon nitride film according to a cyclic film deposition under plasma atmosphere with a metal amide, a silicon precursor, and a nitrogen source gas as precursors. The deposition method for forming a metal silicon nitride film on a substrate comprises steps of: pulsing a metal amide precursor; purging away the unreacted metal amide; introducing nitrogen source gas into reaction chamber under plasma atmosphere; purging away the unreacted nitrogen source gas; pulsing a silicon precursor; purging away the unreacted silicon precursor; introducing nitrogen source gas into reaction chamber under plasma atmosphere; and purging away the unreacted nitrogen source gas. | 2008-12-25 |
20080318444 | Electrical connector provided with alignment slot - An electrical connector includes a mating portion including a first cavity ( | 2008-12-25 |
20080318445 | Electrical connector with improved housing - An electrical connector for interconnecting integrated circuits (ICs) to a circuit board, includes a number of contacts ( | 2008-12-25 |
20080318446 | Electronic Component Cover and Arrangement - An electronic component cover comprises a plate having a first region adapted to substantially cover at least one side of a first electronic component. The plate is adapted to accommodate a second electronic component thereon, such as a SIM card or a SIM card reader. The plate may include a second region to accommodate the second electronic component therein. The electronic component cover may comprise one or more leads adapted to provide electrical communication between the first electronic component and the second electronic component. The one or more leads are electrically isolated from the plate. The cover may further comprise a nonconductive mount adapted to accommodate the second electronic component thereon. The nonconductive mount secures the one or more leads to the plate while electrically isolating the one or more leads from the plate. | 2008-12-25 |
20080318447 | Electronic Apparatus - According to one embodiment, an electronic apparatus includes a conductive layer provided on an outer surface of a housing, a conductive member provided inside the housing, and a connecting component attached to the housing. The housing is provided with a through hole which causes the inside of the housing to communicate with the outside. The connecting component has conductivity, and is provided with a major diameter section and a minor diameter section. The major diameter section is formed larger than the through hole, is opposed to the conductive layer from outside the housing, and is electrically connected to the conductive layer. The minor diameter section is formed smaller than the through hole, is inserted in the through hole to reach the inside of the housing, and is electrically connected to the conductive member. | 2008-12-25 |
20080318448 | DIMM SOCKET POSITIVE LOCK EXTRACTOR - A card edge connector including a housing and a pair of extractors is disclosed for electrically connecting a first PCB such as a daughter card to a second PCB such as a motherboard. The extractors both secure and eject the daughter card from the connector. The extractors may be configured to reduce micro-motion of the daughter card by applying a vertical downward force thereto. | 2008-12-25 |
20080318449 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED eSATA FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended External Serial Advanced Technology Attachment (eSATA) flash drive includes a MLC dual-personality extended eSATA plug connector connected to a flash drive and removably connectable to a host. The connector is adaptable to receive electoral data from both a USB and eSATA interface. | 2008-12-25 |
20080318450 | Preferential via exit structures with triad configuration for printed circuit boards - A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board. | 2008-12-25 |
20080318451 | Electrical connector provided with terminals constructed to simplify the assembly thereof - An electrical connector ( | 2008-12-25 |
20080318452 | Electrical connector - An electrical connector comprises a dielectric housing comprising a mating face, a rear face opposed to said mating face, and a plurality of first passages extending from said rear face to said mating face, a plurality of first conductive contacts respectively secured in said dielectric housing, wherein said first conductive contacts are manufactured according to the same specification, each first conductive contact comprises a retaining portion, a contacting portion extending from a end of said retaining portion, and a mounting portion extending from the end opposite to said contacting portion, wherein said retaining portions and contacting portions of said first conductive contacts are respectively inserted into corresponding said first passages at different depths, said retaining portion secured in corresponding said first passage, said contacting portion exposed in corresponding first passage, said mounting portion extending out from said rear face. | 2008-12-25 |
20080318453 | Compliant pin - A pin for insertion into a hole having a diameter and a plating therein is provided. The pin includes a compliant portion including a pair of outwardly biased beam members having an elongate opening therebetween. Each beam has a beam thickness. The beam thickness and the elongate opening are optimized with respect to the diameter such when the pin is inserted into the hole that the compliant portion is limited to a predetermined level of plastic deformation and the compliant portion is limited to a predetermined level of damage imparted upon the hole plating. | 2008-12-25 |
20080318454 | System and Method for Coupling an Integrated Circuit to a Circuit Board - An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit. | 2008-12-25 |
20080318455 | BACKPLANE CONNECTOR WITH HIGH DENSITY BROADSIDE DIFFERENTIAL SIGNALING CONDUCTORS - Embodiments of the present invention address deficiencies of the art in respect to backplane connectivity and provide a backplane connector for high density broadside differential signaling. In an embodiment of the invention, a backplane connector can be provided. The backplane connector can include a signal header assembly and a signal receptacle assembly. The signal header assembly can include pairs of differential signaling conductors arranged in columns for broadside signaling. Comparably, the signal receptacle assembly can include pairs of conductor receptacles arranged in columns to receive corresponding ones of the pairs of the differential signaling conductors. Finally, a surface mount (SMT) lead can be provided for each of the conductor receptacles and each of the signaling conductors | 2008-12-25 |
20080318456 | SAFETY LUER CONNECTION - A connection device has a male connector and a female connector. The female connector will only accommodate the dedicated male connector, thereby prohibiting a misconnection with the wrong male connector. In certain embodiments, a member prohibits male connectors, other than a dedicated male connector, from being inserted into the female connector. In certain other embodiments, a post prohibits male connectors, other than a dedicated male connector including a slot, from being inserted into the female connector. In still certain other embodiments, a series of prongs in the male connector and corresponding grooves in the female connector ensure the proper connection. Once the male connector is inserted and secured within the female connector, a fluid-tight seal is formed between the male connector and the female connector. | 2008-12-25 |
20080318457 | Electrical connector - An electrical connector ( | 2008-12-25 |
20080318458 | CONNECTOR - A connector includes female and male housings ( | 2008-12-25 |
20080318459 | Land grid array socket with improved fastening structure - a fastening structure comprises a stiffener including a first end and a second end opposite to the first end. A load plate is pivotally supported on a first end of the stiffener and has a pair of lateral walls. A lever is pivotally mounted on the lateral walls of the load plate and a locking portion to lock the load plate to the stiffener. An LGA socket using the fastening structure comprises an insulative housing having a plurality of contacts. A stiffener includes a first end and a second end and is positioned on a bottom surface of the insulative housing. A load plate is pivotally attached on the first end of the stiffener and has at least a lateral sidewall. A lever is pivotally mounted on the lateral sidewall, the lever and the load plate is being pivotal between an open position and a closed position together, the lever has a transverse locking portion to lock the load plate to the stiffener near the second end of the stiffener. | 2008-12-25 |
20080318460 | Electrical connection system - A connection position assurance retainer may include mechanisms for retaining connectors. For example, a female connector and a male connector may be mated and retained. Male and female terminals, the female terminal including a terminal insert, may also be provided. | 2008-12-25 |
20080318461 | PANEL-MOUNT CONNECTORS WITH LATCHING FEATURES - An electrical connector assembly is provided for mounting onto a panel having a panel opening. The connector assembly includes a connector and a latch. The latch is configured to mount on the connector, and attach to the panel as the housing is inserted into the opening. | 2008-12-25 |
20080318462 | Locking device for a shielded sub-miniature connection assembly - Locking device for a shielded sub-miniature connection assembly having two sub-miniature connectors with housings made of two molded thermoplastic half-shells, a high contact density miniature sub-assembly with a molded thermoplastic insulating body provided with contact cavities for the positioning and retention of contacts, wherein one of the housings includes on at least one of its faces a movable metal latch able to co-act with a slot made in at least one of the outside faces of the complementary housing. | 2008-12-25 |
20080318463 | LOOSE-PROOF CONNECTOR - A loose-proof connector includes a screwing sleeve and a connecting body. The screwing sleeve is an annular body and has a circular through hole. The inner wall of the circular through hole is provided with a plurality of recessed arcs that are arranged circumferentially. The connecting body is inserted into the circular through hole of the screwing sleeve. An annular band of the connecting body is provided with protruding arcs to correspond to each recessed arc. The protruding arcs oppose to the any one of the recessed arcs and thus are adjacent thereto. Via this arrangement, the protruding arcs can bounce between any two adjacent recessed arcs, thereby generating a locking effect, and thus the loose-proof effect can be surely achieved. | 2008-12-25 |
20080318464 | Electrical connector with cover configured for heat dissipation - An electrical connector assembly includes an insulative housing ( | 2008-12-25 |
20080318465 | CABLE INTERCONNECT SYSTEMS - In order to monitor connectivity status associated with an interconnect cable from the end-points to which either end of the cable is attached, a storage device storing a field replaceable unit identifier is provided to uniquely identify a cable end-point, which identifier can then be accessed to determine the connectivity status. | 2008-12-25 |
20080318466 | Electrical connector - An electrical connector ( | 2008-12-25 |
20080318467 | RELAY RECEPTACLE SHORTING PLUG - A relay receptacle shorting plug to short power contacts of a relay receptacle. The shorting plug includes a base having a plurality of terminals projecting from a first end of the base and the terminals have a physical arrangement to mate with contacts of the relay receptacle. The arrangement of the terminals allows for the shorting plug to be matably inserted into the relay receptacle. The terminals include first and second power terminals and at least one control terminal. The shorting plug also includes a closed conductive pathway between the first and second power terminals so that the shorting plug provides a current pathway between first and second power contacts of the relay receptacle. The relay receptacle shorting plug may provide an elongated structure to facilitate insertion and removal of the shorting plug with respect to the relay receptacle. | 2008-12-25 |
20080318468 | Electrical connector - An electrical connector comprises an elongate dielectric housing a plurality of conductive contacts and a pair of metal post. The dielectric housing comprises a pair of blocks on opposite elongate sides and a mating portion between said pair of blocks. Each said block comprises a planar mounting surface, an opposite upper surface, and through hole perpendicular to said mounting surface. The pair of metal posts are respectively inserted into said through holes in said pair of blocks, each metal post comprises a connecting portion stick out said mounting surface of said block, and a stop section hold on the upper surface of said block. The blocks can be made into a thin board, and the stop section of the post can be made into a thin cap. The total height of the block and post, from the mounting surface, can be made very low to meet the demand of smaller and thinner equipment. | 2008-12-25 |
20080318469 | Connector assembly with gripping sleeve - A connector assembly includes an electrical connector and a sleeve. The electrical connector has opposite first and second ends. The first end is rotatable with respect to the second end and configured to couple to a mating connector. The second end is configured to terminate a cable. The sleeve is molded over the first end such that the sleeve is fixed to the first end, and the sleeve and the first end of the connector together rotate with respect to the second end of the connector. Also, the sleeve has an outer gripping surface. | 2008-12-25 |
20080318470 | Coaxial Connector with Built-In Capacitor - A coaxial connector with a built-in capacitor includes: a core wire connection terminal having, on a rear end thereof, a core wire connection portion for connecting thereto a core wire of a coaxial cable; an inner terminal having, on a tip end thereof, a fitted/connected portion fitted and connected to an other party's terminal; an insulator holding the inner terminal while covering an outer circumference of the inner terminal, and having a holding hole of the core wire connection terminal on a rear end thereof; a shield terminal having, on a tip end thereof, a cylindrical shell portion that covers an outer circumference of the insulator, and having, on a rear end thereof, a shield conductor crimping portion for crimping and connecting thereto a shield conductor of the coaxial cable; and an inner dielectric that is sandwiched between a tip end portion of the core wire connection terminal and a rear end portion of the inner terminal, and thereby composes a capacitor function portion while using, as opposite electrodes, the tip end portion of the core wire connection terminal and the rear end portion of the inner terminal. | 2008-12-25 |
20080318471 | DEAD CABLE END - A dead cable end distributes holding force over a length of a cable end to reduce or eliminate damage to cables. The dead cable end includes a housing containing a plurality of collets each residing in a collet receptacle. Each collet includes a conical exterior and a lengthwise collet gap, and each collet receptacle includes a conical interior. The collets and collet receptacle are held inside the housing by a screw-in retaining nut, and the collet and collet receptacle pairs are compressed between the retaining nut and a spring inside the housing. The cable end resides inside the collets, and axial compressive forces on each collet and collet receptacle pair cause each collet to compress radially and hold the cable end. Anti-rotation pins are inserted through the housing into slots in the collet receptacle next to the screw-in retainer to prevent internal rotation during tightening. | 2008-12-25 |
20080318472 | END CONNECTOR FOR COAXIAL CABLE - A connector for attaching a cable to a terminal includes a connector body with a hex head fastener rotatably attached at one end of the body. A compressible gasket or clamp sleeve is positioned along the connector body for engaging and sealing about a portion of the jacket of the cable received within the connector. | 2008-12-25 |
20080318473 | FLUIDTIGHT CONNECTOR AND CONNECTOR ASSEMBLY - A watertight connector has a rubber member ( | 2008-12-25 |
20080318474 | WALL PLATE ASSEMBLY WITH INTEGRAL UNIVERSAL SERIAL BUS MODULE - A wall plate assembly including a wall plate with an integrated USB module. The assembly includes a USB connector and printed circuit board formed together on the wall plate as an integral whole. By placing USB extender circuitry directly on the printed circuit board, rather than in a separate housing, the present assembly can maintain its bus-powered attributes without the bulk of a separate extender housing. A quick-connect coupling enables fast electrical connection and disconnection with a complementary quick-connect coupling on a USB wire. | 2008-12-25 |
20080318475 | Portable Data Storage Apparatus With Connector Retraction - Portable data storage apparatus includes a housing having a front wall, and an opening in the front wall. A circuit board is located within the housing. A connector is electrically connected to the circuit board and extends outwardly therefrom for movement therewith. A cap is pivotally connected to the housing for movement relative to the housing between a first position and a second position. An operating mechanism operatively connects the cap and the circuit board for moving the circuit board and the connector with the movement of the cap. The circuit board and the connector are in a retracted position when the cap is in the first position, and are in an extended position when the cap is in the second position. | 2008-12-25 |
20080318476 | Cable Connector Assembly with Repairable Braid Termination - The invention relates to a cable connector assembly including a cable connector with metallic cover shells and a cable, said cable including a shielding braid in electrical connection with at least one of said metallic cover shells. A portion of said shielding braid is folded back over a support member provided for said cable to clamp said portion of said shielding braid between said support member and at least one of said metallic cover shells in a clamping portion of said cable connector. Accordingly a cable connector assembly is obtained with improved mechanical and electromagnetic shielding characteristics. The support member is not crimped on the cable jacket and may include multiple parts. The invention further relates to a cable connector and a method for assembling a cable to a cable connector. | 2008-12-25 |
20080318477 | Electrical Plug-in Connection and Method for the Identification of a Battery - An electrical plug connection for connecting a consumer or a charging device to a battery. The plug connection includes a plug part and a socket part. The part of the plug connection located on the battery side is provided with a transponder ( | 2008-12-25 |
20080318478 | MOLDED CARD EDGE CONNECTOR FOR ATTACHMENT WITH A PRINTED CIRCUIT BOARD - An edge connector suitable for attachment with a printed circuit board. The edge connector comprises a body composed of a plastic resin, the body defining a first end that is configured to operably attach to a portion of a printed circuit board and a second end configured to operably connect to a slot in a host device and a plurality of conductive traces and contact pads defined on a portion of a surface of the body, the traces being configured to electrically connect with corresponding traces defined on the printed circuit board. | 2008-12-25 |
20080318479 | Plug in the Field of Telecommunications, an Assembly Including a Telecommunications Module and a Plug, and a Method of Manufacturing a Plug | 2008-12-25 |
20080318480 | Electrical connection sheet having a frame embedded in an elastic insulator - An electrical connection sheet includes a plate-like elastic insulator having a first and a second principal surface which are spaced from each other in a predetermined direction. Columnar elastic conductors penetrate a center portion of the elastic insulator to protrude from the first and the second principal surfaces. A frame is embedded in a peripheral portion of the elastic insulator and extends along the peripheral portion. | 2008-12-25 |
20080318481 | Jet pump of personal watercraft - A jet pump of a personal watercraft of the present invention includes a pump casing | 2008-12-25 |
20080318482 | Marine Propulsion Control System and a Vessel Containing Such a Marine Propulsion Control System - A marine propulsion control system for controlling a set of propulsion units carried by a hull of a vessel, said marine propulsion control system including an input command regulator for generating a desired delivered thrust by the propulsion units in the set of propulsion units, a set of control units, wherein each control unit is associated with a separate propulsion unit in said set of propulsion units, wherein each control units is arranged to control the delivered thrust of the associated propulsion unit depending on input control signals received by the control unit and vessel including such a propulsion control unit. | 2008-12-25 |
20080318483 | Conductive Monofilament and Fabric - A conductive monofilament and static dissipative fabric having the same wherein the monofilament includes electrically conductive material and binder and has static dissipation properties. | 2008-12-25 |
20080318484 | Net Structure for Ball Game Court - A net structure for ball game court includes a plurality of wefts, warps, meshes formed at the nodes where the wefts and the warps intersect, and a plurality of grids are defined by the wefts and warps, and the wefts and the warps are made of a rope element woven one another. Several enhanced areas are formed in predetermined parts of the net structure employing double wefts and warps. | 2008-12-25 |
20080318485 | Core spun yarn and woven stretch fabric - A core spun yarn comprising a bi-component polyester filament and an elastomeric fiber. The polyester filament has a denier from about 20 to about 150 and the elastomeric fiber has a denier from 20 to 140. The polyester filament is about 2 weight percent to about 60 weight percent, based on total weight of the yarn and the elastomeric fiber is from about 1 percent to about 40 percent, based on total weight of the yarn. The elastomeric fiber may have higher draft than the bi-component polyester fiber. The polyester filament comprises poly (trimethylene terephthalate) and at least one polymer selected from the group consisting of poly (ethylene terephthalate) and poly (tetramethylene terephthalate) and said elastomeric fiber is spandex. The yarn may include a sheath of at least one staple fiber. The disclosure also includes a fabric of the bi-component polyester filament and an elastomeric fiber. | 2008-12-25 |
20080318486 | Industrial fabric with porous and controlled plasticized surface - The present invention relates to a process of obtaining an industrial fabric with porous and controlled plasticized surface and an industrial fabric with the mentioned characteristics thereof. The invention also relates to an industrial fabric such as press fabric for use in the press section of a paper machine with enhanced aesthetic properties by the use of plasticizers and optional heat and/or pressure treatment. | 2008-12-25 |
20080318487 | Method for Manufacturing a Particularly Soft and Three-Dimensional Nonwoven and Nonwoven Thus Obtained - The present invention relates to a method for manufacturing nonwoven and nonwoven obtainable by said method. Particularly, the invention relates to a nonwoven provided with improved tactile and absorbent characteristics, which make it suitable for use in the field of surface cleaning, personal hygiene, or formation of garments. | 2008-12-25 |
20080318488 | Deer rattling device - A rattling device to replicate the sound of antlers of bucks engaged in combat. The device comprises a rounded base body assembly, a striker assembly, a flexible spring that holds the striker assembly and base base body together, a leg strap, and a belt hanger. The rounded base body and the striker assembly are made of molded plastic. The rounded base body assembly contains a series of variably sized hollow nodes. The striker assembly comprises a series of similarly sized hollow nodes. The device is manufactured such that the nodes of the base plate face the nodes of the striker assembly. In the rest position, the nodes are held firmly against each other by the force of the flexible spring. When the hunter wants to replicate the sound of bucks battling each other, the striker assembly is pulled away from the rounded base body. The flexible elastic spring provides a force that opposes the action of the hunter. When the hunter releases the striker assembly, the spring forces it back into base plate where the nodes of the striker assembly impinge on the nodes of the rounded base body making the sound of the initial thrust of two battling bucks. As the hunter pulls the striker assembly slightly away from the rounded base body and slightly rotates the striker assembly, a sound is replicated that simulates the sound of the antlers of battling bucks continuing to engage each other at close quarters. The base plate and striker assembly are injection molded. The nodes of the base plate and striker assembly are hollow. The nodes face each other. The device contains a leg strap and belt hanger to affix it to the hunter's body or clothing. | 2008-12-25 |
20080318489 | Radiation curable arts and crafts toy - A kit and method for creating a 3-dimensional toy includes a battery powered light, a container filled with a light curable polymer and one or more molds into which the light curable polymer is inserted. Optimal the kit may also include one or more sheets of transparent material to which the light curable polymer does not adhere and coloring which can be added to the light curable polymer. The method of forming a the 3-dimensional toy involves obtaining a mold, dispensing a light curable polymer into the mold; and then curing the polymer by applying light in the visible or near visible range to the polymer via a battery powered light. | 2008-12-25 |
20080318490 | Dual output blower for an imflatable puppet - A dual output blower for inflatable puppet has a fan and a valve assembly. The fan has an inlet, a primary outlet and a valve outlet. The valve assembly comprises a body, a switching board and a driver. The body has a valve chamber formed in the body, a valve inlet, two valves and a blower output, each communicating with the valve chamber. The switching board is rotatably mounted in the valve chamber. The driver is mounted securely on the switching board and rotates the switching board to determine which valve of the valve assembly inputs and outputs air. When an inflatable puppet is connected to one of the valves of the valve assembly, the driver may control the orientation of the switching board to guide the air and make the inflatable puppet perform novel and entertaining movements. | 2008-12-25 |