52nd week of 2015 patent applcation highlights part 60 |
Patent application number | Title | Published |
20150372035 | APPLICATION OF REDUCED DARK CURRENT PHOTODETECTOR WITH A THERMOELECTRIC COOLER - A IDCA system combining thermo-electric cooler (TEC) and an internal nBn photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized. | 2015-12-24 |
20150372036 | IMAGE SENSOR AND IMAGE PROCESSING SYSTEM INCLUDING THE SAME - An image sensor is provided. The image sensor includes a first photoelectric conversion element and a second photoelectric conversion element, which are formed in a semiconductor substrate; a red color filter formed on the first photoelectric conversion element; a cyan color filter formed on the second photoelectric conversion element; and an organic photoelectric conversion layer formed on the red color filter and the cyan color filter, the organic photoelectric conversion layer configured to absorb wavelengths in a green range. | 2015-12-24 |
20150372037 | SOLID-STATE IMAGE SENSOR AND ITS MANUFACTURING METHOD, CURABLE COMPOSITION FOR FORMING INFRARED CUT-OFF FILTERS, AND CAMERA MODULE - A solid-state image sensor includes a semiconductor substrate, photoelectric conversion elements arranged on a light receiving surface side of the semiconductor substrate and making up pixels, and a filter layer disposed on a light incidence side of the photoelectric conversion elements so as to correspond to the photoelectric conversion elements. The filter layer includes at least red color filters, green color filters, blue color filters and infrared cut-off filters. The infrared cut-off filters are each arranged next to at least one of the red color filters, the green color filters and the blue color filters. The solid-state image sensor suppresses occurrence of deterioration of the spectral characteristics of an adjacent color filter of any of three primary colors. | 2015-12-24 |
20150372038 | IMAGE SENSOR AND IMAGE PROCESSING SYSTEM INCLUDING THE SAME - An image sensor capable of boosting a voltage of a floating diffusion node is provided. The image sensor includes a floating diffusion node and a storage element which are in a semiconductor substrate. The image sensor includes a first light-shielding material formed over the floating diffusion node, and a second light-shielding material formed over the storage diode. The second light-shielding material is separated from the first light-shielding material. The image sensor also includes a first voltage supply line configured to apply a first voltage to the first light-shielding material and a second voltage supply line configured to apply a second voltage lower than the first voltage to the second light-shielding material. | 2015-12-24 |
20150372039 | IMAGING APPARATUS - An imaging apparatus includes an image sensor and an image fiber that guides light incident from a focusing optical system toward the image sensor. The image sensor has such configuration that the distance in a first direction between two intersections is between ¼ times and ¾ times a pixel pitch of the image sensor, where one intersection is an intersection between a straight line passing through the center of the first sensor pixel and parallel to the first direction and a straight line connecting the center of the target pixel and the center of the adjacent pixel and the other intersection is an intersection between a straight line passing through the center of the second sensor pixel and parallel to the first direction and a straight line connecting the center of the target pixel and the center of the adjacent pixel. | 2015-12-24 |
20150372040 | Pixel Isolation Elements, Devices and Associated Methods - Light trapping pixels, devices incorporating such pixels, and various associated methods are provided. In one aspect, for example, a light trapping pixel device can include a light sensitive pixel having a light incident surface, a backside surface opposite the light incident surface, and a peripheral sidewall disposed into at least a portion of the pixel and extending at least substantially around the pixel periphery. The pixel can also include a backside light trapping material substantially covering the backside surface and a peripheral light trapping material substantially covering the peripheral sidewall. The light contacting the backside light trapping material or the peripheral light trapping material is thus reflected back toward the pixel. | 2015-12-24 |
20150372041 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer. | 2015-12-24 |
20150372042 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 2015-12-24 |
20150372043 | SOLID-STATE IMAGE PICKUP APPARATUS AND ELECTRONIC APPARATUS - A solid-state image pickup apparatus includes a pixel region in which a plurality of pixels each including a photoelectric conversion element are arranged, transfer wirings formed on the pixel region in parallel to each other with uniform opening widths, and different wirings formed in a wiring layer above the transfer wirings. At least a part of the different wirings is overlapped with the transfer wirings on a plan position. The transfer wirings and the different wirings form a light shielding structure in the pixel region. | 2015-12-24 |
20150372044 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a semiconductor integrated circuit device having pixel regions in a photodiode array region and having, in each of the pixel regions, a waveguide holding hole having a substantially perpendicular sidewall above the photodiode and embedded with a silicon oxide-based sidewall insulating film reaching the bottom surface of the hole and two or more silicon nitride-based insulating films having a higher refractive index on the inner side of the hole. This structure makes it possible to prevent deterioration of pixel characteristics of an imaging device, such as CMOS sensor, which is rapidly decreasing in size. | 2015-12-24 |
20150372045 | Backside Illumination Image Sensor Chips and Methods for Forming the Same - A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die. | 2015-12-24 |
20150372046 | A NOVEL IR IMAGE SENSOR USING A SOLUTION-PROCESSED PbS PHOTODETECTOR - An image sensor is constructed on a substrate that is a read-out transistor array with a multilayer array of infrared photodetectors formed thereon. The infrared photodetectors include a multiplicity of layers including an infrared transparent electrode distal to the substrate, a counter electrode directly contacting the substrate, and an infrared sensitizing layer that comprises a multiplicity of nanoparticles. The layers can be inorganic or organic materials. In addition to the electrodes and sensitizing layers, the multilayer stack can include a hole-blocking layer, an electron-blocking layer, and an anti-reflective layer. The infrared sensitizing layer can be PbS or PbSe quantum dots. | 2015-12-24 |
20150372047 | PHOTODIODE ARRAY HAVING A CHARGE-ABSORBING DOPED REGION - The invention concerns a photodiode array, and the method for producing same, comprising—a cathode comprising at least one substrate layer ( | 2015-12-24 |
20150372048 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device includes a plurality of pixels each including a photoelectric conversion section that generates an electric charge in accordance with incident light and a junction field-effect transistor that outputs an image signal in accordance with the electric charge generated by the photoelectric conversion section. The solid-state image pickup device includes a first element isolation region using an insulator and a second element isolation region using a pn junction, the first element isolation region and the second element isolation region being arranged in a region in which the plurality of pixels are arranged. | 2015-12-24 |
20150372049 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first film on a semiconductor substrate. The semiconductor substrate includes metal impurities, which may cause defects in the semiconductor device. A second film is formed on the first film such that the first film is between the second film and the semiconductor substrate. The first film, the second film, and the semiconductor substrate are heated. During the heating, which may occur during various manufacturing steps of the semiconductor device, the metal impurities from the semiconductor substrate diffuse into the second film. After the heating, the first and second films are removed from the semiconductor substrate. | 2015-12-24 |
20150372050 | IMAGE SENSOR HAVING LENS TYPE COLOR FILTER AND METHOD FOR FABRICATING THE SAME - The image sensor includes lens-type color filters having a uniform shape for a plurality of pixels. The image sensor includes a plurality of pixels formed in a substrate, a plurality of color filter housings formed over outer boundaries of the respective pixels, and a plurality of color filters filled in spaces defined by the respective color filter housings, wherein the clock filter housings surround edges of the respective color filters with a given curvature. | 2015-12-24 |
20150372051 | MICRO ASSEMBLED LED DISPLAYS AND LIGHTING ELEMENTS - The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 μm to 50 μm), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible. | 2015-12-24 |
20150372052 | MICRO ASSEMBLED LED DISPLAYS AND LIGHTING ELEMENTS - The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 μm to 50 μm), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible. | 2015-12-24 |
20150372053 | MICRO ASSEMBLED LED DISPLAYS AND LIGHTING ELEMENTS - The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 μm to 50 μm), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible. | 2015-12-24 |
20150372054 | MONOLITHIC SEMICONDUCTOR CHIP ARRAY - A semiconductor chip ( | 2015-12-24 |
20150372055 | NON-VOLATILE RANDOM ACCESS MEMORY DEVICES WITH SHARED TRANSISTOR CONFIGURATION AND METHODS OF FORMING THE SAME - Embodiments of non-volatile random access memory (RAM) devices and methods of forming the same are provided herein. In an embodiment, a non-volatile RAM device includes a first access transistor that is in electrical communication with a wordline. A first memory element and a first two-terminal selector are serially connected to each other and are in electrical communication with a first bitline and the first access transistor. A second memory element and a second two-terminal selector are serially connected to each other and are in electrical communication with a second bitline and the first access transistor. | 2015-12-24 |
20150372056 | SEMICONDUCTOR DIODES, AND VARIABLE RESISTANCE MEMORY DEVICES - A semiconductor diode includes a first semiconductor pattern including a first impurity, a first diffusion barrier pattern on the first semiconductor pattern, an intrinsic semiconductor pattern on the first diffusion barrier pattern, a second diffusion barrier pattern on the intrinsic semiconductor pattern, and a second semiconductor pattern including a second impurity on the second diffusion barrier pattern. | 2015-12-24 |
20150372057 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE HAVING LATERAL CHANNEL - A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material. | 2015-12-24 |
20150372058 | METHOD FOR FABRICATING SEMICONDUCTOR APPARATUS - A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar. | 2015-12-24 |
20150372059 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer. | 2015-12-24 |
20150372060 | Memory Devices Having Low Permittivity Layers and Methods of Fabricating the Same - A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers. | 2015-12-24 |
20150372061 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING A CROSS POINT CELL ATRRAY - A method of fabricating a semiconductor device is provided. The method includes an intermediate pattern structure on a substrate. The intermediate pattern structure includes a pair of first conductive lines extending in a first direction, a pair of first conductive connectors connecting end portions the pair of first conductive lines to each other, a pair of second conductive lines intersecting the pair of first conductive lines, and a pair of second conductive connectors connecting end portions of the pair of second conductive lines to each other. The first and second conductive connectors are selectively removed using a cut mask pattern to separate the pair of first conductive lines from each other and to separate the pair of second conductive lines from each other. | 2015-12-24 |
20150372062 | METHOD FOR PRODUCING AN OPTOELECTRONIC ASSEMBLY, AND OPTOELECTRONIC ASSEMBLY - A method for producing an optoelectronic assembly having a first and at least a second optoelectronic components may include forming a first electrically conductive layer on a substrate, forming a second electrically conductive layer on the first electrically conductive layer, applying an insulator material on the second electrically conductive layer and the substrate, such that at least a first insulator region, which insulates a first component region from a second component region, a second insulator region, which insulates the second component region from a first contact region, a third insulator region arranged on a side of the first component region, and a fourth insulator region arranged between the first and second insulator regions on a side of the second component region are formed by the insulator material, forming a first and second optically functional layers in the first and second component regions, respectively, and applying an electrically conductive electrode layer. | 2015-12-24 |
20150372063 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display (OLED) device, and a method of manufacturing the OLED device are discussed. The OLED device according to one embodiment includes a substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode formed on the substrate; a first bank layer and a second bank layer formed on the substrate; and a first organic light emitting layer, a second organic light emitting layer, and a third organic light emitting layer formed on the first pixel electrode, the second pixel electrode, and the third pixel electrode, respectively. The first organic light emitting layer overlaps the second organic light emitting layer on the first bank layer. | 2015-12-24 |
20150372064 | DISPLAY DEVICE - A display device includes a light scattering layer to scatter light from a light emitter. The light scattering layer includes a liquid crystal layer between a first electrode and a second electrode. The liquid crystal layer includes cholesteric liquid crystals which scatter light from the light emitter based on an intensity of an applied electric field. | 2015-12-24 |
20150372065 | DISPLAY DEVICE AND ELECTRONIC DEVICE - A display device having a reduced frame width and a shape that is not significantly different from the shape of a display region is provided even in the case where the display region is non-rectangular. The display device includes a display region and a terminal electrode. The terminal electrode overlaps with the display region and is electrically connected to an external electrode through the non-display side of the display region. | 2015-12-24 |
20150372066 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate, an optical layer formed over the substrate and a light emitting pixel formed over the optical layer. The optical layer includes a first refractive index layer portion having a first refractive index, a second refractive index layer portion having a second refractive index greater than the first refractive index. The second portion is disposed next to the first portion and contacts the first portion. The light emitting pixel includes a pixel electrode overlapping the first portion and comprising a first reflective layer, a pixel-defining film overlapping the second portion, an intermediate layer formed over the pixel electrode and comprising an organic light emission layer, and an opposite electrode formed over and overlapping the intermediate layer and the pixel-defining film and comprising a second reflective layer. | 2015-12-24 |
20150372067 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device includes a substrate having an emission area and a dummy area that surrounds the emission area, a plurality of sub-pixels disposed on the emission area of the substrate, and a plurality of dummy pixels disposed on the dummy area of the substrate, each dummy pixel including a plurality of fine patterns. | 2015-12-24 |
20150372068 | DISPLAY DEVICE - A display device includes a substrate, a thin film transistor unit disposed on the substrate, and a shielding unit disposed between the substrate and the thin film transistor unit. The thin film transistor unit includes a gate, an insulating layer, a semiconductor layer, a source, and a drain. The shielding unit includes a shielding layer and a first buffer layer. The first buffer layer is disposed between the shielding layer and the thin film transistor. Light with a wavelength of 200 nm to 510 nm has a transmittance between 0 to 15% when passing through the shielding layer. | 2015-12-24 |
20150372069 | LIGHT EMITTING DISPLAY APPARATUS - There is provided a light emitting display apparatus including at least a light emitting element and a thin film transistor (TFT) for driving the light emitting element, characterized in that a mechanism is provided in which a semiconductor constituting the TFT is irradiated with at least a part of light whose wavelength is longer than a predetermined wavelength among the light emitted by the light emitting element. | 2015-12-24 |
20150372070 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels. Each of the pixels includes a first insulating layer and first and second signal lines spaced apart from each other. At least a portion of the first and second signal lines is formed over the first insulating layer. Each pixel also includes a second insulating layer interposed between the first and second signal lines. The second insulating layer has a lower permittivity that the first insulating layer. | 2015-12-24 |
20150372071 | DISPLAY MODULE - Organic EL display module including a pixel disposed in respective intersections between a plurality of scanning lines and a plurality of data lines, which lines are aligned in a matrix, and a current supply line that supplies electric current to the pixel, wherein the pixel includes an active device selected by the scanning line, a data storage device that stores a data signal that is supplied from the data line by control of the active device, and an organic light emitting device that emits light by the electric current supplied by the current supply line according to the data signal stored in the data storage device, wherein the data storage device provides a lower electrode, an insulating layer and an upper electrode, and wherein the lower electrode has a same layer with a channel layer of the active device and the upper electrode is made of a metal material. | 2015-12-24 |
20150372072 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL, ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE, AND METHOD FOR FABRICATING ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL - An organic light emitting diode (OLED) display panel is disclosed. The display panel includes a substrate, and a Thin-film Transistor (TFT) disposed on the substrate. The TFT includes a source electrode, and a drain electrode. The display panel also includes a power line disposed above the substrate, an auxiliary electrode electrically connected to the power line, and a signal input terminal, electrically connected to the power line and providing an input signal. A first collective portion of the auxiliary electrode and the power line has a first length and a first resistance. A second collective portion of the auxiliary electrode and the power line has a second length and a second resistance. The first collective portion is between the second collective portion and the signal input terminal. The first length is equal to the second length, and the first resistance is greater than the second resistance. | 2015-12-24 |
20150372073 | Coil and Method of Manufacturing a Coil - A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening. | 2015-12-24 |
20150372074 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride. | 2015-12-24 |
20150372075 | EDGE TERMINATION STRUCTURE FOR A POWER INTEGRATED DEVICE AND CORRESPONDING MANUFACTURING PROCESS - An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane. | 2015-12-24 |
20150372076 | Semiconductor Switching Device with Different Local Cell Geometry - A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. | 2015-12-24 |
20150372077 | PROCESSES USED IN FABRICATING A METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET. | 2015-12-24 |
20150372078 | MODULATED SUPER JUNCTION POWER MOSFET DEVICES - A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns. | 2015-12-24 |
20150372079 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a non-volatile semiconductor memory device includes plural gate electrodes in which a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode layer are sequentially stacked on a semiconductor substrate, in which the control gate electrode layer includes a polysilicon layer that is formed on the second insulating film and a metal layer that is formed on the polysilicon layer, and a portion of the metal layer having the maximum width dimension is positioned above a lower end portion of the metal layer. | 2015-12-24 |
20150372080 | SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET - A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. | 2015-12-24 |
20150372081 | IMPROVING LINEARITY IN SEMICONDUCTOR DEVICES - A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region. | 2015-12-24 |
20150372082 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN - A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed. | 2015-12-24 |
20150372083 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET INTERCONNECTING A SOURCE REGION AND A DRAIN REGION - A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed. | 2015-12-24 |
20150372084 | RAISED FIN STRUCTURES AND METHODS OF FABRICATION - A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench. | 2015-12-24 |
20150372085 | LAYOUTS AND VERTICAL STRUCTURES OF MOSFET DEVICES - A metal-oxide-semiconductor field-effect transistor device includes a first active area, a first gate electrode configured to cross the first active area and extend in a Y direction, and define a first source area and a first drain area, first gate contacts disposed on the first gate electrode to align on a first virtual gate passing line extending in the Y direction, first source contacts disposed on the first source area to align on a first virtual source passing line extending in the Y direction, and first drain contacts disposed on the first drain area to align on a first virtual drain passing line extending in the Y direction, wherein at least one of the first drain contacts is disposed to align on any one of first virtual X-straight lines configured to pass between the first source contacts and extend parallel in an X direction perpendicular to the Y direction. | 2015-12-24 |
20150372086 | Semiconductor Switching Device with Different Local Threshold Voltage - A semiconductor device includes a semiconductor substrate having a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A a gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a first threshold and at least a second switchable region having a second threshold which is higher than the first threshold. An area assumed by the first switchable region is larger than an area assumed by the second switchable region. | 2015-12-24 |
20150372087 | Semiconductor Switching Devices with Different Local Transconductance - A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. The active area defined by the switchable cells includes at least a first switchable region having a first transconductance and a second switchable region having a second transconductance which is different from the first transconductance. | 2015-12-24 |
20150372088 | CELLULAR LAYOUT FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is substantially disposed over the center of the semiconductor device cell. The SSBC also includes at least one source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC. | 2015-12-24 |
20150372089 | CELLULAR LAYOUT FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC. | 2015-12-24 |
20150372090 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced. | 2015-12-24 |
20150372091 | SEMICONDUCTOR CHIP CARRIERS WITH MONOLITHICALLY INTEGRATED QUANTUM DOT DEVICES AND METHOD OF MANUFACTURE THEREOF - A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains. | 2015-12-24 |
20150372092 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage. | 2015-12-24 |
20150372093 | WIDE BANDGAP HIGH-DENSITY SEMICONDUCTOR SWITCHING DEVICE AND MANUFACTURING PROCESS THEREOF - A switching device, such as a barrier junction Schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them. A contact metal layer having homogeneous chemical-physical characteristics extends on and in direct contact with the top surface of the body and forms Schottky contact metal portions with the surface portions of the body and ohmic contact metal portions with the switching regions. The contact metal layer is formed by depositing a nickel or cobalt layer on the body and carrying out a thermal treatment so that the metal reacts with the semiconductor material of the body and forms a silicide. | 2015-12-24 |
20150372094 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode. | 2015-12-24 |
20150372095 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A MOS gate structure including a p base region, a p epitaxial layer, an n | 2015-12-24 |
20150372096 | High Electron Mobility Transistors and Integrated Circuits with Improved Feature Uniformity and Reduced defects for Microwave and Millimetre Wave Applications - High mobility transistors and microwave integrated circuits with an improved uniformity of the width of the smallest of features, an increased lithographic yield and reduced defects in the active components are provided. Before and during fabrication, a first grooving process is performed to partially or completely remove composite epitaxial layers in the field lanes to reduce the initial bow to be smaller than DOF range and to improve the uniformity of the critical dimension. A second grooving process may also be performed to remove composite epitaxial layers in the dicing lanes to further improve the uniformity of the width of the smallest features for the devices and circuits to be made. | 2015-12-24 |
20150372097 | METHOD OF FORMING III-V CHANNEL - Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap. | 2015-12-24 |
20150372098 | HETEROJUNCTION BIPOLAR TRANSISTORS FOR IMPROVED RADIO FREQUENCY (RF) PERFORMANCE - The present disclosure relates to heterojunction bipolar transistors for improved radio frequency (RF) performance. In this regard, a heterojunction bipolar transistor includes a base, an emitter, and a collector. The base is formed over the collector such that a base-collector junction is formed between the base and the collector. The base-collector junction is configured to become forward-biased at a first turn-on voltage. The emitter is formed over the base such that a base-emitter junction is formed between the base and the emitter. The base-emitter junction is configured to become forward-biased at a second turn-on voltage, as opposed to the first turn-on voltage. Notably, the second turn-on voltage is lower than the first turn-on voltage. | 2015-12-24 |
20150372099 | CONTACT SILICIDE FORMATION USING A SPIKE ANNEALING PROCESS - A substrate is provided. The substrate has a source/drain region formed therein and a dielectric layer formed thereover. A contact hole is etched in the dielectric layer to expose a portion of the source/drain region. A metal material is formed on the source/drain region exposed by the opening. A first annealing process is performed to facilitate a reaction between the metal material and the portion of the source/drain region disposed therebelow, thereby forming a metal silicide in the substrate. The first annealing process is a spike annealing process. A remaining portion of the metal material is removed after the performing of the first annealing process. Thereafter, a second annealing process is performed. Thereafter, a contact is formed in the contact hole, the contact being formed on the metal silicide. | 2015-12-24 |
20150372100 | INTEGRATED CIRCUITS HAVING IMPROVED CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact. | 2015-12-24 |
20150372101 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region. | 2015-12-24 |
20150372102 | SEMICONDUCTOR DEVICE - The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced. | 2015-12-24 |
20150372103 | SPLIT GATE POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR - The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures. | 2015-12-24 |
20150372104 | MULTI-CHANNEL GATE-ALL-AROUND FET - A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs. | 2015-12-24 |
20150372105 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial channel layer positioned in between the high-k gate dielectric layer and the substrate. A length of the epitaxial channel layer is larger than a length of the metal gate, and a bottom of the epitaxial channel layer and the substrate are coplanar. | 2015-12-24 |
20150372106 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film. | 2015-12-24 |
20150372107 | SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS - Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions. | 2015-12-24 |
20150372108 | METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH - Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented. | 2015-12-24 |
20150372109 | REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY - After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed. | 2015-12-24 |
20150372110 | SEMICONDUCTOR FIN FABRICATION METHOD AND FIN FET DEVICE FABRICATION METHOD - A semiconductor fin fabrication method includes: providing a substrate; selectively epitaxially growing a first mask layer in a predetermined zone on the substrate; selectively epitaxially growing a first epitaxial layer on the substrate by using the first mask layer as a mask; and removing the first mask layer and a part, under the first mask layer, of the substrate by using the first epitaxial layer as a mask and by using an anisotropic etching method, so as to form a fin under the first epitaxial layer. According to the foregoing solutions, a manner in which a selective epitaxial growth technology and an anisotropic etching technology are combined is used It can be ensured that a semiconductor fin and a surface of a gate oxidized layer are perpendicular to each other, roughness of a surface of the semiconductor fin is reduced, and a fin with a smooth side surface is formed. | 2015-12-24 |
20150372111 | METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES - A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers. | 2015-12-24 |
20150372112 | REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY - After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed. | 2015-12-24 |
20150372113 | METHOD AND STRUCTURE FOR ENABLING HIGH ASPECT RATIO SACRIFICIAL GATES - Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. | 2015-12-24 |
20150372114 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench. | 2015-12-24 |
20150372115 | METHODS OF FORMING NANOWIRE DEVICES WITH DOPED EXTENSION REGIONS AND THE RESULTING DEVICES - A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device. | 2015-12-24 |
20150372116 | Apparatus and Method for Multiple Gate Transistors - A method comprises etching away an upper portion of a substrate to form a trench between two adjacent isolation regions, wherein the substrate has a first crystal orientation and is formed of a first semiconductor material, growing a first semiconductor region in the trench over the substrate, wherein the first semiconductor region is formed of a second semiconductor material and an upper portion of the first semiconductor region has a second crystal orientation and growing a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is formed of a third semiconductor material. | 2015-12-24 |
20150372117 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an N | 2015-12-24 |
20150372118 | METHOD FOR FABRICATING VERTICALLY STACKED NANOWIRES FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the substrate further comprising a patterned hardmask layer disposed on the multi-material layer, etching the multi-material layer through openings defined by the patterned hardmask layer to expose sidewalls of the first and the second layer of the multi-material layer, and laterally and selectively etching the second layer from the substrate. | 2015-12-24 |
20150372119 | METHOD FOR FABRICATING VERTICALLY STACKED NANOWIRES FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein. | 2015-12-24 |
20150372120 | Fin Structure of Semiconductor Device - A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized. | 2015-12-24 |
20150372121 | ASYMMETRIC FORMATION APPROACH FOR A FLOATING GATE OF A SPLIT GATE FLASH MEMORY STRUCTURE - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided. | 2015-12-24 |
20150372122 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device which occupies a small area and is highly integrated. A first conductive layer is formed; a first insulating layer is formed over the first conductive layer; a second conductive layer is formed over the first insulating layer using the same material as the first conductive layer; a third conductive layer is formed over the second conductive layer; a second insulating layer is formed over the third conductive layer; a resist mask is formed over the second insulating layer; etching is successively performed from the upper layer and an opening is formed in the first conductive layer and the diameter of the opening in the second conductive layer is increased in the same step; and a contact hole where an upper surface of the first conductive layer is exposed is formed by etching the first insulating layer. | 2015-12-24 |
20150372123 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film. | 2015-12-24 |
20150372124 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer including carbon and having a first side and an opposing second side. The semiconductor device further includes an intrinsic nitride semiconductor layer on the first nitride semiconductor layer. A first side of the intrinsic semiconductor layer faces the second side of the first nitride semiconductor layer. The semiconductor device further includes a second nitride semiconductor layer including aluminum and disposed on a second side of the intrinsic nitride semiconductor layer opposite to the first nitride semiconductor layer. The first nitride semiconductor layer has a carbon distribution in which a concentration of carbon changes between a high concentration region and a low concentration region. In some embodiments, the high concentration region has a carbon concentration at least 100 times higher than the carbon concentration in the low concentration region. | 2015-12-24 |
20150372125 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon. | 2015-12-24 |
20150372126 | MULTICHANNEL TRANSISTOR - A field effect transistor (FET) comprises a plurality of substantially parallel conductive channels ( | 2015-12-24 |
20150372127 | METHOD AND STRUCTURE FOR ENABLING HIGH ASPECT RATIO SACRIFICIAL GATES - Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. | 2015-12-24 |
20150372128 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The silicon carbide film includes a second range having a second breakdown voltage holding layer, a channel forming region, and a source region. The first and second breakdown voltage holding layers constitutes a breakdown voltage holding region having a thickness in an element portion. When voltage is applied to attain a maximum electric field strength of 0.4 MV/cm or more in the breakdown voltage holding region during an OFF state, a maximum electric field strength in the second range within the element portion is configured to be less than ⅔ of a maximum electric field strength in the first range. | 2015-12-24 |
20150372129 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively. | 2015-12-24 |
20150372130 | POWER DEVICE TERMINATION STRUCTURES AND METHODS - Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors. | 2015-12-24 |
20150372131 | CHARGED BALANCED DEVICES WITH SHIELDED GATE TRENCH - This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown. | 2015-12-24 |
20150372132 | SEMICONDUCTOR DEVICE WITH COMPOSITE TRENCH AND IMPLANT COLUMNS - A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column. | 2015-12-24 |
20150372133 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2015-12-24 |
20150372134 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure comprises a substrate, a first well formed in the substrate, a first heavily doped region formed in the first well, a second heavily doped region formed in the substrate and separated apart from the first well, a second well formed in the substrate and under the second heavily doped region, a gate dielectric formed on the substrate between the first heavily doped region and the second heavily doped region, and a gate electrode formed on the gate dielectric. The gate dielectric has a substantially uniform thickness across at least a portion extending from a side close to the second heavily doped region. The first well has a first type of doping. The first heavily doped region, the second heavily doped region and the second well have a second type of doping. | 2015-12-24 |