52nd week of 2015 patent applcation highlights part 58 |
Patent application number | Title | Published |
20150371835 | PHOTOMULTIPLIER AND ITS MANUFACTURING METHOD - The present invention relates to a photomultiplier having a structure for making it possible to easily realize high detection accuracy and fine processing, and a method of manufacturing the same. The photomultiplier comprises an enclosure having an inside kept in a vacuum state, whereas a photocathode emitting electrons in response to incident light, an electron multiplier section multiplying in a cascading manner the electron emitted from the photocathode, and an anode for taking out a secondary electron generated in the electron multiplier section are arranged in the enclosure. A part of the enclosure is constructed by a glass substrate having a flat part, whereas each of the electron multiplier section and anode is two-dimensionally arranged on the flat part in the glass substrate. | 2015-12-24 |
20150371836 | SATURATION CORRECTION FOR ION SIGNALS IN TIME-OF-FLIGHT MASS SPECTROMETERS - The invention relates to time-of-flight mass spectrometers in which individual time-of-flight spectra are measured by detection systems with limited dynamic measurement range and are summed to sum spectra. The invention proposes a method to increase the dynamic range of measurement of the spectrum. To achieve this, those ion signals whose measured values display saturation of the analog-to-digital converter (ADC) are replaced by correction values, particularly if several successive measured values are in saturation. The correction values are obtained from the width of the signals, preferably simply from the number of measured values in saturation. | 2015-12-24 |
20150371837 | METHOD AND DEVICE FOR MASS SPECTROMETRY - A mass spectrometry is equipped with a liquid specimen supply part which supplies a liquid specimen sandwiched between bubbles, an ion source part ionizes the specimen, and a mass spectrometry part which detects ions separated in accordance with mass. In particular the ion source part is configured so as to include a liquid supply tube for transporting a specimen from the liquid specimen supply part, a degassing/liquid retention part in which bubbles are removed, a spraying part which ionizes the specimen, and a high-voltage power supply part which applies a high voltage to the spraying part. The device is further characterized in that after removing the bubbles, a Taylor cone is formed from the resultant pre-solution, and the specimen is ionized thereafter. Thus, the ionization of an intended specimen is stabilized, and the measurement reproducibility is improved. | 2015-12-24 |
20150371838 | Curved Ion Guide with Non Mass to Charge Ratio Dependent Confinement - A non-linear ion guide is disclosed comprising a plurality of electrodes. An ion guiding region is arranged between the electrodes, and the ion guiding region curves at least in a first direction. A DC voltage is applied to at least some of the electrodes in order to form a DC potential well which acts to confine ions within the ion guiding region in the first direction. | 2015-12-24 |
20150371839 | ION TRANSPORT DEVICE AND MASS ANALYSIS DEVICE - A first ion transport unit with an ion funnel structure having high acceptance is arranged in the front half and a second ion transport unit with a Q-array structure having low emittance and high gas conductance is arranged in the rear half, and an aperture electrode to which only direct current voltage is applied is provided between them. The inside diameter of the opening of the aperture electrode is made larger than the inside diameter of the opening of the ring electrode at the last stage of the first ion transport unit, and the inscribed circle diameter of the first stage electrode plate of the second ion transport unit is made larger still. As a result, interference of high frequency electric fields between the first ion transport unit and the second ion transport unit | 2015-12-24 |
20150371840 | ION INJECTION DEVICE FOR A TIME-OF-FLIGHT MASS SPECTROMETER - The invention provides methods and devices to pulse ions from an RF ion storage into the flight tube of a time-of-flight mass spectrometer. The pusher cell comprises essentially two parallel plates, both plates completely slotted into two electrically insulated halves. The four half plates can be supplied with RF voltages to form a two-dimensional quadrupole field in the center between the slits, or with DC voltages to form a homogeneous acceleration field to eject ions. The RF quadrupole field is not ideal, but sufficiently good to store ions, to damp the ions by an additional collision gas, and to form a fine thread of ions in the axis of the quadrupole field. The DC acceleration field is extremely homogeneous; slight distortions near the slits can be corrected by external electrodes. The ideal acceleration field results in a high mass resolution and the device does not show any mass discrimination. | 2015-12-24 |
20150371841 | LIGHT SOURCE DEVICE AND PROJECTOR - In one embodiment, a light source device comprises an arc tube having a first sealing portion extending from a light emission portion. A reflection mirror is attached to neighbor the first sealing portion and has a concave reflection surface. A container accommodates the arc tube and the reflection mirror. A branch portion has a first opening which branches a part of a cooling air flowing within the container to guide the cooling air to the arc tube. First and second duct portions are each connected to the branch portion. The first and second duct portions extend along a center axis of a light reflected by the reflection mirror such that the air flows in a direction opposite to a traveling direction of the light reflected by the reflection surface. A guiding member directs the air toward the first or second duct portion by moving by its own weight. | 2015-12-24 |
20150371842 | SULFUR LAMP - A sulfur lamp having low microwave leakage includes a structure made of a plurality of electrically conductive strips. The lamp cage is formed from respective halves removably joined together and configured to be resonant at the microwave frequency generated by the magnetron, in a mode that induces wall currents parallel to the joints formed by joining the halves together. | 2015-12-24 |
20150371843 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus. The method includes: forming a first layer including a first element on a substrate by supplying a gas containing the first element; forming a second layer including first and second elements by supplying a gas containing the second element to modify the first layer; and forming a thin film having a predetermined thickness by setting the forming of the first layer and the forming of the second layer to one cycle and repeating the cycle at least once. Pressure, or pressure and a gas supply time in one process of the forming of the first layer and the forming of the second layer are controlled to be higher or longer, or lower or shorter than pressure, or pressure and a time in the one process when the thin film having a stoichiometric composition is formed. | 2015-12-24 |
20150371844 | PROCESS FOR PRODUCING A GALLIUM ARSENIDE SUBSTRATE, GALLIUM ARSENIDE SUBSTRATE AND USE THEREOF - The present invention relates to a novel process for producing a surface-treated gallium arsenide substrate as well as novel provided gallium arsenide substrates as such as well as the use thereof. The improvement of the process according to the invention is based on a particular final surface treatment with an oxidation treatment of at least one surface of the gallium arsenide substrate in dry condition by means of UV radiation and/or ozone gas, a contacting of the at least one surface of the gallium arsenide substrate with at least one liquid medium and a Marangoni drying of the gallium arsenide substrate. The gallium arsenide substrates provided according to the invention exhibit a so far not obtained surface quality, in particular a homogeneity of surface properties, which is detectable by means of optical surface analyzers, specifically by means of ellipsometric lateral substrate mapping for the optical contact-free quantitative characterization. | 2015-12-24 |
20150371845 | SURFACE TREATMENT APPARATUS AND METHOD FOR SEMICONDUCTOR SUBSTRATE - In one embodiment, a surface treatment apparatus for a semiconductor substrate includes a holding unit, a first supply unit, a second supply unit, a third supply unit, a drying treatment unit, and a removal unit. The holding unit holds a semiconductor substrate with a surface having a convex pattern formed thereon. The first supply unit supplies a chemical solution to the surface of the semiconductor substrate, to perform cleaning and oxidation. The second supply unit supplies pure water to the surface of the semiconductor substrate, to rinse the semiconductor substrate. The third supply unit supplies a water repelling agent to the surface of the semiconductor substrate, to form a water repellent protective film on the surface of the convex pattern. The drying treatment unit dries the semiconductor substrate. The removal unit removes the water repellent protective film while making the convex pattern remain. | 2015-12-24 |
20150371846 | LAYER-BY-LAYER DEPOSITION OF CARBON-DOPED OXIDE FILMS THROUGH CYCLICAL SILYLATION - Embodiments of the present invention generally relate to methods of forming carbon-doped oxide films. The methods generally include generating hydroxyl groups on a surface of the substrate using a plasma, and then performing silylation on the surface of the substrate. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma in order to perform an additional silylation. Multiple plasma treatments and silylations may be performed to deposit a layer having a desired thickness. | 2015-12-24 |
20150371847 | METHOD FOR CONTROLLING SEMICONDUCTOR DEPOSITION OPERATION - The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof. | 2015-12-24 |
20150371848 | METHOD FOR THE FABRICATION AND TRANSFER OF GRAPHENE - Provided herein are processes for transferring high quality large-area graphene layers (e.g., single-layer graphene) to a flexible substrate based on preferential adhesion of certain thin metallic films to graphene followed by lamination of the metallized graphene layers to a flexible target substrate in a process that is compatible with roll-to-roll manufacturing, providing an environmentally benign and scalable process of transferring graphene to flexible substrates. | 2015-12-24 |
20150371849 | METHOD FOR THE REUSE OF GALLIUM NITRIDE EPITAXIAL SUBSTRATES - A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates. | 2015-12-24 |
20150371850 | METHOD OF FORMING SEMICONDUCTOR THIN FILM - Provided is a method of forming a semiconductor thin film. The method may include forming, on a substrate, a thin film that contains one of Ge, Si, and a SiGe mixture, and Sn in a content of 0.1 atomic % or more to 20 atomic % or less, and applying pulsed laser light to the thin film. | 2015-12-24 |
20150371851 | AMORPHOUS CARBON DEPOSITION PROCESS USING DUAL RF BIAS FREQUENCY APPLICATIONS - Methods for forming an amorphous carbon layer with desired film mechanical strength low film stress as well as optical film properties are provided. In one embodiment, a method of forming an amorphous carbon layer includes forming a plasma of a deposition gas mixture including a hydrocarbon gas supplied in a processing chamber by application of a RF source power, applying a low frequency RF bias power and a high frequency RF bias power to a first electrode disposed in the processing chamber, controlling a power ratio of the high frequency to the low frequency RF bias power, and forming an amorphous carbon layer on a substrate disposed in the processing chamber. | 2015-12-24 |
20150371852 | SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOMETER TECHNOLOGY - The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer. | 2015-12-24 |
20150371853 | COATING TREATMENT METHOD WITH AIRFLOW CONTROL, AND NON-TRANSITORY RECORDING MEDIUM HAVING PROGRAM RECORDED THEREON FOR EXECUTING COATING TREATMENT WITH AIRFLOW CONTROL - A coating treatment apparatus supplying a coating solution to a front surface of a rotated substrate and diffusing the supplied coating solution to an outer periphery side of the substrate to thereby apply the coating solution on the front surface of the substrate includes: a substrate holding part holding a substrate; a rotation part rotating the substrate held on the substrate holding part; a supply part supplying a coating solution to a front surface of the substrate held on the substrate holding part; and an airflow control plate provided at a predetermined position above the substrate held on the substrate holding part for locally changing an airflow above the substrate rotated by the rotation part at an arbitrary position. | 2015-12-24 |
20150371854 | METHODS FOR FABRICATING REFINED GRAPHITE-BASED STRUCTURES AND DEVICES MADE THEREFROM - Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device. | 2015-12-24 |
20150371855 | APPARATUS FOR ETCHING TWO-DIMENSIONAL MATERIAL AND METHOD OF PATTERNING TWO-DIMENSIONAL MATERIAL USING THE SAME - According to example embodiments, an apparatus for etching a two-dimensional material layer includes a stage configured to support an etching target including graphene on the stage, a light source configured to emit light having a wavelength that is shorter than a wavelength of visible light, a mask imprinted with a pattern for transferred onto the etching target, a fluid inlet configured to supply a fluid over the etching target, and a fluid outlet configured to absorb a residue and a reaction product after the fluid is supplied over the etching target using the fluid inlet. | 2015-12-24 |
20150371856 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is prepared. A surface electrode is formed in contact with the first main surface of the silicon carbide substrate. An adhesive tape is adhered to the surface electrode so as to cover the surface electrode. The silicon carbide substrate is heated at a first pressure lower than atmospheric pressure, with the adhesive tape being adhered to the surface electrode. After the silicon carbide substrate is heated, the second main surface of the silicon carbide substrate is ground. After the second main surface is ground, the second main surface of the silicon carbide substrate is processed at a second pressure lower than atmospheric pressure, with the adhesive tape being adhered to the surface electrode. | 2015-12-24 |
20150371857 | LOWER DOSE RATE ION IMPLANTATION USING A WIDER ION BEAM - In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece. | 2015-12-24 |
20150371858 | Method for Treating a Semiconductor Wafer - A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum. | 2015-12-24 |
20150371859 | METHOD FOR MANUFACTURING MOLYBDENUM OXIDE-CONTAINING THIN FILM - Disclosed is a method for manufacturing a molybdenum oxide-containing thin film, involving vaporizing a starting material for forming a thin film containing a compound represented by the following general formula (I) to give vapor containing a molybdenum amide compound, introducing the obtained vapor onto a substrate, and further introducing an oxidizing gas to cause decomposition and/or a chemical reaction to form a thin film on the substrate. In the formula, R | 2015-12-24 |
20150371860 | METHOD AND SYSTEM FOR THINNING WAFER THEREOF - A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided. | 2015-12-24 |
20150371861 | PROTECTIVE SILICON OXIDE PATTERNING - A method of patterning a substrate is described and include two possible layers which may be easily integrated into a photoresist patterning process flow and avoid an observed photoresist peeling problems. A conformal carbon layer or a conformal silicon-carbon-nitrogen layer may be formed between an underlying silicon oxide layer and an overlying photoresist layer. Either inserted layer may avoid remotely-excited fluorine etchants from diffusing through the photoresist and chemically degrading the silicon oxide. The conformal carbon layer may be removed at the same time as the photoresist and the conformal silicon-carbon-nitrogen layer may be removed at the same time as the silicon oxide, limiting process complexity. | 2015-12-24 |
20150371862 | METHOD OF FORMING PATTERN - A method of forming a pattern including following steps is provided. A wafer is provided, wherein the wafer includes a plurality of wafer interior dies and a plurality of wafer edge dies. A first pattern is formed on each of the wafer interior dies, and a second pattern is formed on each of the wafer edge dies. A method of forming the first patterns includes performing at least two exposure processes, and a method of forming the second patterns includes performing at least one of the at least two exposure processes, wherein a number of the exposure processes performed for forming the second patterns is less than a number of the exposure processes performed for forming the first patterns. | 2015-12-24 |
20150371863 | REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING - A method utilizing a chemical mechanical polishing process to remove a patterned material stack comprising at least one pattern transfer layer and a template layer during a rework process or during a post pattern transfer cleaning process is provided. The pattern in the patterned material stack is formed by pattern transfer of a directed self-assembly pattern generated from microphase separation of a self-assembly material. | 2015-12-24 |
20150371864 | LOW TEMPERATURE GAS-PHASE CARBON REMOVAL - A method of etching carbon films on patterned heterogeneous structures is described and includes a gas phase etch using remote plasma excitation. The remote plasma excites a fluorine-containing precursor and an oxygen-containing precursor, the plasma effluents created are flowed into a substrate processing region. The plasma effluents etch the carbon film more rapidly than silicon, silicon nitride, silicon carbide, silicon carbon nitride and silicon oxide. | 2015-12-24 |
20150371865 | HIGH SELECTIVITY GAS PHASE SILICON NITRIDE REMOVAL - A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while retaining silicon, such as polysilicon. | 2015-12-24 |
20150371866 | HIGHLY SELECTIVE DOPED OXIDE REMOVAL METHOD - A method of etching doped silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the doped silicon oxide. The plasmas effluents react with the patterned heterogeneous structures to selectively remove doped silicon oxide. | 2015-12-24 |
20150371867 | PROTECTIVE TRENCH LAYER AND GATE SPACER IN FINFET DEVICES - Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer. | 2015-12-24 |
20150371868 | METHOD FOR FABRICATING VERTICALLY STACKED NANOWIRES FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes in a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer includes a coating layer coated on an outer surface of a main body formed in the material layer, selectively removing a first portion of the coating layer from the material layers to expose the underlying main body of the material layers while maintaining a second portion of the coating layer remaining on the material layers, laterally etching the main body of the material layers exposed by removal of the coating layer, and selectively growing film layers on the exposed main body of the material layer. | 2015-12-24 |
20150371869 | NITROGEN-CONTAINING COMPOUNDS FOR ETCHING SEMICONDUCTOR STRUCTURES - A method for etching silicon-containing films is disclosed. The method includes the steps of introducing a vapor of a nitrogen containing etching compound into a reaction chamber containing a silicon-containing film on a substrate, wherein the nitrogen containing etching compound is an organofluorine compound containing at least one C≡N or C═N functional group; introducing an inert gas into the reaction chamber; and activating a plasma to produce an activated nitrogen containing etching compound capable of etching the silicon-containing film from the substrate. | 2015-12-24 |
20150371870 | DIE LEVEL CHEMICAL MECHANICAL POLISHING - A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die. | 2015-12-24 |
20150371871 | Method of Reducing an Impurity Concentration in a Semiconductor Body, Method of Manufacturing a Semiconductor Device and Semiconductor Device - A method of reducing an impurity concentration in a semiconductor body includes irradiating the semiconductor body with particles through a first side of the semiconductor body. The method further includes removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C. | 2015-12-24 |
20150371872 | Solution Based Etching of Titanium Carbide and Titanium Nitride Structures - Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C. The titanium carbide structures may be etched in a solution that also includes ammonium hydroxide, in addition to hydrogen peroxide, and maintained at about 25° C. | 2015-12-24 |
20150371873 | PACKAGING SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a packaging substrate includes: patterning a first photo-resisting layer having first openings on a copper foil layer to expose portions of the copper foil layer; patterning a removable second photo-resisting layer having second openings on the first photo-resisting layer to expose the first openings; filling copper into the first and second openings to form base portions and a first wiring layer; orderly forming a first dielectric layer and a second wiring layer on the first wiring layer; patterning a removable third photo-resisting layer comprising covering portions opposite to the base portions on the copper foil layer; and etching the copper foil layer to form protruding portions connected to and corresponding to the base portions to define a copper pillar bump, a size of the copper pillar bump gradually increasing from the protruding portions to the base portions. | 2015-12-24 |
20150371874 | SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES - The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front. | 2015-12-24 |
20150371875 | SUBSTRATE PROCESSING APPARATUS - Cleaning processing of each of the inside of a shower head and the inside of a processing space can be sufficiently or appropriately performed even when gas supply is performed via the shower head. A substrate processing apparatus includes a processing space for processing a substrate, a shower head buffer chamber disposed adjacent to the processing space with a dispersion plate having through-holes therebetween, an inert gas supply system configured to supply an inert gas into the shower head buffer chamber to form a gas curtain in the shower head buffer chamber, a first cleaning gas supply system configured to supply a cleaning gas into the processing space, and a control member configured to control the inert gas supply system and the first cleaning gas supply system to concurrently supply the cleaning gas into the processing space and the inert gas into the shower head buffer chamber. | 2015-12-24 |
20150371876 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus is provided including a processing chamber disposed within a vacuum vessel to form plasma therein, a processing stage disposed in the processing chamber to mount a wafer thereon, a first power supply for outputting an electric field supplied to form the plasma and forming an electric field of a first frequency supplied with repetition of a high output and a low output during processing of the wafer, a second power supply for supplying power of a second frequency to an electrode disposed within the processing stage, and a control device for causing a first value between load impedance at time of the high output of the electric field and load impedance at time of the low output of the electric field to match with impedance of the first power supply. | 2015-12-24 |
20150371877 | SUBSTRATE SUPPORT WITH SYMMETRICAL FEED STRUCTURE - Apparatus for processing a substrate is disclosed herein. In some embodiments, a substrate support may include a substrate support having a support surface for supporting a substrate the substrate support having a central axis; a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface; an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support; an outer conductor disposed about the inner conductor; and an outer dielectric layer disposed between the inner and outer conductors, the outer dielectric layer electrically isolating the outer conductor from the inner conductor. The outer conductor may be coupled to electrical ground. | 2015-12-24 |
20150371878 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 2015-12-24 |
20150371879 | ROLL TO ROLL WAFER BACKSIDE PARTICLE AND CONTAMINATION REMOVAL - Particulate cleaning assemblies and methods for cleaning are disclosed. In one example, a device for removing particles from a backside surface of a substrate is described. The device includes a chamber body with a substrate chucking device, a particulate cleaning article positioned over the substrate supporting surface, an optical sensing device positioned under the particulate cleaning article and a substrate positioning device separates the particulate cleaning article and a substrate. In another example, a method for removing particles from a substrate is disclosed. The method includes positioning a substrate with a processing surface and a supporting surface in a process chamber. At least a portion of the substrate can be chucked to a substrate chucking device, the substrate chucking device having a substrate supporting surface with a particulate cleaning article positioned thereon. The substrate is then separated from the particulate cleaning article leaving particles behind. | 2015-12-24 |
20150371880 | SEMICONDUCTOR DIE ENCAPSULATION OR CARRIER-MOUNTING METHOD, AND CORRESPONDING SEMICONDUCTOR DIE ENCAPSULATION OR CARRIER-MOUNTING APPARATUS - A semiconductor die encapsulation or carrier-mounting method includes the steps of providing a first tool part for holding multiple semiconductor dies and providing the semiconductor dies on the first tool part; providing a second tool part, one of the first and second tool parts including displaceable insert members to allow applying a pressure by each displaceable insert member on a surface area of a semiconductor die; and bringing together the first and second tool parts such as to define a space between the first and second tool parts, the semiconductor products being arranged in the space. The displaceable insert members apply a pressure onto the surface area of the semiconductor dies. The pressure applied by the displaceable insert members is monitored and regulated to a predetermined pressure. Subsequently, the first and second tool parts are separated and the processed semiconductor dies are removed. | 2015-12-24 |
20150371881 | TEMPERATURE MEASUREMENT IN MULTI-ZONE HEATER - Embodiments of the present disclosure generally provide apparatus and methods for monitoring one or more process parameters, such as temperature of substrate support, at various locations. One embodiment of the present disclosure provides a sensor column for measuring one or more parameters in a processing chamber. The sensor column includes a tip for contacting a chamber component being measured, a protective tube having an inner volume extending from a first end and second end, wherein the tip is attached to the first end of the protective tube and seals the protective tube at the first end, and a sensor disposed near the tip. The inner volume of the protective tube houses connectors of the sensor, and the tip is positioned in the processing chamber through an opening of the processing chamber during operation. | 2015-12-24 |
20150371882 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space. | 2015-12-24 |
20150371883 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - In the present invention, a substrate is placed at a predetermined position on a substrate support even though the substrate is deviated on a substrate transfer unit. | 2015-12-24 |
20150371884 | Concentric Stiffener Providing Warpage Control To An Electronic Package - Techniques or processes for reducing and/or mitigation warpage are disclosed. A method for fabricating a package includes providing a stiffener member for mounting on a substrate of the package, determining an out-of-plane displacement for the substrate at a temperature of interest, the out-of-plane displacement corresponding to warpage, and if the warpage exceeds a predetermined value, modifying at least one attribute associated with the stiffener member. | 2015-12-24 |
20150371885 | TRAY AND WAFER HOLDING APPARATUS - A tray includes a support base having both a first face on which a clamp object is placed and a second face opposite the first face, an upper electrode embedded in the support base and situated toward the first face, a lower electrode embedded in the support base and situated further toward the second face than the upper electrode is, and one or more interconnect lines configured to provide an electrical connection between the upper electrode and the lower electrode. | 2015-12-24 |
20150371886 | EDGE GRIP SUBSTRATE HANDLER - A mechanism for handling substrates such as semiconductor wafers is disclosed. The mechanism supports the substrate in a tilted orientation to ensure that undesirable contact between a bowed substrate and the mechanism does not occur. The structure that supports the substrate in a tilted orientation may be fixed or adjustable. A sensor may be provided to measure and/or monitor a distance between a substrate and the mechanism. Alternatively, a sensor for determining contact between the substrate and the mechanism may be provided. | 2015-12-24 |
20150371887 | UNIVERSAL CLAMPING FIXTURE TO MAINTAIN LAMINATE FLATNESS DURING CHIP JOIN - A clamping apparatus and method for maintaining a workpiece flatness during processing includes a base having a planar surface for receiving a first workpiece. Two sets of opposing clamping mechanisms are mounted to the base and include a clamp head at a distal end of a rod extending from a housing in removable overlapping relation to the first workpiece. Each set of the clamp heads are in opposing spaced relationship to each other defining a second workpiece area, and the clamp heads are configured to mate with a top surface of the first workpiece. A biasing member is coupled to each of the housings and apply a downward vertical force to the housings, rods, and the clamp heads for applying a downward vertical pressure to the first workpiece. The first workpiece is thereby discouraged from thermally expanding in a vertical direction and is thermally expandable horizontally along the planar surface. | 2015-12-24 |
20150371888 | UNIVERSAL CLAMPING FIXTURE TO MAINTAIN LAMINATE FLATNESS DURING CHIP JOIN - A clamping apparatus and method for maintaining a workpiece flatness during processing includes a base having a planar surface for receiving a first workpiece. Two sets of opposing clamping mechanisms are mounted to the base and include a clamp head at a distal end of a rod extending from a housing in removable overlapping relation to the first workpiece. Each set of the clamp heads are in opposing spaced relationship to each other defining a second workpiece area, and the clamp heads are configured to mate with a top surface of the first workpiece. A biasing member is coupled to each of the housings and apply a downward vertical force to the housings, rods, and the clamp heads for applying a downward vertical pressure to the first workpiece. The first workpiece is thereby discouraged from thermally expanding in a vertical direction and is thermally expandable horizontally along the planar surface. | 2015-12-24 |
20150371889 | METHODS FOR SHALLOW TRENCH ISOLATION FORMATION IN A SILICON GERMANIUM LAYER - Methods for processing a substrate include (a) providing a substrate comprising a silicon germanium layer and a patterned mask layer atop the silicon germanium layer to define a feature in the silicon germanium layer; (b) exposing the substrate to a first plasma formed from a first process gas to etch a feature into the silicon germanium layer; (c) subsequently exposing the substrate to a second plasma formed from a second process gas to form an oxide layer on a sidewall and a bottom of the feature; (d) exposing the substrate to a third plasma formed from a third process gas to etch the oxide layer from the bottom of the feature; and (e) repeating (b)-(d) to form the feature in the first layer to a desired depth, wherein the first process gas, the second process gas and the third process gas are not the same. | 2015-12-24 |
20150371890 | METHOD FOR FABRICATING AND MANUFACTURING MICRO- and NANO-FABRICATED DEVICES AND SYSTEMS SECURELY - A method is disclosed for manufacturing integrated circuits, microelectronics, micro-electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS), photonic, and any micro- and nano-fabricated devices and systems designs that allow these designs to be kept secure. The manufacturing of the devices in the substrates is performed in a traditional manner at a foundry that can be located anywhere in the world., The manufacturing at this foundry is stopped just before the fabrication of the first layer of electrical interconnects. At this stage, the semiconductor substrates with the devices, minus electrical interconnects, are sent back to the design organization (or their designated trusted foundry) to perform the fabrication of the electrical interconnects to complete the entire manufacturing process. Since the electrical interconnection wiring diagram is the critical component of the design, this de-coupling of the manufacturing allows the designs of the devices and systems to be kept secure and confidential. | 2015-12-24 |
20150371891 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion. | 2015-12-24 |
20150371892 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH A UNIQUE GATE CONFIGURATION, AND THE RESULTING FINFET DEVICE - One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure. | 2015-12-24 |
20150371893 | BURIED SIGNAL TRANSMISSION LINE - A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit. | 2015-12-24 |
20150371894 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM AND RECORDING MEDIUM - A substrate processing method can remove a part of a processing target film formed on a surface of a substrate W under a normal pressure atmosphere while suppressing an influence upon the substrate. A source material of the processing target film, which is decomposed by irradiating an ultraviolet ray thereto under an oxygen-containing atmosphere, is coated on the substrate W, and the processing target film is formed by heating the source material coated on the substrate W. Then, the substrate W having thereon the processing target film is placed within a processing chamber under the oxygen-containing atmosphere where a gas flow velocity is equal to or smaller than 10 cm/sec, and the part of the processing target film is removed by irradiating the ultraviolet ray to the substrate W. | 2015-12-24 |
20150371895 | METHOD FOR MANUFACTURING SMEICONDUCTOR DEVICE - In one embodiment, a first insulating film is formed with a recess portion left therein in a contact hole, and the contact hole is surrounded by a first line pattern and a second line pattern, the first line pattern and the second line pattern having different heights. The recess portion is filled so as to form a first mask film, and the first insulating film except for the recess portion is etched back so as to be removed, thereby forming a second contact hole. After that, a conductive material is implanted in the second contact hole, and the top surface of the first line pattern having a low height is exposed, thereby forming a contact plug. | 2015-12-24 |
20150371896 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 2015-12-24 |
20150371897 | Trench Formation using Horn Shaped Spacer - A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer. | 2015-12-24 |
20150371898 | INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer. | 2015-12-24 |
20150371899 | MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES - Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure. | 2015-12-24 |
20150371900 | Nanoscale Interconnects Fabricated by Electrical Field Directed Assembly of Nanoelements - The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes. | 2015-12-24 |
20150371901 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a step of preparing a semiconductor substrate including a semiconductor layer and an epitaxial layer formed on the semiconductor layer, a first division step of obtaining first individual pieces by dividing the semiconductor substrate so as to pass through a central region including a central point of the semiconductor substrate and having a diameter of 10 mm, and a second division step of obtaining second individual pieces by subdividing the first individual piece. | 2015-12-24 |
20150371902 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cubing portion along the trench and dividing the semiconductor substrate along the cutting portion. | 2015-12-24 |
20150371903 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that includes a first electrode and a second electrode; providing a first mask on the dielectric layer; providing a second mask, which overlaps the first mask and has a designated structure, wherein a portion of the first mask is positioned between a first portion and a second portion of the designated structure in a layout view of a process structure that includes the first mask and the second mask; and performing a removal process through the first portion of the designated structure and through the second portion of the designated structure to form a first contact hole and a second contact hole in a remaining portion of the dielectric layer, wherein the two contact holes expose the two electrodes, respectively. | 2015-12-24 |
20150371904 | PATTERNING PROCESS FOR FIN IMPLANTATION - After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation. | 2015-12-24 |
20150371905 | SOI WITH GOLD-DOPED HANDLE WAFER - A method for manufacturing a semiconductor die includes providing an SOI semiconductor wafer including a substrate, an insulating layer over the substrate, and a device layer over the insulating layer. A surface of the SOI semiconductor wafer opposite the substrate is mounted to a temporary carrier mount, and the substrate is removed, leaving an exposed surface of the insulating layer. A high-resistivity gold-doped silicon substrate is then provided on the exposed surface of the insulating layer. By providing the high-resistivity gold-doped silicon substrate, an exceptionally high-resistivity substrate can be achieved, thereby minimizing field-dependent electrical interaction between the substrate and one or more semiconductor devices thereon. Accordingly, harmonic distortion in the semiconductor devices caused by the substrate will be reduced, thereby increasing the performance of the device. | 2015-12-24 |
20150371906 | EVALUATION METHOD FOR OXIDE SEMICONDUCTOR THIN FILM, QUALITY CONTROL METHOD FOR OXIDE SEMICONDUCTOR THIN FILM, AND EVALUATION ELEMENT AND EVALUATION DEVICE USED IN THE EVALUATION METHOD - Provided are: a method for measuring and evaluating (predicting or estimating) stress stability of an oxide semiconductor thin film in a contactless manner; and a quality control method for an oxide semiconductor. This evaluation method comprises a first step and a second step. The first step includes: subjecting an oxide semiconductor thin film to irradiation with both excitation light and microwave radiation; stopping the irradiation with the excitation light after the maximum intensity of reflected wave of the microwave radiation, which varies with the irradiation of the excitation light, from the thin film has been observed; and thereafter measuring a variation in the reflectance with which the microwave radiation is reflected by the thin film. The second step includes: calculating, from the variation in the reflectance, a parameter that corresponds to slow attenuation observed about 1 μs after the stopping; and thus evaluating the stress stability of the oxide semiconductor. | 2015-12-24 |
20150371907 | SUBSTRATE FEATURES FOR INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH - A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines. | 2015-12-24 |
20150371908 | METHODS FOR REDUCING SEMICONDUCTOR SUBSTRATE STRAIN VARIATION - Embodiments of the disclosure provide methods and system for correcting lithographic film stress/strain variations on a semiconductor substrate using laser energy treatment process. In one embodiment, a method for correcting film stress/strain variations on a substrate includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining dose of laser energy in a computing system to correct film stress/strain variations or substrate distortion based on the overlay error map, and providing a laser energy treatment recipe to a laser energy apparatus based on the dose of laser energy determined to correct substrate distortion or film stress/strain variations. | 2015-12-24 |
20150371909 | METHODS FOR POST-EPITAXIAL WARP PREDICTION AND CONTROL - In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a processor, a measured resistivity of a first wafer of the plurality of wafers, receiving, by the processor, a measured shape of the first wafer after at least one of a grinding process and an etching process, and calculating, using the processor, a change in wafer shape during the epitaxial layer deposition process. The method further includes superposing, using the processor, the calculated shape change onto the measured shape of the first wafer to determine a post-epitaxial wafer shape and calculating, using the processor, a post-epitaxial warp value based on the determined post-epitaxial wafer shape. | 2015-12-24 |
20150371910 | Automated Inline Inspection of Wafer Edge Strain Profiles Using Rapid Photoreflectance Spectroscopy - Photoreflectance spectroscopy is used to measure strain at or near the edge of a wafer in a production process. The strain measurement is used to anticipate defects and make prospective corrections in later stages of the production process. Strain measurements are used to associate various production steps with defects to enhance later production processes. | 2015-12-24 |
20150371911 | Systems and methods for reducing beam instability in laser annealing - Systems and methods for reducing beam instability in laser annealing are disclosed. The method includes: directing a conditioned laser beam through an opening in an aperture using a beam-redirecting element; forming a line image on the surface of the semiconductor wafer by imaging the aperture onto the surface, thereby locally heating the surface to form an annealing temperature distribution; detecting a thermal emission from the locally heated wafer surface; determining the annealing temperature distribution from the detected thermal emission; determining from the annealing temperature distribution a line-image intensity profile that includes a time-varying amount of slope; and adjusting the beam-redirecting element to redirect the laser beam to reduce or eliminate the time-varying amount of slope in the line-image intensity profile. | 2015-12-24 |
20150371912 | METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL PLANARIZATION ENDPOINT DETECTION USING AN ALTERNATING CURRENT REFERENCE SIGNAL - Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process. | 2015-12-24 |
20150371913 | INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH - In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time. | 2015-12-24 |
20150371914 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate processing apparatus for executing a predetermined process on a substrate loaded into a process chamber by running a recipe containing a plurality of steps is provided. The recipe includes a processing step of processing the substrate, and a leak check step executed before the processing step to check whether a leak occurs inside the process chamber, and the substrate processing apparatus includes a main control unit configured to execute the processing step while keeping an error that occurs in the leak check step. | 2015-12-24 |
20150371915 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained. | 2015-12-24 |
20150371916 | PRE-APPLIED UNDERFILL - Underfill structures useful as pre-applied underfill materials comprise a polymer layer having a first filled polymer region having a first viscosity and a second filled polymer region having a second viscosity, wherein the first viscosity is less than the second viscosity. Electronic assemblies comprising a chip or die and a substrate are formed using such multi-layer structured pre-applied underfill. | 2015-12-24 |
20150371917 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 2015-12-24 |
20150371918 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 2015-12-24 |
20150371919 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 2015-12-24 |
20150371920 | VEHICULAR POWER CONVERSION DEVICE - Semiconductor elements work for power conversion and generate heat. A plurality of heat-radiating fins are juxtaposed at intervals to form a passage in a first axis direction, receive the heat from the semiconductor elements, and expel the heat into the air flowing through the passage. A first protective fin has an end face having an equal length in the juxtaposition direction to and mutually facing the end face on the first axis positive side of at least some of the heat-radiating fins, and extends in the first axis positive direction from that end face. A second protective fin has an end face having an equal length in the juxtaposition direction to and mutually facing the end face on the first axis negative side of at least some of the heat-radiating fins, and extends in the first axis negative direction from that end face. | 2015-12-24 |
20150371921 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present invention includes: a first substrate ( | 2015-12-24 |
20150371922 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 2015-12-24 |
20150371923 | HEAT CONDUCTIVE SHEET AND STRUCTURE - Provided is a heat conductive sheet obtained by including a heat conductive filler in a cured organic resin, in which the heat conductive filler is made of multiple particles obtained by coating surfaces of plastic particles with a heat conductive material, and a coefficient of variation (CV) value of particle diameters of the particles, which is computed using Equation (1) described below, is equal to or less than 10%. | 2015-12-24 |
20150371924 | HEAT RELEASING SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a heat releasing semiconductor chip package includes attaching a first surface of a semiconductor chip onto an insulating film, injecting a coating liquid onto a second surface of the semiconductor chip to form a liquefied coating layer and curing the liquefied coating layer to form a heat releasing layer. The coating liquid includes a liquefied molding compound for heat releasing and fine alumina particles. Therefore, the heat releasing semiconductor chip package and method for manufacturing the semiconductor chip package form a heat releasing layer in direct contact with the semiconductor chip to maximize a heat releasing effect. | 2015-12-24 |
20150371925 | THROUGH ARRAY ROUTING FOR NON-VOLATILE MEMORY - Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described. | 2015-12-24 |
20150371926 | INTEGRATED CIRCUIT HAVING MAIN ROUTE AND DETOUR ROUTE FOR SIGNAL TRANSMISSION AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAME - The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction. | 2015-12-24 |
20150371927 | COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip. | 2015-12-24 |
20150371928 | Connecting Through Vias to Devices - Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor. | 2015-12-24 |
20150371929 | IMPLANT DEVICE AND METHOD OF MAKING THE SAME - The invention provides chip packaging and processes for the assembly of retinal prosthesis devices. Advantageously, photo-patternable adhesive or epoxy such as photoresist is used as glue to attach a chip to the targeted thin-film (e.g., parylene) substrate so that the chip is used as an attachment to prevent delamination. | 2015-12-24 |
20150371930 | Integrated Circuit Packaging Method Using Pre-Applied Attachment Medium - A method of making an IC package having a die and a substrate that are to be attached at an attachment station including providing the die and substrate and, at a location remote from the attachment station, coating at least one of the die and a die attachment portion of the substrate with attachment medium. | 2015-12-24 |
20150371931 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes a frame including a first step portion provided in a ring shape in an inner circumference of one main surface of the frame, a second step portion provided in a ring shape in an inner circumference of another main surface of the frame, and an inner wall provided between the first step portion and the second step portion; a terminal leading from the first step portion to outside; a circuit board fitted to the second step portion; and an adhesive resin bonding the second step portion and the circuit board, and contacting the inner wall and the terminal. | 2015-12-24 |
20150371932 | THIN FILM RDL FOR NANOCHIP PACKAGE - A high density film adapted for nanochip package comprises three redistribution layers. A bottom redistribution circuit has a plurality of first bottom pads adapted for a nanochip to mount; and has a plurality of first top pads. The density of the first bottom pads is higher than the density of the first top pads. A middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads. The density of the second bottom pads is higher than the density of the second top pads. A top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads; and has a plurality of third top pads. The density of the third bottom pads is higher than the density of the third top pads. | 2015-12-24 |
20150371933 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 2015-12-24 |
20150371934 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture. | 2015-12-24 |