51st week of 2021 patent applcation highlights part 64 |
Patent application number | Title | Published |
20210399118 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film. | 2021-12-23 |
20210399119 | TRANSITION METAL-III-NITRIDE ALLOYS FOR ROBUST HIGH PERFORMANCE HEMTS - Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact. | 2021-12-23 |
20210399120 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer. | 2021-12-23 |
20210399121 | NOVEL APPROACH TO CONTROLLING LINEARITY IN N-POLAR GAN MISHEMTS - Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance. | 2021-12-23 |
20210399122 | Semiconductor Structure and Method for Manufacturing the Same - The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches. | 2021-12-23 |
20210399123 | SEMICONDUCTOR DEVICE HAVING IMPROVED GATE LEAKAGE CURRENT - The present invention relates to a semiconductor device having an improved gate leakage current. The semiconductor device includes: a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, thereby improving the gate leakage current phenomenon. | 2021-12-23 |
20210399124 | SEMICONDUCTOR DEVICE WITH ASYMMETRIC GATE STRUCTURE - The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics. | 2021-12-23 |
20210399125 | GaN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF - A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N | 2021-12-23 |
20210399126 | METHODS OF PROTECTING SEMICONDUCTOR MATERIALS IN THE ACTIVE REGION OF A TRANSISTOR DEVICE AND THE RESULTING TRANSISTOR DEVICE - An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material. | 2021-12-23 |
20210399127 | Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide - A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion. | 2021-12-23 |
20210399128 | POWER DEVICES WITH A HYBRID GATE STRUCTURE - A vertical field effect device having a body, gate dielectric, and a gate electrode, which is in a trench that extends into the body from the top surface of the body and is located between first and second source regions. The first and second regions vertically overlap the gate electrode. The first and second channel regions laterally overlap a bottom of the gate electrode, such that each channel formed in the first and second source regions have a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode. In another embodiment, the first and second channel regions also vertically overlap the gate electrode such that each channel formed in the first and second source regions also have a vertical segment where the first and second channel regions vertically overlap the gate electrode. | 2021-12-23 |
20210399129 | LDMOS TRANSISTOR AND MANUFACTURE THEREOF - an uppermost | 2021-12-23 |
20210399130 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film. | 2021-12-23 |
20210399131 | VTFET WITH CELL HEIGHT CONSTRAINTS - Semiconductor devices include a channel fin having a top surface. A top semiconductor structure, in contact with the entire top surface of the channel fin and having a top portion and a bottom portion, with the top portion of the top semiconductor structure being narrower than the bottom portion. A restraint structure being formed over the bottom portion of the semiconductor structure. | 2021-12-23 |
20210399132 | BURIED CHANNEL METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) AND FORMING METHOD THEREOF - A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-”shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET. | 2021-12-23 |
20210399133 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a dielectric structure, a first source/drain electrode, a second source/drain electrode, an oxide semiconductor layer, a gate dielectric layer, and a first gate electrode. The first source/drain electrode is disposed in the dielectric structure. The oxide semiconductor layer is disposed on the first source/drain electrode in a vertical direction. The second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction. The gate dielectric layer is disposed on the dielectric structure and surrounds the oxide semiconductor layer in a horizontal direction. The gate dielectric layer includes a first portion and a second portion. The first portion is elongated in the horizontal direction. The second portion is disposed on the first portion and elongated in the vertical direction. The first gate electrode is disposed on the first portion of the gate dielectric layer. | 2021-12-23 |
20210399134 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator over the first insulator and the second insulator; a second oxide positioned over the first oxide and between the first conductor and the second conductor; a fourth insulator over the second oxide; a third conductor over the fourth insulator; a fifth insulator in contact with a top surface of the third insulator, a top surface of the second oxide, a top surface of the fourth insulator, and a top surface of the third conductor; a fourth conductor embedded in an opening formed in the first insulator, the third insulator, and the fifth insulator and in contact with the first conductor; and a fifth conductor embedded in an opening formed in the second insulator, the third insulator, and the fifth insulator and in contact with the second conductor. The third insulator includes, in the vicinity of an interface with the fourth conductor and in the vicinity of an interface with the fifth conductor, a region having a higher nitrogen concentration than a different region of the third insulator. | 2021-12-23 |
20210399135 | FERROELECTRIC BASED TRANSISTORS - The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor. | 2021-12-23 |
20210399136 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer. | 2021-12-23 |
20210399137 | INTERFACIAL DUAL PASSIVATION LAYER FOR A FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME - A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor. | 2021-12-23 |
20210399138 | Post CMOS Compatible Ferroelectric Field Effect Transistor With AIScN Dielectric And 2D Material Channel - Provided are ferroelectric field effect transistor (FeFET) based memory devices. These devices include aluminum scandium nitride (AlScN) as a ferroelectric dielectric and 2D chalcogenide semiconductors as a semiconductor channel in the transistor. The disclosed materials, devices and fabrication processes involved are compatible with back end of the line (BEOL) processing of a silicon based microchip and also compatible with silicon microprocessor fabrication. | 2021-12-23 |
20210399139 | TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME - A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions. | 2021-12-23 |
20210399140 | SEMICONDUCTOR DEVICE - A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer; the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the semiconductor layer; an end portion of the first insulating layer is located inward from an end portion of the semiconductor layer; an end portion of the metal oxide layer is located inward from the end portion of the first insulating layer; and an end portion of the conductive layer is located inward from the end portion of the metal oxide layer. The second insulating layer is preferably provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer. It is preferable that the semiconductor layer include a first region, a pair of second regions, and a pair of third regions; the first region overlap with the first insulating layer and the metal oxide layer; the second regions between which the first region is sandwiched overlap with the first insulating layer and not overlap with the metal oxide layer; the third regions between which the first region and the pair of second regions are sandwiched not overlap with the first insulating layer; and the third regions be in contact with the second insulating layer. | 2021-12-23 |
20210399141 | DUAL-LAYER CHANNEL TRANSISTOR AND METHODS OF FORMING SAME - A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance. | 2021-12-23 |
20210399142 | Thin Film Transistor Array Substrate and Display Device - Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced. | 2021-12-23 |
20210399143 | PIN DIODES WITH MULTI-THICKNESS INTRINSIC REGIONS - A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths. | 2021-12-23 |
20210399144 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region. | 2021-12-23 |
20210399145 | III-Nitride Diode With A Modified Access Region - This disclosure describes the structure and technology to modify the free electron density between the anode electrode and cathode electrode of III-nitride semiconductor diodes. Electron density reduction regions (EDR regions) are disposed between the anode and cathode electrodes of the diode structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors. | 2021-12-23 |
20210399146 | TRANSITION METAL CHALCOGENIDE VAN DER WAALS FILMS, METHODS OF MAKING SAME, AND APPARATUSES AND DEVICES COMPRISING SAME - Provided are van der Waals (VDW) films comprising one or more transition metal chalcogenide (TMD) films. Also provided are methods of making VDW films. The methods are based on transfer of monolayer TMD films under vacuum, for example, using a handle layer. Also provided are apparatuses and devices comprising one or more VDW film. | 2021-12-23 |
20210399147 | HIGH PERFORMANCE LONG-LIFETIME CHARGE-SEPARATION PHOTODETECTORS - High-performance long-lifetime charge-separation photodetectors are provided. A new device design is described based on novel band structure engineering of semiconductor materials for photodetectors, such as photosensors, solar cells, and thermophotovoltaic devices. In an exemplary aspect, photodetectors described herein include a charge-separated photo absorber region. This comprises a semiconductor with a band structure that has an indirect fundamental bandgap, with a direct bandgap (┌-┌ transition) only slightly above the indirect fundamental bandgap (L- or X-┌ transitions) (e.g., approximately equal to or larger than an energy of a product of the Boltzmann constant (k | 2021-12-23 |
20210399148 | OPTICAL DEVICE, PHOTOELECTRIC CONVERTER, AND FUEL GENERATOR - An optical device includes a nanostructure body which induces surface plasmon resonance when irradiated with light, an alloy layer which is in contact with the nanostructure body and which has a lower work function than the nanostructure body, and an n-type semiconductor which is in Schottky contact with the alloy layer. The nanostructure body is composed of one selected from the group consisting of elemental metals, alloys, metal nitrides, and conductive oxides. The alloy layer is composed of at least two metals. | 2021-12-23 |
20210399149 | Dark Reference Device for Improved Dark Current Matching - A dark reference device comprises:
| 2021-12-23 |
20210399150 | VANADIUM-CONTAINING ELECTRODES AND INTERCONNECTS TO TRANSPARENT CONDUCTORS - Intermediate temperature metallization pastes containing vanadium are disclosed. The metallization pastes can be used to fabricate electrodes interconnected to a transparent conductor. | 2021-12-23 |
20210399151 | POSITIVE ELECTRODE OF CRYSTALLINE SILICON SOLAR CELL HAVING GATE RUPTURE PREVENTION FUNCTION - Disclosed is a positive electrode of a crystalline silicon solar cell with a break-proof grid function, comprising a positive electrode busbar ( | 2021-12-23 |
20210399152 | GLASS BRICK WITH LUMINESCENT SOLAR CONCENTRATOR FOR PRODUCTION OF ELECTRICAL ENERGY - A glass brick having a luminescent solar concentrator inserted inside it, between the preformed glass portions which constitute the body of the glass brick is provided. | 2021-12-23 |
20210399153 | OPTICALLY-TRANSPARENT SEMICONDUCTOR BUFFER LAYERS AND STRUCTURES EMPLOYING THE SAME - Semiconductor structures including optically-transparent metamorphic buffer regions, devices employing such structures, and methods of fabrication. The optically-transparent metamorphic buffer is grown to provide a lattice constant transition between a smaller lattice constant and a larger lattice constant (or vice-versa), allowing materials with two different lattice constants to be monolithically integrated. Such buffer layer may include at least two elements from group V of the periodic table. The optically-transparent metamorphic buffer region may include digital-alloy superlattice structure (s) to confine material defects to the metamorphic buffer layer, and improve electrical properties of the metamorphic buffer layer, thereby improving the electronic properties of electronic devices such as optoelectronic devices and photovoltaic cells. Photonic devices such as solar cells and optical detectors containing such semiconductor structures. | 2021-12-23 |
20210399154 | METHOD FOR MANUFACTURING A UV-RADIATION DETECTOR DEVICE BASED ON SIC, AND UV-RADIATION DETECTOR DEVICE BASED ON SIC - A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected. | 2021-12-23 |
20210399155 | ASYMMETRIC LATERAL AVALANCHE PHOTODETECTOR - Avalanche photodetector devices are disclosed in which spatial asymmetry is employed to preferentially enhance avalanche multiplication of electrons. In some example embodiments, an avalanche photodetector device includes p-doped and n-doped regions and a central waveguide region, where the p-doped region is laterally offset from the central waveguide by a first lateral offset region, and where the n-doped region is laterally offset from the central waveguide by a second lateral offset region. The first and second lateral offset regions are asymmetrically defined such that impact ionization and avalanche multiplication of electrons in the second laterally offset region is enhanced relative to that of holes in the first laterally offset region. In some example implementations, the asymmetry may be provided by a difference in relative heights and/or lateral spatial extends (widths) of the lateral offset regions, such that the electric field, or a spatial extent associated therewith, is enhanced for electrons. | 2021-12-23 |
20210399156 | HIGH SENSITIVITY SEMICONDUCTOR DEVICE FOR DETECTING FLUID CHEMICAL SPECIES AND RELATED MANUFACTURING METHOD - A device for detecting a chemical species, including a Geiger-mode avalanche diode, which includes a body of semiconductor material delimited by a front surface. The semiconductor body includes: a cathode region having a first type of conductivity, which forms the front surface; and an anode region having a second type of conductivity, which extends in the cathode region starting from the front surface. The detection device further includes: a sensitive structure arranged on the anode region and including at least one sensitive region, which has an electrical permittivity that depends upon the concentration of the chemical species; and a resistive region, arranged on the sensitive structure and electrically coupled to the anode region. | 2021-12-23 |
20210399157 | EMBEDDED WAFER LEVEL OPTICAL SENSOR PACKAGING - The present disclosure is directed to a sensor die with an embedded light sensor and an embedded light emitter as well as methods of manufacturing the same. The light emitter in the senor die is surrounded by a resin. The sensor die is incorporated into semiconductor device packages as well as methods of manufacturing the same. The semiconductor device packages include a first optically transmissive structure on the light sensor of the sensor die and a second optically transmissive structure on the light emitter of the sensor die. The first optically transmissive structure and the second optically transmissive structure cover and protect the light sensor and the light emitter, respectively. A molding compound is on a surface of a sensor die and covers sidewalls of the first and second optically transmissive structures on the sensor die. | 2021-12-23 |
20210399158 | ENCAPSULATION FOR SOLAR CELL AND METHOD FOR ENCAPSULATING SOLAR CELL - The subject disclosure provides a simple, fast, and high-yield method for encapsulating solar cells. This method can produce an encapsulation of solar cell(s) that is flat, bubble-free, lightweight, and flexible. In addition, it can also reduce equipment and material costs. | 2021-12-23 |
20210399159 | Photovoltaic Devices and Method of Making - Embodiments of a photovoltaic device are provided herein. The photovoltaic device can include a layer stack and an absorber layer disposed on the layer stack. The absorber layer can include a first region and a second region. Each of the first region of the absorber layer and the second region of the absorber layer can include a compound comprising cadmium, selenium, and tellurium. An atomic concentration of selenium can vary across the absorber layer. The first region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. The second region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. A ratio of an average atomic concentration of selenium in the first region of the absorber layer to an average atomic concentration of selenium in the second region of the absorber layer can be greater than 10. | 2021-12-23 |
20210399160 | SELF-ASSEMBLY APPARATUS AND METHOD FOR SEMICONDUCTOR LIGHT EMITTING DEVICE - Discussed is a self-assembly apparatus of a semiconductor light emitting device, the self-assembly apparatus including a fluid chamber configured to accommodate a plurality of semiconductor light emitting devices, each semiconductor light emitting device having a magnetic body; a magnet disposed to be spaced apart from the fluid chamber and configured to apply a magnetic force to the plurality of semiconductor light emitting devices; and a position controller connected to the magnet, and configured to control a position of the magnet; and a power supply configured to induce formation of an electric field on a substrate placed at an assembly position so that the plurality of semiconductor light emitting devices are seated at preset positions on the substrate while being moved due to a positional change of the magnet, wherein the position controller transfers the magnet in one direction while rotating the magnet about a rotation axis for the magnet. | 2021-12-23 |
20210399161 | MASS TRANSFER APPARATUS AND MASS TRANSFER METHOD - The application relates to a mass transfer apparatus and a mass transfer method. The apparatus includes: a laser device configured to emit a laser beam; a first lens configured to shape the laser beam into a circular light spot through the first lens; and a second lens configured to guide the circular light spot to a first substrate on which to-be-transferred micro light-emitting diode chips are mounted. A transmission assembly is fixed on the second lens and configured to move the second lens to adjust a distance between the first lens and the second lens so as to adjust a diameter of the circular light spot. | 2021-12-23 |
20210399162 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride semiconductor light-emitting element includes a light-emitting layer comprising a well layer comprising AlGaN and emitting ultraviolet light; an electron blocking layer being located on the light-emitting layer and comprising AlGaN with a first Al composition ratio higher than an Al composition ratio of the well layer; and a p-type cladding layer being located on the electron blocking layer, comprising AlGaN with a second Al composition ratio higher than the Al composition ratio of the well layer and lower than the first Al composition ratio, and being doped with a predetermined concentration of a p-type dopant. An interface between the electron blocking layer and the p-type cladding layer is doped with not less than a predetermined amount of an n-type dopant. | 2021-12-23 |
20210399163 | LIFT-OFF METHOD AND LASER PROCESSING APPARATUS - A lift-off method includes a relocation substrate joining step of joining a relocation substrate to a surface of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby forming a composite substrate, a buffer layer breaking step of applying a pulsed laser beam having a wavelength transmittable through an epitaxy substrate and absorbable by a buffer layer to the buffer layer from a reverse side of the epitaxy substrate of the optical device wafer of the composite substrate, thereby breaking the buffer layer, and an optical device layer relocating step of peeling off the epitaxy substrate from the optical device layer, thereby relocating the optical device layer to the relocation substrate. In the buffer layer breaking step, irradiating conditions of the pulsed la-ser beam are changed for respective ring-shaped areas of the buffer layer, and the pulsed laser beam is applied to the optical device wafer under the changed irradiating conditions. | 2021-12-23 |
20210399164 | METHOD OF MANUFACTURING A RED LIGHT-EMITTING CHIP CARRYING STRUCTURE - A method of manufacturing a red light-emitting chip carrying structure is provided. The method includes providing a red LED wafer including a wafer base, a plurality of porous connection layers, and a plurality of red LED chips; placing the red LED chips on a chip carrying substrate; projecting a laser light beam onto the porous connection layers or the chip carrying substrate; and then removing the wafer base and a removal part of each of the porous connection layers so as to leave a residual part of each of the porous connection layers on a corresponding one of the red LED chips. Therefore, the red LED chips can be transferred from the red LED wafer to a chip adhesive layer of the chip carrying substrate or a plurality of conductive soldering materials on the chip carrying substrate. | 2021-12-23 |
20210399165 | System and Method for the Repair of Serially Connected Display Elements - A system and method are provided for repairing an emissive element display. If a defective emissive element is detected in a subpixel, a subpixel repair interface isolates the defective emissive element. The repair interface may be a parallel repair interface with n number of selectively fusible electrically conductive repair nodes, connected in parallel to a control line of the matrix. Alternatively, the repair interface may be a series repair interface with m number of repair nodes, selectively connectable to bypass adjacent (defective) series-connected emissive elements. If the subpixel emissive elements are connected in parallel, and a defective low impedance emissive element is detected, a parallel repair interface fuses open a connection between the defective emissive element and a matrix control line. If the subpixels include series-connected emissive elements, and a high impedance emissive element is detected, a series repair interface forms a connection bypassing the defective emissive element. | 2021-12-23 |
20210399166 | LIGHT-EMITTING DIODE AND PROCESS FOR PRODUCING A LIGHT-EMITTING DIODE - A light-emitting diode | 2021-12-23 |
20210399167 | SINGLE CHIP MULTI BAND LED AND APPLICATION THEREOF - A lighting apparatus includes a light emitting diode, in which the light emitting diode includes an n-type nitride semiconductor layer, an active layer located on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer located on the active layer. The light emitting diode emits light that varies from yellow light to white light depending on an driving current. | 2021-12-23 |
20210399168 | LIGHT EMITTING DEVICE - A light emitting device includes a first light emitting cell and a second light emitting cell. Each light emitting cell includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers. The second semiconductor layer of the second light emitting cell has an exposed surface. A transparent bonding layer is located between the first and second light emitting cells. A hole is formed on the first and second light emitting cells and the transparent bonding layer. A first route metal is located on a sidewall of the hole and electrically coupled to the second semiconductor layer of the first light emitting cell and the first semiconductor layer of the second light emitting cell. The active layer of the second light emitting cell has an area greater than the active layer of the first light emitting cell. | 2021-12-23 |
20210399169 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip may have or include an x-doped region, a y-doped region, an active region arranged between the x-doped region and the y-doped region, and an x-contact region. The x-contact region may be arranged to the side of the x-doped region facing away from the active region. The x-contact region may include at least one first region and at least one second region. The x-contact region may be designed such that, during operation of the optoelectronic semiconductor chip, more charge carriers are injected into the x-doped region via the second region than via the first region. | 2021-12-23 |
20210399170 | LIGHT EMITTING DEVICE - A light-emitting device comprises a substrate; a first semiconductor layer formed on the substrate; a first patterned layer formed on the first semiconductor layer; and a second semiconductor layer formed on the first semiconductor layer, wherein the second semiconductor layer comprises a core layer comprising a group III or transition metal material formed along the first patterned layer. | 2021-12-23 |
20210399171 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor light emitting device according to an embodiment of the present invention includes a growth substrate, a first conductivity type semiconductor layer formed on the growth substrate, an active layer formed in a partial region on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer, a trench formed by etching a portion of the surface of the second conductivity type semiconductor layer, and metal nanoparticles inserted into the trench. | 2021-12-23 |
20210399172 | DISPLAY DEVICE - A display device includes a substrate, a plurality of pixels provided to the substrate, a plurality of light emitting elements provided to each of the pixels, and a cathode electrode covering the light emitting elements. The light emitting elements each include a p-type cladding layer, an active layer, an n-type cladding layer, and a high-resistance layer stacked in order on the substrate, sheet resistance of the high-resistance layer is higher than sheet resistance of the n-type cladding layer, an upper surface of the n-type cladding layer has a plurality of recesses, and the cathode electrode covers the high-resistance layer and is directly coupled to the recesses and a peripheral part of the n-type cladding layer. | 2021-12-23 |
20210399173 | NANOROD LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nanorod light-emitting device including a first semiconductor layer doped with a first conductive type impurity, an emission layer disposed above the first semiconductor layer, a second semiconductor layer disposed above the emission layer and doped with a second conductive type impurity that is electrically opposite to the first conductive type impurity, a conductive layer disposed between at least one of a center portion of a lower surface of the emission layer and the first semiconductor layer and a center portion of an upper surface of the emission layer and the second semiconductor layer, and a current blocking layer surrounding a sidewall of the conductive layer. | 2021-12-23 |
20210399174 | LIGHT-EMITTING SEMICONDUCTOR STRUCTURE AND LIGHT-EMITTING SEMICONDUCTOR SUBSTRATE - A light-emitting semiconductor substrate, which is applied to a light-emitting semiconductor structure, includes a base and a plurality of particle groups. The base includes an upper surface. The particle groups are on the upper surface or inside the base dispersedly, and each of the particle groups includes Sn, Sn compounds or combinations thereof. | 2021-12-23 |
20210399175 | NITRIDE SEMICONDUCTOR DEVICE AND SUBSTRATE THEREOF, METHOD FOR FORMING RARE EARTH ELEMENT-ADDED NITRIDE LAYER, AND RED-LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The purpose of the present invention is to provide a technique of manufacturing a nitride semiconductor layer with which, when producing a semiconductor device by forming a nitride semiconductor layer on off-angle inclined substrate, it is possible to stably supply high-quality semiconductor devices by preventing occurrence of a macro step using a material that is not likely to occur lattice strains or crystal defects by mixing with GaN and does not require continuous addition; and provided is a nitride semiconductor device which comprises a nitride semiconductor layer formed on a substrate, wherein the substrate is inclined at an off angle, a rare earth element-added nitride layer to which a rare earth element is added is formed on the substrate as a primed layer, and a nitride semiconductor layer is formed on the rare earth element-added nitride layer. | 2021-12-23 |
20210399176 | LIGHT EMITTING SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer; a first electrode provided on a first surface of the first semiconductor layer; a second electrode provided on a first surface of the second semiconductor layer, the active layer being provided between the first surface of the first semiconductor layer and a second surface of the second semiconductor layer that is opposite to the first surface of the second semiconductor layer; a first insulation layer provided on the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and a side surface of the active layer; a first cover electrode provided on the first electrode; a second cover electrode provided on the second electrode, a second insulation layer provided on the first cover electrode, the second cover electrode, and the first insulation layer, wherein: the second insulation layer includes a first opening over the first cover electrode and a second opening over the second cover electrode, and a plan view of the semiconductor includes a light emitting region that includes a surface of the second cover electrode in the second opening of the second insulation layer, and a non-light emitting region that includes a surface of the first cover electrode in the second opening of the first insulation layer, and a first area of the non-light emitting region is smaller than a second area of the light emitting region. | 2021-12-23 |
20210399177 | DISPLAY DEVICE - A display device includes a substrate; a first circuit part and a second circuit part on the substrate and spaced from each other in a first direction; and an emission part between the first circuit part and the second circuit part, the emission part being located between the first circuit part and the second circuit part in a direction parallel to the substrate, wherein the first circuit part includes a first electrode extending to the emission part, wherein the second circuit part includes a second electrode extending to the emission part, and wherein the emission part includes a light emitting element located between the first electrode and the second electrode. | 2021-12-23 |
20210399178 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR - An electronic device that includes a base member made of a material containing metal atoms, the base member having a bonding surface, and the bonding surface contains oxides of the metal atoms; an electronic element is mounted on the base member; an organic structure on the bonding surface of the base member; and a cover member bonded to the bonding surface of the base member via the organic structure so as to encapsulate the electronic element in a space between the base member and the cover member. | 2021-12-23 |
20210399179 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure includes a substrate, a light emitting unit, a wavelength conversion layer, and a reflective structure. The light emitting unit and the reflective structure are disposed on a mounting surface of the substrate. The wavelength conversion layer is disposed on the light emitting unit. The wavelength conversion layer has a light input surface, a top light output surface opposite to the light input surface, and a side light output surface connecting the light input surface and the top light output surface. The reflective structure surrounds the light emitting unit and the wavelength conversion layer. The reflective structure has a top reflecting surface located on a top of the reflective structure, and a height position of the top reflecting surface is higher than a height position of the light input surface and lower than a height position of the top light output surface. | 2021-12-23 |
20210399180 | OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - The invention relates to an optoelectronic component, comprising: at least two optoelectronic semiconductor chips, which are designed to emit electromagnetic radiation during operation; at least one connecting element, which is electrically conductive, flexible and extensible; and a shaped body, which surrounds the at least two optoelectronic semiconductor chips and the at least one connecting element at least in some locations, wherein the optoelectronic semiconductor chips are each arranged on a carrier. The invention further relates to a method for producing an optoelectronic component. | 2021-12-23 |
20210399181 | DISPLAY DEVICE - A display device comprises first and second pixels, a light-emitting layer, color conversion layers, and color filter layers, the light-emitting layer comprising first and second light-emitting elements in the first and second pixels, wherein the color conversion layers comprise first and second color conversion layers in the first and second pixels, the color filter layers comprise first and second color filter layers in the first and second pixels, the first and second light-emitting elements emit first light having a central wavelength range of a first wavelength, the first and second color conversion layers contain color conversion particles converting the first light into second light having a central wavelength range of a second wavelength longer than the first wavelength, the first color filter layer transmits the first light and blocks the second light, and the second color filter layer transmits the second light and blocks transmission of the first light. | 2021-12-23 |
20210399182 | LIGHT-EMITTING DIODE PACKAGE HAVING CONTROLLED BEAM ANGLE AND LIGHT-EMITTING DEVICE USING SAME - A light-emitting diode package having a controlled beam angle is proposed. The diode package can include at least one first lead frame; at least one second lead frame formed to correspond to and be spaced apart from the at least one first lead frame; light-emitting diode chips mounted on the at least one first lead frame; a first package main body which is fixed on the partial surfaces of the at least one first lead frame and the at least one second lead frame and formed so as to have a first inclined side at a portion of the circumference around the light-emitting diode chips; and a second package main body formed so as to have a second inclined side at the remaining portion of the circumference around the light-emitting diode chips other than the portion. | 2021-12-23 |
20210399183 | ACTIVE ELECTRICAL ELEMENTS WITH LIGHT-EMITTING DIODES - Light-emitting devices with active electrical elements and light-emitting diodes (LEDs) are disclosed. LEDs may be mounted on an active electrical element such that the LEDs are within peripheral edges of the active electrical element. Contact pads may be arranged on the active electrical element for receiving external power and communication signals for active control of the LEDs. A light-transmissive carrier may be positioned over the active electrical element and the LEDs. Electrical traces of the carrier may be configured to electrically connect with the contact pads to route external power connections and communication signals for the active electrical element. Other electrical traces of the carrier may form a touch sensing element that is electrically coupled with the active electrical element. Active electrical elements with LEDs provided thereon may form compact sizes for use as active LED pixels configured for active-matrix addressing within an LED display. | 2021-12-23 |
20210399184 | STACKED SEMICONDUCTOR DEVICE, AND SET OF ONBOARD-COMPONENTS, BODY AND JOINTING-ELEMENTS TO BE USED IN THE STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor. | 2021-12-23 |
20210399185 | DISPLAY PANEL AND MANUFACTURING METHOD - The present disclosure provides a display panel and a manufacturing method. The display panel includes: a base substrate including a display surface and a display back surface arranged opposite to each other, and a side surface connected to the display surface and the display back surface; a plurality of first wirings on the display surface of the base substrate; a plurality of second wirings on the display back surface of the base substrate; a transition body on the side surface of the base substrate and in contact with the first wirings and the second wirings, a surface of the transition body away from the side surface being a smooth curved surface; and a plurality of connection lines covering an outer surface of the transition body, each first wiring being electrically connected to a corresponding second wiring via a corresponding connection line. | 2021-12-23 |
20210399186 | LOW POWER THERMOELECTRIC SYSTEMS - A device for manipulating the temperature of a surface may include a heat transfer surface including active portions and a passive portion. The passive portion may include an inner passive portion disposed between each of the active portions and/or may include an outer passive portion that may surround each of the active portions. The active portions may form 40-90% of a total surface area of the heat transfer surface, where total surface area includes active portions and an inner passive portion. The passive portion(s) may have a thermal conductivity less than the active portion. A processor may be in electrical communication with thermoelectric modules defining or forming the active portions to generate a heat flux through the heat transfer surface. The heat flux through the active portions may be between 500 and 15,000 W/m | 2021-12-23 |
20210399187 | THERMOELECTRIC STRUCTURE AND METHOD - A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures. | 2021-12-23 |
20210399188 | Method for Wireless Power Transfer Using Thermoelectric Generators - A TEG system is attached to a rotating shaft and generates electricity from radiant energy that is substantially radiatively transmitted through the atmosphere from a stationary source to the TEG system that is rotating with the shaft. The rotation of the shaft provides cooling to the TEG system, but not heat energy. The TEG system includes at least one TEG, each TEG equipped with an energy receiving and heat containment window and an energy conversion system in combination with controlled convection cooling enhanced by an airflow moving in response to the rotation of the rotating shaft. Individual TEGs having controlled convection cooling also are described. | 2021-12-23 |
20210399189 | BULK THERMOELECTRIC DEVICE PREPARATION METHOD - The present invention relates to a method of manufacturing a bulk type thermoelectric element implemented so as to simplify the manufacturing process as well as to reduce the manufacturing cost. The method of manufacturing a bulk type thermoelectric element includes the steps of: preparing two types of P-type and N-type substrates by slicing a thermoelectric element material; bonding P-type pellets formed on the P-type substrate and N-type pellets formed on the N-type substrate to each other to alternately engaging with each other, and then polishing (grinding) the bottom of each substrate to form a P/N layer in which the P-type pellets and the N-type pellets are cross-formed; and assembling ceramic substrates with conductive electrode pads (PAD) on the top and the bottom of the P/N layer to complete a thermoelectric element. | 2021-12-23 |
20210399190 | Apparatus Including Thermal Energy Harvesting Thermionic Device, and Related Methods - Embodiments relate to a method in which electrical energy is supplied to a heat generating source to convert the electrical energy to heat. A thermal energy harvesting thermionic device proximal to the heat generating source to receive the heat from the heat generating source is heated and an electrical output is generated. The thermal energy harvesting thermionic device includes at least a cathode, an anode spaced from the cathode to provide an inter-electrode gap between the cathode and the anode, and a plurality of nanoparticles suspended in a fluid medium contained in the inter-electrode gap. The temperature of the thermal energy harvesting thermionic device is monitored, and a source of the electrical energy is activated to supply the electrical energy to the heat generating source in response to a change in the temperature of the thermal energy harvesting thermionic device. Also provided are related apparatus. | 2021-12-23 |
20210399191 | ACTIVE MATERIAL AND ELECTRIC POWER GENERATOR CONTAINING IT - The invention relates to an active material comprising at least one oxygen-containing compound selected from Fe | 2021-12-23 |
20210399192 | SUPERCONDUCTING QUBIT LIFETIME AND COHERENCE IMPROVEMENT VIA BACKSIDE ETCHING - A method for improving lifetime and coherence time of a qubit in a quantum mechanical device is provided. The method includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit having capacitor pads. The method further includes at least one of removing an amount of substrate material from the backside of the substrate at an area opposite the at least one qubit or depositing a superconducting metal layer at the backside of the substrate at the area opposite the at least one qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface so as to enhance a lifetime (T1) and a coherence time (T2) in the at least one qubit. | 2021-12-23 |
20210399193 | QUANTUM DEVICE AND METHOD OF MANUFACTURING THE SAME - A quantum device ( | 2021-12-23 |
20210399194 | QUANTUM DEVICE AND METHOD OF MANUFACTURING THE SAME - A quantum device ( | 2021-12-23 |
20210399195 | QUANTUM DEVICE - A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device | 2021-12-23 |
20210399196 | QUANTUM DEVICE - A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip | 2021-12-23 |
20210399197 | QUANTUM DEVICE - A quantum device according to an example embodiment includes a quantum chip | 2021-12-23 |
20210399198 | Digital Circuits Comprising Quantum Wire Resonant Tunneling Transistors - A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires. | 2021-12-23 |
20210399199 | SPURIOUS JUNCTION PREVENTION VIA IN-SITU ION MILLING - Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material. | 2021-12-23 |
20210399200 | METHOD FOR THE IN SITU PRODUCTION OF MAJORANA MATERIAL SUPERCONDUCTOR HYBRID NETWORKS AND TO A HYBRID STRUCTURE WHICH IS PRODUCED USING THE METHOD - A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere. | 2021-12-23 |
20210399201 | DRIVER CIRCUITRY FOR PIEZOELECTRIC TRANSDUCERS - The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: output stage circuitry configured to receive an input signal and to drive the piezoelectric transducer to produce the output signal; variable voltage power supply circuitry configured to output a supply voltage for the charge drive output stage circuitry, wherein the supply voltage output by the variable voltage power supply circuitry varies based on the input signal; a supply capacitor for receiving the supply voltage output by the variable voltage power supply circuitry; a reservoir capacitor; and circuitry for transferring charge between the reservoir capacitor and the supply capacitor. | 2021-12-23 |
20210399202 | PIEZOELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A piezoelectric device that exhibits good piezoelectric characteristics, while reducing generation of leakage current paths, and a method of manufacturing the same, are provided. The piezoelectric device has a multilayer stack in which a first electrode, a piezoelectric layer, and a second electrode are stacked in this order on a substrate, wherein at least the first electrode is formed of an amorphous oxide conductor. | 2021-12-23 |
20210399203 | Metamaterial-Based Substrate for Piezoelectric Energy Harvesters - A metamaterial-based substrate (meta-substrate) for piezoelectric energy harvesters. The design of the meta-substrate combines kirigami and auxetic topologies to create a high-performance platform including preferable mechanical properties of both metamaterial morphable structures. The creative design of the meta-substrate can improve strain-induced vibration applications in structural health monitoring, internet-of-things systems, micro-electromechanical systems, wireless sensor networks, vibration energy harvesters, and other applications whose efficiency is dependent on their deformation performance. The meta-substrate energy harvesting device includes a meta-material substrate comprising an auxetic frame having two kirigami cuts and a piezoelectric element adhered to the auxetic frame by means of a thin layer of elastic glue. | 2021-12-23 |
20210399204 | IMPROVEMENTS IN OR RELATING TO ENERGY GENERATION IN A PIEZOELECTRIC SWITCH - The present invention provides an energy harvesting system that removes the need for batteries for sensing and actuating purposes through the use of energy harvesting materials such as piezoelectric transducers. The present invention particularly provides clamping and actuation mechanisms for energy harvesting applications including energy harvesting switches, more particularly energy harvesting wireless switches. The present invention is designed to produce sufficient instantaneous energy to power low-power circuits such as radio transmitters, allowing for seamless integration with existing smart devices. In addition, the system benefits from battery less operation, eliminating the need for regular battery maintenance and replacement as well as end of life recycling. An energy harvesting system is provided comprising:
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20210399205 | Piezoelectric Element, Piezoelectric Element Application Device - A piezoelectric element 1 includes a first electrode | 2021-12-23 |
20210399206 | PATTERNING OF ORGANIC FILM BY WET ETCHING PROCESS - An organic film is patterned without applying a hard mask or photolithography. A hydrophilic solvent-soluble resist is placed and arranged on the organic film using a non-lithography process. The hydrophilic solvent-soluble resist is placed and arranged using a printing or lamination process. The organic film is patterned using a wet etchant that is selective to the organic film but non-selective to the hydrophilic solvent-soluble resist. The hydrophilic solvent-soluble resist protects the underlying organic film from contamination and damage, prevents undercutting, and assists in providing a desired taper profile during patterning. | 2021-12-23 |
20210399207 | MEMORY CELL WITH LOW RESISTANCE TOP ELECTRODE CONTACT AND METHODS FOR FORMING THE SAME - A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack. | 2021-12-23 |
20210399208 | MAGNETORESISTANCE EFFECT ELEMENT, MAGNETIC MEMORY, AND FILM FORMATION METHOD FOR SAID MAGNETORESISTANCE EFFECT ELEMENT - For implementation of a magnetoresistance effect element having a quadruple interface, a magnetoresistance effect element having a small resistance area product RA, a high magnetoresistance ratio, and a high effective magnetic anisotropy energy density K | 2021-12-23 |
20210399209 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses. | 2021-12-23 |
20210399210 | SPIN ELEMENT AND RESERVOIR ELEMENT - A spin element includes a wiring, a laminated body including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part which sandwich the first ferromagnetic layer in a plan view in a laminating direction, and a first high resistance layer which is in contact with the wiring between the first conductive part and the wiring and has an electrical resistivity equal to or higher than that of the wiring. | 2021-12-23 |
20210399211 | STORAGE ELEMENT, SEMICONDUCTOR DEVICE, MAGNETIC RECORDING ARRAY, AND METHOD OF MANUFACTURING STORAGE ELEMENT - A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring that extends in a second direction different from the first direction and together with the nonmagnetic layer sandwiches the first ferromagnetic layer in the first direction; and an electrode that together with the nonmagnetic layer sandwiches the second ferromagnetic layer in at least a part in the first direction, wherein the electrode is in contact with at least a part of a lateral side surface of the second ferromagnetic layer. | 2021-12-23 |
20210399212 | DIELECTRIC RETENTION AND METHOD OF FORMING MEMORY PILLAR - A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer. | 2021-12-23 |
20210399213 | MULTI TERMINAL DEVICE STACK FORMATION METHODS - Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device. | 2021-12-23 |
20210399214 | METHOD FOR MANUFACTURING MAGNETIC TUNNEL JUNCTION - Disclosed is a method for manufacturing a magnetic tunnel junction, using an etching apparatus including a sample loading chamber, a vacuum transition chamber, a reactive ion plasma etching chamber, an ion beam etching chamber, a coating chamber and a vacuum transmission chamber, wherein a magnetic tunnel junction is etched, cleaned and coated for protection without interrupting a vacuum by using the reactive ion plasma etching chamber, the ion beam etching chamber, and the coating chamber in combination. The invention can effectively reduce damages and contaminations of devices, avoid the influence caused by over-etching, and improve performance of devices; at the same time, it can accurately control the steepness of an etching pattern and obtain a pattern result that meets performance requirements. | 2021-12-23 |
20210399215 | ETCHING METHOD FOR SINGLE-ISOLATED MAGNETIC TUNNEL JUNCTION - A method for etching magnetic tunnel junction of single isolation layer, using an etching apparatus including a sample loading chamber, a vacuum transition chamber, a reactive ion etching chamber, an ion beam etching chamber, a coating chamber, and a vacuum transmission chamber, is applicable for the reactive ion etching chamber, ion beam etching chamber and coating chamber to process and treat a wafer according to specific steps without interrupting a vacuum. It can effectively alleviate the influence of masking effect in the production process of high-density small devices. Furthermore, the combined use of the ion beam etching chamber and the reactive ion etching chamber greatly reduces metal contaminations and damage on the film structure of the magnetic tunnel junction, greatly improves the performance and reliability of the devices, overcomes the technical problems existing in a single etching process in the art, and improves production efficiency and etching process accuracy | 2021-12-23 |
20210399216 | METHOD FOR ETCHING MAGNETIC TUNNEL JUNCTION - Disclosed is method for etching a magnetic tunnel junction. An etching apparatus used comprises a sample loading chamber, a vacuum transition chamber, a reactive ion plasma etching chamber, an ion beam etching chamber, a film coating chamber and a vacuum transport chamber. The method comprises multiple performances of the steps of reactive ion and plasma etching, ion beam etching and film coating. Multiple performances of entry into and exit from the chambers are required during the process, and the delivery between the chambers is performed under vacuum. | 2021-12-23 |
20210399217 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, wherein the etching apparatus used includes a sample loading chamber ( | 2021-12-23 |