51st week of 2017 patent applcation highlights part 56 |
Patent application number | Title | Published |
20170365448 | COIL FILAMENT FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION SOURCE - A vapor deposition source that includes a substantially vertical plate to which first and second filament posts are coupled. The vapor deposition source also includes a filament having a first end and a second end. The filament provides a substantially concentric source of electrons. The first end of the filament is connected to the first filament post and the second end of the filament is connected to the second filament post. The first end of the filament is substantially vertically aligned with the second end of the filament when the filament is connected to the first and second posts. | 2017-12-21 |
20170365449 | RF RETURN STRAP SHIELDING COVER - Embodiments described herein generally relate to a substrate support assembly having a shield cover. In one embodiment, a substrate support assembly is disclosed herein. The substrate support assembly includes a support plate, a plurality of RF return straps, at least one shield cover, and a stem. The support plate is configured to support a substrate. The plurality of RF return straps are coupled to a bottom surface of the support plate. At least one shield cover is coupled to the bottom surface of the support plate, between the plurality of RF return straps and the bottom surface. The stem is coupled to the support plate. | 2017-12-21 |
20170365450 | CLEANING PROCESS FOR REMOVING BORON-CARBON RESIDUALS IN PROCESSING CHAMBER AT HIGH TEMPERATURE - Embodiments of the invention generally relate to methods for removing a boron-carbon layer from a surface of a processing chamber using water vapor plasma treatment. In one embodiment, a method for cleaning a surface of a processing chamber includes positioning the pedestal at a first distance from the showerhead, and exposing a deposited boron-carbon layer to a first plasma process where the first plasma process comprises generating a plasma that comprises water vapor and a first carrier gas by biasing a showerhead that is disposed over a pedestal, and positioning the pedestal at a second distance from the showerhead and exposing the deposited boron-carbon layer to a second plasma process where the second plasma process comprises generating a plasma that comprises water vapor and a second carrier gas by biasing the showerhead and biasing a side electrode relative to the showerhead. | 2017-12-21 |
20170365451 | SPUTTERING APPARATUS AND METHOD FOR FORMING SEMICONDUCTOR FILM USING SPUTTERING APPARATUS - A novel sputtering apparatus capable of separating functions can be provided. A sputtering apparatus is capable of forming a semiconductor film and includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, and a second driver portion connected to the second shutter. The first driver portion and the second driver portion operate in conjunction with each other. | 2017-12-21 |
20170365452 | Method of Calibrating Ion Signals - A method of mass or ion mobility spectrometry is disclosed comprising: providing an ion source for generating analyte ions and reference ions; providing a mass analyser or ion mobility separator (IMS); providing an ion trap between the ion source and the mass analyser or IMS; guiding reference ions from the ion source into the ion trap and trapping the reference ions in the ion trap; guiding the analyte ions from the ion source into the mass analyser or IMS, wherein the analyte ions bypass the ion trap; and releasing reference ions from the ion trap into the mass analyser or IMS for analysis. | 2017-12-21 |
20170365453 | Methods of Performing Ion-Ion Reactions in Mass Spectrometry - A method is described that produces product ions for mass analysis, the method comprising the steps of: introducing precursor ions into an RF electric field ion containment device, introducing reagent ions into the RF electric field ion containment device and performing an ion-ion interaction in the RF electric field ion containment device by co-trapping the precursor ions with the reagent ions. Precursor ions and product ions may be retained and/or isolated in the RF electric field ion containment device. The steps above may be repeated until a predetermined amount of reaction completeness is attained. Mass analysis of at least some of the ions in the RF electric field ion containment device may be performed where the ions are mass analyzed either directly from the RF electric field ion containment device. | 2017-12-21 |
20170365454 | CHEMICALLY MODIFIED ION MOBILITY SEPARATION APPARATUS AND METHOD - An ion mobility spectrometry apparatus and method wherein ions are selected using an AC gate, then separated along a drift axis while providing a drift gas flow in a direction that is substantially neither in the direction of the drift axis nor opposite to the drift axis. | 2017-12-21 |
20170365455 | CONCENTRIC APCI SURFACE IONIZATION ION SOURCE, ION GUIDE, AND METHOD OF USE - A concentric APCI surface ionization probe, supersonic sampling tube, and method for use of the concentric APCI surface ionization probe and supersonic sampling tube are described. In an embodiment, the concentric APCI surface ionization probe includes an outer tube, an inner capillary, and a voltage source coupled to the outer tube and the inner capillary. The inner capillary is housed within and concentric with the outer tube such that ionized gas (e.g., air) travels out of the outer tube, reacts with a sample, and the resulting analyte ions are sucked into the inner capillary. A supersonic sampling tube can include a tube coupled to a mass spectrometer and/or concentric APCI surface ionization probe, where the tube includes at least one de Laval nozzle. | 2017-12-21 |
20170365456 | Ion Trap Mass Spectrometer - An apparatus | 2017-12-21 |
20170365457 | Ion Trap Mass Spectrometer - An apparatus | 2017-12-21 |
20170365458 | Adduct-Based System and Methods for Analysis and Identification of Mass Spectrometry Data - A system and method to screen a plurality of molecules in datasets obtained from mass spectroscopy, including selecting and receiving at least one dataset of mass spectral data, and selecting customizable m/z mass tolerance peaks to assign initial compound assignments from at least one adduct ion hierarchy database for at least one compound having a parent molecule. Adduct ion hierarchy screening is applied to at least a portion of the dataset, wherein selected dataset features are tested to determine if they represent the most abundant expected adduct of the parent molecule class and if the expected adduct assignment hierarchy are present in the dataset. | 2017-12-21 |
20170365459 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND RECORDING MEDIUM - To reduce a hydroxy group in a silicon oxide film formed at a low temperature and obtain a silicon oxide film with an excellent film quality, (a) accommodating a substrate on a surface of which a silicon oxide film formed at a processing temperature of 300° C. or lower is formed in a processing container, (b) plasma-exciting a hydrogen gas, and a step of supplying hydrogen active species generated in (b) to the substrate are performed. | 2017-12-21 |
20170365460 | METHOD AND A PROCESSING DEVICE FOR PROCESSING AT LEAST ONE CARRIER - A processing device including: a chamber to accommodate at least one carrier in a processing region of the chamber, an inlet structure disposed over the chamber, the inlet structure providing a merging region fluidly connected to the processing region, a first liquid control arrangement coupled at least to the chamber, the first liquid control arrangement configured to provide a first liquid in the processing region of the chamber and to raise a level of the first liquid into the merging region of the inlet structure, and a second liquid control arrangement coupled to the inlet structure, the second liquid control arrangement configured to introduce a second liquid in the merging region, wherein the first liquid control arrangement is further configured to drain the first liquid from the chamber to form a continuous surface layer of the second liquid on the first liquid and to expose the at least one carrier. | 2017-12-21 |
20170365461 | DISPLAY DEVICE, DRIVING METHOD OF THE SAME, AND ELECTRONIC DEVICE - A display device which can display a clear image and can display an image with low power consumption is provided. The display device includes an arithmetic circuit having a function of generating first to third display data, a first display portion, and a second display portion. The arithmetic circuit has a function of detecting a color region and a gray-scale region of the generated first display data and generating the second display data corresponding to an image to be displayed on the first display portion and the third display data corresponding to an image to be displayed on the second display portion, on the basis of the detection results. | 2017-12-21 |
20170365462 | REMOTE PLASMA BASED DEPOSITION OF OXYGEN DOPED SILICON CARBIDE FILMS - Disclosed are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide film. The one or more radical species can be formed in a remote plasma source. | 2017-12-21 |
20170365463 | EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL WAFER AND PROCESS FOR PRODUCING THE SAME - An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 μm or more and 10 μm or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 μm or more and 100 μm or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less. | 2017-12-21 |
20170365464 | Compound Semiconductor Substrate and Method of Forming a Compound Semiconductor Substrate - A method of forming a compound semiconductor substrate includes providing a crystalline base substrate having a first semiconductor material and a main surface, and forming a first semiconductor layer on the main surface and having a pair of tracks disposed on either side of active device regions. The first semiconductor layer is formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material. The pair of tracks have a relatively weaker crystalline structure than the active device regions. The method further includes thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate. The pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling. | 2017-12-21 |
20170365465 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MANUFACTURING APPARATUS - There is provided a method of manufacturing a semiconductor device, which includes: forming a silicon film inside a recess formed in a surface of a workpiece by supplying a film forming gas containing silicon to the workpiece; subsequently, supplying a process gas, which includes a halogen gas for etching the silicon film and a roughness suppressing gas for suppressing roughening of a surface of the silicon film after being etched by the halogen gas, to the workpiece; etching the silicon film formed on a side wall of the recess to enlarge an opening width of the recess by applying thermal energy to the process gas and activating the process gas; and subsequently, filling silicon into the recess by supplying the film forming gas to the workpiece and depositing silicon on the silicon film remaining in the recess. | 2017-12-21 |
20170365466 | FILM FORMING METHOD AND ALUMINUM NITRIDE FILM FORMING METHOD FOR SEMICONDUCTOR APPARATUS - The present disclosure provides a film forming method and an aluminum nitride film forming method for a semiconductor device. The film forming method for a semiconductor device includes performing multiple sputtering routes sequentially. Each sputtering routes includes: loading a substrate into a chamber; moving a shielding plate between a target and the substrate; introducing an inert gas into the chamber to perform a surface modification process on the target; performing a pre-sputtering to pre-treat a surface of the target; moving the shielding plate away from the substrate, and performing a main sputtering on the substrate to form a film on the substrate; and moving the substrate out of the chamber. | 2017-12-21 |
20170365467 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a method of manufacturing a semiconductor device, which includes: forming a first seed layer containing silicon and germanium on a substrate by performing, a predetermined number of times, a cycle which includes supplying a first process gas containing silicon or germanium and containing a halogen element to the substrate, supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing germanium and not containing a halogen element to the substrate; and forming a germanium-containing film on the first seed layer by supplying a fourth process gas containing germanium and not containing a halogen element to the substrate. | 2017-12-21 |
20170365468 | PRE-CLEAN OF SILICON GERMANIUM FOR PRE-METAL CONTACT AT SOURCE AND DRAIN AND PRE-HIGH K AT CHANNEL - The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species. | 2017-12-21 |
20170365469 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF ITS PRODUCTION - The present document discloses a semiconductor device structure ( | 2017-12-21 |
20170365470 | DEVICE SUBSTRATE, METHOD OF MANUFACTURING DEVICE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region. | 2017-12-21 |
20170365471 | MASK SUBSTRATE STRUCTURE - The present disclosure relates to lithographic masks and, more particularly, to a lithographic mask substrate structure and methods of manufacture. The mask includes a sub-resolution assist feature (SRAF) formed on a quartz substrate and composed of a patterned transition film and absorber layer. | 2017-12-21 |
20170365472 | CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING - The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material. | 2017-12-21 |
20170365473 | METHODS FOR FORMING STRUCTURES BY GENERATION OF ISOLATED GRAPHENE LAYERS HAVING A REDUCED DIMENSION - Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device. | 2017-12-21 |
20170365474 | DEPOSITING A PASSIVATION LAYER ON A GRAPHENE SHEET - Embodiments of the disclosed technology include depositing a passivation layer onto a surface of a wafer that may include a graphene layer. The passivation layer may protect and isolate the graphene layer from electrical and chemical conditions that may damage the graphene layer. As such, the passivation layer may further protect the graphene sensor from being damaged and impaired for its intended use. Additionally, the passivation layer may be patterned to expose select areas of the graphene layer below the passivation layer, thus creating graphene wells and exposing the graphene layer to the appropriate chemicals and solutions. | 2017-12-21 |
20170365475 | LASER DOPING APPARATUS AND LASER DOPING METHOD - The laser doping apparatus may irradiate a predetermined region of a semiconductor material with a pulse laser beam to perform doping. The laser doping apparatus may include: a solution supplying system configured to supply dopant-containing solution to the predetermined region, and a laser system including at least one laser device configured to output the pulse laser beam to be transmitted by the dopant-containing solution, and a time-domain pulse waveform changing apparatus configured to control a time-domain pulse waveform of the pulse laser beam. | 2017-12-21 |
20170365476 | CREATION OF HYPERDOPED SEMICONDUCTORS WITH CONCURRENT HIGH CRYSTALLINITY AND HIGH SUB-BANDGAP ABSORPTANCE USING NANOSECOND LASER ANNEALING - In one aspect, a method of processing a semiconductor substrate is disclosed, which comprises incorporating at least one dopant in a semiconductor substrate so as to generate a doped polyphase surface layer on a light-trapping surface, and optically annealing the surface layer via exposure to a plurality of laser pulses having a pulsewidth in a range of about 1 nanosecond to about 50 nanoseconds so as to enhance crystallinity of said doped surface layer while maintaining high above-bandgap, and in many embodiments sub-bandgap optical absorptance. | 2017-12-21 |
20170365477 | PROVIDING A TEMPORARY PROTECTIVE LAYER ON A GRAPHENE SHEET - Embodiments of the disclosed technology include patterning a graphene sheet for biosensor and electronic applications using lithographic patterning techniques. More specifically, the present disclosure is directed towards the method of patterning a graphene sheet with a hard mask metal layer. The hard mask metal layer may include an inert metal, which may protect the graphene sheet from being contaminated or damaged during the patterning process. | 2017-12-21 |
20170365478 | NOVEL METHODS OF ATOMIC LAYER ETCHING (ALE) USING SEQUENTIAL, SELF-LIMITING THERMAL REACTIONS - The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. The invention provides a solid substrate obtained according to any of the methods of the invention. The invention further provides a porous substrate obtained according to any of the methods of the invention. The invention further provides a patterned solid substrate obtained according to any of the methods of the invention. | 2017-12-21 |
20170365479 | SEMICONDUCTOR DEVICE - The present disclosure provides semiconductor devices and fabrication methods thereof. A work function layer is formed on the semiconductor substrate. A buffer layer is formed on the work function layer. The work function layer is doped through the buffer layer with impurity ions. The buffer layer obstructs a flow of the impurity ions to control a concentration of the impurity ions in different regions of the work function layer to regulate a work function of the work function layer in the different regions. | 2017-12-21 |
20170365480 | HYDROGENATION AND NITRIDIZATION PROCESSES FOR MODIFYING EFFECTIVE OXIDE THICKNESS OF A FILM - Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques. | 2017-12-21 |
20170365481 | SEMICONDUCTOR STRUCTURES - Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods. | 2017-12-21 |
20170365482 | Method For Growing NI-Containing Thin Film With Single Atomic Layer Deposition Technology - The present invention provides a method for growing ni-containing thin film with single atomic layer deposition technology, comprising steps of: A) placing a substrate in a reaction chamber, and under the vacuum condition, passing a gas-phase Ni source in a form of pulses into the reaction chamber for deposition to obtain a substrate deposited with the Ni source, the Ni source comprising a compound having a structure of Formula I; B) passing a gas-phase reducing agent in a form of pulses into the reaction chamber to reduce the Ni source deposited on the substrate, obtaining a substrate deposited with a Ni thin film. The application of the Ni source having a structure of Formula I in the single atomic layer deposition technology allows a Ni-containing deposition layer with good shape retention to be deposited and formed on a nano-sized semiconductor device. | 2017-12-21 |
20170365483 | ATOMIC LAYER DEPOSITION METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed. | 2017-12-21 |
20170365484 | PRINTING OF THREE-DIMENSIONAL METAL STRUCTURES WITH A SACRIFICIAL SUPPORT - A method for 3D printing includes printing a first metallic material on a substrate as a support structure ( | 2017-12-21 |
20170365485 | ION BEAM ETCHING - Pattern-multiplication via a multiple step ion beam etching process utilizing multiple etching steps. The ion beam is stationary, unidirectional or non-rotational in relation to the surface being etched during the etching steps, but sequential etching steps can utilize an opposite etching direction. Masking elements are used to create additional masking elements, resulting in decreased spacing between adjacent structures and increased structure density. | 2017-12-21 |
20170365486 | PATTERN PROCESSING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE PRODUCT, AND PRETREATMENT LIQUID FOR PATTERN STRUCTURE - Provided are a pattern processing method for applying a pretreatment liquid for modifying the surface of a pattern structure to a semiconductor substrate provided with the pattern structure, which has at least one of polysilicon, amorphous silicon, Ge, or a low dielectric constant material having a k value of 2.4 or less, a method for manufacturing a semiconductor substrate product, and a pretreatment liquid for a pattern structure. | 2017-12-21 |
20170365487 | CHEMISTRIES FOR ETCHING MULTI-STACKED LAYERS - Methods for fabricating a 3D NAND flash memory are disclosed. The method includes the steps of forming a hardmask pattern on the hardmask layer, and using the hardmask pattern to form apertures in the alternating layers by selectively plasma etching the alternating layers versus the hardmask layer using a hydrofluorocarbon etching gas selected from the group consisting of 1,1,1,3,3,3-hexafluoropropane (C | 2017-12-21 |
20170365488 | Method for Forming Semiconductor Device Structure with Fine Line Pitch and Fine End-To-End Space - A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H | 2017-12-21 |
20170365489 | SYSTEM AND METHOD FOR MANUFACTURING A CAVITY DOWN FABRICATED CARRIER - A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion. | 2017-12-21 |
20170365490 | METHODS FOR POLYMER COEFFICIENT OF THERMAL EXPANSION (CTE) TUNING BY MICROWAVE CURING - Methods of curing polyimide to tune the coefficient of thermal expansion are provided herein. In some embodiments, a method of curing a polymer layer on a substrate, includes: (a) applying a variable frequency microwave energy to the substrate to heat the polymer layer and the substrate to a first temperature; and (b) adjusting the variable frequency microwave energy to increase a temperature of the polymer layer and the substrate to a second temperature to cure the polymer layer. | 2017-12-21 |
20170365491 | Continuous Substrate Processing System - A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system. | 2017-12-21 |
20170365492 | WAFER PROCESSOR DOOR INTERFACE - A processing system includes at least one processor having a tank for holding a process liquid. A clean assembly above the tank is provided with an upper housing having at least one upper housing spray nozzle, and a lower housing having at least one lower housing spray nozzle, with the lower housing below the upper housing. A door between the upper housing and the lower housing is movable via an actuator from an open position wherein a load port through the clean assembly is open, to a closed position wherein the load port is closed off. The door largely prevents liquids used in the upper housing from moving down into the process liquid in the tank, and may also improve gas flow in the system. | 2017-12-21 |
20170365493 | HEATING DEVICE AND HEATING CHAMBER - A heating device and a heating chamber are provided, comprising a base plate ( | 2017-12-21 |
20170365494 | System and Method for Decapsulation of Plastic Integrated Circuit Packages - System and method for decapsulation of plastic integrated circuit packages by providing a microwave generator, providing a Beenakker resonant cavity connected to the microwave generator, which cavity comprises a coupling antenna loop, providing the cavity with a tube or tubes for supply of plasma gas and etchant gas or gases and with means for igniting the plasma gas, and providing that the cavity is set at a predefined value of its Q factor by embodying the coupling antenna loop and/or a wire optionally attached to the coupling antenna loop in a metal or metal alloy, or providing that at least at part of its surface area the coupling antenna loop and/or the wire is coated with a metal or metal alloy different than copper and with a higher resistivity than copper. | 2017-12-21 |
20170365495 | Encapsulated Instrumented Substrate Apparatus for Acquiring Measurement Parameters in High Temperature Process Applications - An apparatus includes an instrumented substrate apparatus, a substrate assembly including a bottom and top substrate mechanically coupled, an electronic assembly, a nested enclosure assembly including an outer and inner enclosure wherein the outer enclosure encloses the inner enclosure and the inner enclosure encloses the electronic assembly. An insulating medium between the inner and outer enclosure and a sensor assembly communicatively coupled to the electronic assembly including one or more sensors disposed at one or more locations within the substrate assembly wherein the electronic assembly is configured to receive one or more measurement parameters from the one or more sensors. | 2017-12-21 |
20170365496 | WAFER CONTAINER WIHT SHOCK CONDITION PROTECTION - A front opening wafer container has a container portion and a door sized to close an open front of the container portion. The container portion has shelves for holding wafers defining a seating position and has forward and rearward wafer supports to suspend wafers therebetween in a transport position above the seating position. Shock condition cushion portions are arranged adjacent the transport position for protecting the wafers during a shock condition. The wafers may be bonded wafers having a thinned wafer side and a carrier substrate side. Wafer engagement pads and finger members extend in opposing directions from a central strip on the door providing a balance wafer engagement. When closing the door, a primary wafer support portion engages the wafers first and a secondary elastomeric wafer support engages the wafer secondly. A V-groove for receiving the wafers in the wafer supports has a greater angle defined between the V-groove and the thinned wafer side than the angle defined between the V-groove and carrier substrate side providing enhanced protection for the bonded wafers. | 2017-12-21 |
20170365497 | METHOD AND SYSTEM FOR POSITIONING USING NEAR FIELD TRANSDUCERS, PARTICULARLY SUITED FOR POSITIONING ELECTRONIC CHIPS USING INTERPOSERS - Method for positioning and orienting a first object relative to a second object. Method includes positioning a near field transducer having an aperture on the first object, and directing a laser light toward the aperture of the near field transducer on the first object to create an effervescent wave on the other side of the aperture. Positioning a sensor on the second object for detecting the effervescent wave from the near field transducer. Providing an algorithm, and using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first and second objects in a desired position and orientation relative to the other one of the first and second objects. One or both of the first and second objects may be an interposer, such as a silicon or glass interposer. | 2017-12-21 |
20170365498 | Tri-Modal Carrier for a Semiconductive Wafer - A tri-modal carrier provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The tri-modal carrier includes a doped semiconductive substrate, a plurality of electrostatic field generating (EFG) circuits, and a capacitance charging interface. A positive pole and a negative pole from each EFG circuit are embedded into the doped semiconductive substrate. An exposed portion of the doped semiconductive substrate is located between the positive pole and the negative pole, which is used as a biased pole for each EFG circuit. The combination of these poles for each EFG circuit is used to generate a non-uniform electrostatic field for bonding the semiconductive wafer. The tri-modal carrier also uses flat surface properties and the removal of trapped gas particles to strengthen the bond between the tri-modal carrier and the semiconductive wafer. | 2017-12-21 |
20170365499 | Setting Up Ultra-Small or Ultra-Thin Discrete Components for Easy Assembly - Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component. | 2017-12-21 |
20170365500 | ADHESIVE SHEET FOR LASER DICING AND METHOD FOR MANUFACTURING SEMICONDUCTOR - An adhesive sheet for laser dicing is provided that is capable of, in laser dicing by irradiation with laser light through the adhesive sheet, suppressing laser light scattering in the adhesive sheet while allowing easy chip division by expanding the adhesive sheet and enables inhibition of dust attachment during chip division for chip production in high yields. The present invention provides an adhesive sheet for laser dicing, including a substrate film having a back layer containing a friction reducing agent and an antistatic agent on one surface and having an adhesive layer on another surface, wherein the back layer has a surface with arithmetic mean roughness Ra of 0.1 μm or less, the sheet has a tensile modulus of elasticity at 23° C. from 50 to 200 MPa, and the sheet has a parallel transmittance of 85% or more in a wavelength range from 400 to 1400 nm. | 2017-12-21 |
20170365501 | APPARATUS AND METHOD FOR AUTOMATICALLY SETTING, CALIBRATING AND MONITORING OR MEASURING PICKUP HEAD POSITION AND FORCE DURING COMPONENT PICKUP OPERATIONS - A system is disclosed for calibrating the compressive forces exerted on a component during a component retrieval process from a carrier or support surface by a component handling device. The system includes a sensor, a component pickup assembly having a reference structure, a housing and a spring guide holder coupled to a suction tip. A resilient member may reside within the housing and the reference structure such that the spring guide holder and the housing are spaced from each other to define a variable first gap thereinbetween. A gate is formed by the reference structure and a sheath located on the housing whereby the reference structure is spaced from the housing to define a variable second gap thereinbetween. A detection structure is located within the variable second gap such that the sensor is able to detect portions of the detection structure. The detected portion of the detection structure or element at the second gap size is correlated to the height of the variable first gap and the height of the variable first gap is correlated to a reference predetermined threshold compressive force exerted on the component by the resilient member. | 2017-12-21 |
20170365502 | SEMICONDUCTOR DEVICE POSITIONING SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE POSITIONING - A positioning system and method for positioning a semiconductor device are disclosed. In an embodiment, a positioning system for positioning a semiconductor device includes a long-stroke stage configured to be movable with respect to a supporting structure within a plane and a short-stroke stage attached to the long-stroke stage and configured to carry a semiconductor device and to be rotatable within the plane. The long-stroke stage acts as a balance mass between the short-stroke stage and the supporting structure. | 2017-12-21 |
20170365503 | INTEGRATED CIRCUIT FOR A STABLE ELECTRICAL CONNECTION AND MANUFACTURING METHOD THEREOF - An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode. | 2017-12-21 |
20170365504 | FORMING AIR GAP - A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming conductive interconnects in an ILD including a high etch selectivity dielectric layer such as a silicon nitride with hydrogen component (SiNH) layer, and patterning an air gap mask layer preferably using extreme ultraviolet (EUV) light form an air gap mask. The air gap mask may be used to etch an air gap space in the high etch selectivity dielectric layer. Use of EUV with the high etch selectivity dielectric layer provides an air gap having a width of no greater than 15 nm with the opening used to form the air gap space having a width of no greater than 10 nm width. This integration approach offers smaller pinch-off height, e.g., less than approximately 6 nm, which improves process window for subsequent Mx+1 module builds. | 2017-12-21 |
20170365505 | FILLING PROCESSES - A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles. | 2017-12-21 |
20170365506 | METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION - A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure. | 2017-12-21 |
20170365507 | Field Emission Devices and Methods of Making Thereof - In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device. | 2017-12-21 |
20170365508 | Via Patterning Using Multiple Photo Multiple Etch - A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer. | 2017-12-21 |
20170365509 | DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION - Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method. | 2017-12-21 |
20170365510 | METHOD OF FORMING OPENING PATTERN - A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask. | 2017-12-21 |
20170365511 | ARTICLES INCLUDING ULTRA LOW DIELECTRIC LAYERS - An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids. | 2017-12-21 |
20170365512 | HYDROGENATION AND NITRIDIZATION PROCESSES FOR REDUCING OXYGEN CONTENT IN A FILM - Embodiments described herein generally relate to a sequential hydrogenation and nitridization process for reducing interfacial and bulk O atoms in a conductive structure in a semiconductor device. A hydrogenation and plasma nitridization process is performed on a metal nitride layer in a conductive structure prior to deposition of a second metal layer, thereby reducing interfacial oxygen atoms formed on a surface of the metal nitride and oxygen atoms present in the bulk metal layers of the conductive structure. As a result, adhesion of the second metal layer to the metal nitride layer is improved and the electrical resistance of the contact structure is reduced. | 2017-12-21 |
20170365513 | TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill. | 2017-12-21 |
20170365514 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer. | 2017-12-21 |
20170365515 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body. | 2017-12-21 |
20170365516 | Methods for Forming a Semiconductor Device and Semiconductor Devices - A method for forming a semiconductor device includes forming a plurality of non-semiconductor material portions at a first side of a semiconductor substrate; forming semiconductor material on the plurality of non-semiconductor material portions to bury the plurality of non-semiconductor material portions within semiconductor material; removing at least a portion of the semiconductor substrate from a second side of the semiconductor substrate to uncover the plurality of non-semiconductor material portions at a backside of the semiconductor device; and forming a rough surface at the backside of the semiconductor device by removing at least a subset of the plurality of non-semiconductor material portions while at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions remains or by removing at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions while the plurality of non-semiconductor material portions remain. | 2017-12-21 |
20170365517 | Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation - A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die. | 2017-12-21 |
20170365518 | SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS - A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal. | 2017-12-21 |
20170365519 | METHOD OF PROCESSING A WAFER AND WAFER PROCESSING SYSTEM - A wafer has a device area on one side with a plurality of devices partitioned by a plurality of division lines. Either side of the wafer is attached to an adhesive tape supported by a first annular frame. A modified region is formed in the wafer along the division lines by a laser. The wafer is placed on a support member whose outer diameter is smaller than an inner diameter of the first annular frame. After applying the laser beam, the adhesive tape is expanded thereby dividing the wafer along the division lines. A second annular frame is attached to a portion of the expanded adhesive tape. An inner diameter of the second annular frame is smaller than the outer diameter of the support member and smaller than the inner diameter of the first annular frame. | 2017-12-21 |
20170365520 | Method for Producing an Integrated Heterojunction Semiconductor Device - A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface. | 2017-12-21 |
20170365521 | SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES - A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material. | 2017-12-21 |
20170365522 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - An integrated circuit device includes: a first fin-type active region in a first area of a substrate, the first fin-type active region having a first recess filled with a first source/drain region; a first device isolation layer covering both lower sidewalls of the first fin-type active region; a second fin-type active region in a second area of the substrate, the second fin-type active region having a second recess filled with a second source/drain region; a second device isolation layer covering both lower sidewalls of the second fin-type active region; and a fin insulating spacer on the first device isolation layer, the fin insulating spacer covering a sidewall of the first fin-type active region under the first source/drain region. | 2017-12-21 |
20170365523 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern. | 2017-12-21 |
20170365524 | Nano Wire Structure and Method for Fabricating the Same - A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings. | 2017-12-21 |
20170365525 | METHOD AND STRUCTURE TO ENABLE DUAL CHANNEL FIN CRITICAL DIMENSION CONTROL - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins. | 2017-12-21 |
20170365526 | VERTICAL FIN FIELD EFFECT TRANSISTOR (V-FINFET), SEMICONDUCTOR DEVICE HAVING V-FINFET AND METHOD OF FABRICATING V-FINFET - A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode | 2017-12-21 |
20170365527 | TRANSISTOR, SEMICONDUCTOR STRUCTURE, AND FABRICATION METHOD THEREOF - A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation. | 2017-12-21 |
20170365528 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode. | 2017-12-21 |
20170365529 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR - An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel. | 2017-12-21 |
20170365530 | METHOD OF PRODUCING A FUNCTIONAL INLAY AND INLA PRODUCED BY THE METHOD - The method of manufacturing a functional inlay, comprises at least the steps of: (1) providing a substrate ( | 2017-12-21 |
20170365531 | WAFER PROCESSING EQUIPMENT HAVING CAPACITIVE MICRO SENSORS - Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a particle monitoring device for particle detection includes several capacitive micro sensors mounted on a wafer substrate to detect particles under all pressure regimes, e.g., under vacuum conditions. In an embodiment, one or more capacitive micro sensors is mounted on a wafer processing tool to measure material deposition and removal rates in real-time during the wafer fabrication process. Other embodiments are also described and claimed. | 2017-12-21 |
20170365532 | INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH - In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time. | 2017-12-21 |
20170365533 | COMPACT HIGH-VOLTAGE SEMICONDUCTOR PACKAGE - There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package. | 2017-12-21 |
20170365534 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE - A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening. | 2017-12-21 |
20170365535 | High Voltage Power Electronics Module For Subsea Applications - The present disclosure relates to a high voltage power electronics module for subsea applications. The power electronics module includes: a baseplate, a power semiconductor chip arranged on the baseplate, and an encapsulation structure arranged on the baseplate and configured to encapsulate the power semiconductor chip, wherein the encapsulation structure is an epoxy having an elastic modulus less in a range of 1 to 20 Giga Pascal, GPa, at room temperature and a coefficient of thermal expansion less than 20 ppm/K. | 2017-12-21 |
20170365536 | Electronic Device - An electronic device includes electronic components and an epoxy resin portion which seals the electronic components. The electronic device is disposed in a refrigerant which cools the electronic components. A first layer having a three-dimensional crosslinking structure is formed on a surface or inside of the epoxy resin portion. The first layer is formed such that a length calculated by cube root of an average free volume in the three-dimensional crosslinking structure of the first layer is shorter than a length of the longest side of molecules forming the refrigerant. | 2017-12-21 |
20170365537 | THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM - Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film. | 2017-12-21 |
20170365538 | Flexible Graphite Sheet Support Structure and Thermal Management Arrangement - A flexible graphite sheet support structure forms a thermal management arrangement for device having a heat source. The flexible graphite sheet support structure includes first and second spaced apart support members and a flexible graphite sheet secured to the spaced apart support members forming a free standing flex accommodating section that spans between them. Curve retention members having convex curved surfaces are used to keep the flex accommodating section in a bell shaped curve while preventing the flexible graphite sheet from exceeding a minimum bend radius. The thermal management arrangement formed by the flexible graphite sheet support structure enables the flexible graphite sheet to move heat from one support structure to the other while reducing the transmission of vibration between them and allowing relative movement between the spaced apart support structures. | 2017-12-21 |
20170365539 | Semiconductor Packages and Methods of Fabrication Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad. | 2017-12-21 |
20170365540 | PACKAGE STRUCTURE - A chip packaging structure includes a flexible circuit board, a first built-up structure, a second built-up structure, and a first solder resist layer. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer. The first dielectric layer includes a first conductive pattern, a bearing layer opposite to the first conductive pattern and corresponding to the laminated area. The first built-up structure is located on the first conductive pattern and corresponds to the laminated area, and includes a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern. The second built-up structure is located on the bearing layer and corresponds to the laminated area, and includes a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern. The first solder resist layer covers the second conductive pattern. | 2017-12-21 |
20170365541 | POWER MODULE - A power module (10) having a leadframe (20), a power semiconductor (30) arranged on the leadframe (20), a base plate (40) for dispersing heat generated by the power semiconductor (30) and a potting compound (50) surrounding the leadframe (20) and the power semiconductor (30), that physically connects the power semiconductor (30) and/or the leadframe (20) to the base plate (40). | 2017-12-21 |
20170365542 | SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer. | 2017-12-21 |
20170365543 | SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material. | 2017-12-21 |
20170365544 | SEMICONDUCTOR DEVICE FABRICATED BY FLUX-FREE SOLDERING - A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes placing a first semiconductor chip on a carrier with the first main surface of the first semiconductor chip facing the carrier. A first layer of soft solder material is provided between the first main surface and the carrier. Heat is applied during placing so that a temperature at the first layer of soft solder material is equal to or higher than a melting temperature of the first layer of soft solder material. A second layer of soft solder material is provided between the first contact area and the second main surface. Heat is applied during placing so that a temperature at the second layer of soft solder material is equal to or higher than a melting temperature of the second layer of soft solder material. The first and second layers of soft solder material are cooled to solidify the soft solder materials. | 2017-12-21 |
20170365545 | RESIN BOARD, METHOD OF MANUFACTURING RESIN BOARD, CIRCUIT BOARD, AND METHOD OF MANUFACTURING CIRCUIT BOARD - A resin board includes: a resin layer and a through electrode buried in the resin layer, wherein the through electrode has an electrode surface exposed from a front surface or a back surface of the resin layer and a lateral surface, and the electrode surface and the lateral surface form an obtuse angle. | 2017-12-21 |
20170365546 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer. | 2017-12-21 |
20170365547 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND CONDUCTIVE POST - A semiconductor device comprises a semiconductor element | 2017-12-21 |