| 51st week of 2012 patent applcation highlights part 21 |
| Patent application number | Title | Published |
|---|
| 20120319695 | CAR BATTERY SYSTEM - The car battery system of the present invention is provided with a battery block | 2012-12-20 |
| 20120319696 | DEVICE HAVING CAPACITIVE LOADS AND ABNORMALITY DETECTING METHOD THEREOF - In a device having capacitive loads in which a plurality of capacitive loads are connected in parallel, power is supplied from an AC power source to a load group comprising the plurality of capacitive loads, the load group is divided into a plurality of small load groups, and a current detecting sensor for detecting a current which flows in at least one small load group at a side which is closer to the load side than a branch point at which the load group is divided into the plurality of small load groups and a current abnormality detecting part for determining an abnormality of a load by a current detecting signal which is detected by the current detecting sensor are equipped. | 2012-12-20 |
| 20120319697 | METHODS FOR PROVIDING PROPER IMPEDANCE MATCHING DURING RADIO-FREQUENCY TESTING - Wireless electronic devices may include a transceiver, an antenna resonating element coupled to the transceiver via a transmission line path, transceiver and antenna impedance matching circuits, and other circuitry. The transceiver and the impedance matching circuits may be formed on a first substrate. The antenna resonating element may be formed using a second substrate. The antenna resonating element may be decoupled from the first substrate during testing. First and second sets of test points may be formed at first and second locations long the transmission line path. During testing, a test probe may mate with the first set of test points, whereas an impedance adjustment circuit that serves to electrically isolate the antenna impedance matching circuit from the transceiver may mate with the second set of test points. The impedance adjustment circuit need not be used if the antenna impedance matching circuit is decoupled from the transceiver during testing. | 2012-12-20 |
| 20120319698 | RIPPLE SPRING AND DIAGNOSTIC METHOD THEREFOR - A ripple spring is provided having one or more conductive layers, and one or more non-conductive layers. The conductive layers and the non-conductive layers are laminated together to form a symmetrical stack of layers. A method is also provided for monitoring the ripple spring. The method includes the steps of providing a ripple spring that holds a winding in place, where the ripple spring is positioned at least partially within a stator slot defined within an electromechanical device. Providing a conductive layer disposed within the ripple spring, and generating signals from the conductive layer, the signals corresponding to at least one aspect of the ripple spring. An analyzing step analyses the signals to determine the at least one aspect of the ripple spring, wherein the at least one aspect facilitates an identification of faults in the ripple spring. | 2012-12-20 |
| 20120319699 | INSULATION DETERIORATION DIAGNOSIS APPARATUS - The invention is related to an insulation deterioration diagnostic apparatus for an electric path connected between an inverter device and an inverter-driven load device, including: a zero-phase current transformer having an annular magnetic core, a magnetizing coil wound around the magnetic core, and a detecting coil wound around the magnetic core, the transformer being for detecting a zero-phase current of an electric path; a magnetization control circuit for supplying an alternating current having a frequency at least twice as high as a drive frequency of the load device to the magnetizing coil to magnetize the magnetic core; and a frequency extracting circuit for extracting a frequency component identical to the drive frequency fd, from the output signal of the detecting coil, whereby precisely measuring a current leaking from an inverter-driven load device over a wide range of frequencies. | 2012-12-20 |
| 20120319700 | SOLENOID-OPERATED VALVE AND METHOD OF MONITORING SAME - A method for monitoring operation of a solenoid valve having an armature and a poppet coupled to the armature includes the steps of energizing a coil in the valve to generate a current signature reflecting current vs. time, detecting a first inflection point in the current signature, wherein the first inflection point occurs when the armature starts to move from one of the open and closed positions toward the other of the open and closed positions, and detecting a second inflection point in the current signature. The second inflection point occurs when the armature moves completely to the other of the open and closed positions. In one embodiment, the first inflection point indicates when the valve begins to open, making it possible to accurately determine the elapsed opening time of the valve. | 2012-12-20 |
| 20120319701 | System and Method of Occupant Detection with a Resonant Frequency - An occupant detection system that includes an electrode arranged proximate to an expected location of an occupant for generating an electric field between the electrode and the occupant proximate thereto. An electrical network coupled to the electrode forms a resonant circuit that includes the occupant as part of the resonant circuit. A controller coupled to the resonant circuit is configured to determine a resonant frequency of the resonant circuit indicative of an occupant presence, and a network signal magnitude at the resonant frequency indicative of a humidity value proximate to the electrode. | 2012-12-20 |
| 20120319702 | GUIDED WAVE CUTOFF SPECTROSCOPY USING A CYLINDRICAL MEASUREMENT CELL - A cylindrical waveguide ( | 2012-12-20 |
| 20120319703 | INSTRUMENT AND METHOD FOR DETECTING PARTIAL ELECTRICAL DISCHARGES - An instrument ( | 2012-12-20 |
| 20120319704 | STACKED SENSOR FOR TESTING A POROUS MEDIUM - A sensor is provided for testing a porous medium. The sensor includes a plurality of porous elements, a number of electrically conductive interface plates which is one greater than the quantity of elements, and the same number of conductors. Each element operates as a discrete variable capacitor, exhibits a different known liquid release curve, and includes a first axial opening. The elements are stacked one on top of another. Each plate includes a second axial opening. The plates are axially distributed within the sensor such that the first and second axial openings combine to form a longitudinal cavity that extends from the sensor's proximal end to its distal end, and each element is sandwiched between a different pair of plates. A distal end of each conductor is attached to a different one of the plates, and a proximal end is routed through the cavity to the sensor's proximal end. | 2012-12-20 |
| 20120319705 | HYBRID THREE-DIMENSIONAL SENSOR ARRAY, IN PARTICULAR FOR MEASURING ELECTROGENIC CELL ASSEMBLIES, AND THE MEASURING ASSEMBLY - The invention relates to a hybrid three-dimensional sensor array, in particular for measuring biological cell assemblies. The sensor array has a plurality of microstructured sensor plates, each having one carrier section on which a plurality of sensor needles are arranged in a comb-like manner, which carry a plurality of electrode surfaces. Furthermore, a plurality of spacer elements are provided, which are fastened between the sensor plates so that both the carrier sections and the sensor needles of adjacent sensor plates are at a distance from each other. The invention further relates to a measuring assembly for measuring electrical activities of biological cell assemblies using such a sensor array. | 2012-12-20 |
| 20120319706 | CAPACITANCE-BASED SYSTEM HEALTH MONITORING SYSTEM, APPARATUS AND METHOD FOR LAYERED STRUCTURE - The present disclosure endeavors to provide an SHM system and method using a conductive material (e.g., CNT) to measure changes in a layered structure. Change in capacitance of a layered structure may be measured over time thereby indicating a change in the structural integrity of the material. The SHM system may be embedded with, or within, the layered structure such that the system is effectively part of the material. Alternatively, it may be external to the layered structure such that the system is a separate device used to measure the capacitance. The SHM system may also localize any changes in a layered structure by using, for example, strips or panels of conductive material on opposite sides of the layered structure being measured. Damage within overlapping portions of the conductive material provides localization capability where varying the size of the strips or panels may be use to vary the sensitivity and resolution of both the locations and size of the defect. | 2012-12-20 |
| 20120319707 | SELF-MONITORING POWER SUPPLY CORD AND OPERATING EQUIPMENT - The invention relates to a power supply cord with at least two conductors N, L for transferring a supply voltage with two protective earths insulated from one another, which at the first end are conductively connected with each other and at the second end there is a measurement device provided for measurement of the resistance of a measuring circuit comprising the PE and measurement conductor P, and wherein in case of exceeding the resistance, a warning signal is output. | 2012-12-20 |
| 20120319708 | TRANSMISSION GEAR POSITION SENSOR USING PRINTED CIRCUIT ELEMENT - A gear position sensor employs a sliding electrical connection between arcuate conductors and flexible wiper arms held on opposite surfaces that rotate relative to each other with the movement of a gear selector shaft. The traces may have multiple segments joined by resistors to provide flexible change in resistance value and resistance range for different applications. | 2012-12-20 |
| 20120319709 | HIGH SPEED CONTROLLABLE LOAD - A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test. | 2012-12-20 |
| 20120319710 | METHOD AND APPARATUS FOR IMPLEMENTING PROBES FOR ELECTRONIC CIRCUIT TESTING - Disclosed is an improved probe having a spring portion which allows effective contact with a device under test without requiring a lower die portion. The probe includes a slot retention and placement portion, which provides for an improved approach for manufacturing arrangements of probes, where the slot retention and placement portions of the probe facilitate precise placement and alignment of the probes while not excessively increasing the cost or complexity of the probes and probe cards. | 2012-12-20 |
| 20120319711 | Probe Head Formation Methods Employing Guide Plate Raising Assembly Mechanism - An assembly includes a lower guide plate having a first plurality of through-holes therein, and an upper guide plate over the lower guide plate. The upper guide plate includes a second plurality of through-holes therein. The assembly further includes a plurality of probe pins. Each of the probe pins is inserted through one of the first plurality of through-holes and one of the second plurality of through-holes. The assembly further includes a plurality of probe pin stoppers, each attached to one of the probe pins, wherein the plurality of probe pin stoppers has lateral sizes greater than lateral sizes of the second plurality of through-holes. The plurality of probe pin stoppers is located over the upper guide plate. | 2012-12-20 |
| 20120319712 | Probe Module With Interleaved Serpentine Test Contacts For Electronic Device Testing - A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught. | 2012-12-20 |
| 20120319713 | AUTOMATIC PROBE CONFIGURATION STATION AND METHOD THEREFOR - A probe system for facilitating the inspection of a device under test. System incorporates a storage rack; a probe bar gantry assembly; a probe assembly configured to electrically mate the device under test; and a robot system for picking the probe assembly from the storage rack and deliver the probe assembly to the probe bar gantry. The robot system is also enabled to pick a probe assembly from the probe bar gantry and deliver the probe assembly to the storage rack. The probe assembly includes a clamping assembly for attaching the probe assembly to the probe bar gantry or the storage rack. The probe assembly may include an array of contact pins configured to mate with conductive pads on the device under test when the probe assembly is installed on the probe bar gantry assembly. | 2012-12-20 |
| 20120319714 | PROBE-ABLE VOLTAGE CONTRAST TEST STRUCTURES - Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices. | 2012-12-20 |
| 20120319715 | PROBE-ABLE VOLTAGE CONTRAST TEST STRUCTURES - Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices. | 2012-12-20 |
| 20120319716 | PROBE-ABLE VOLTAGE CONTRAST TEST STRUCTURES - Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices. | 2012-12-20 |
| 20120319717 | METHOD AND APPARATUS FOR 3D IC TEST - An apparatus comprises a die comprising a plurality of switch/router circuits; and a plurality of additional dies. Each respective one of the plurality of additional dies comprises: a respective network interface, which is electrically coupled to a respective one of the plurality of switch/router circuits; and a respective interconnection test logic, which is electrically coupled to the respective network interface and the interconnection test logic in at least one other one of the plurality of additional dies. | 2012-12-20 |
| 20120319718 | SIGNAL TRANSMISSION APPARATUS AND SEMICONDUCTOR TEST APPARATUS USING THE SAME - The semiconductor test apparatus includes a pin electronics unit. The pin electronics unit includes a driver configured to generate a test signal to be applied to a semiconductor device and a comparator configured to receive a response signal output from the semiconductor device and to convert the response signal into a digital signal. A first line is connected between the driver and a connector to which the external cable is connected. A second line diverges from the connector side of the first line. A probing unit is connected between the first and second lines, and is configured to at least reduce distortion of a signal on the first line to be transmitted to the second line. A divergence point at which the second line diverges from the first line is located outside the pin electronics unit near the connector. | 2012-12-20 |
| 20120319719 | SEMICONDUCTOR DEVICE AND TEST METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device has a first driving circuit inputting first data; a first gate circuit for the first data to pass therethrough; a first holding circuit holding the first data from the first gate circuit; a logic circuit carrying out a logic operation on the first data from the first holding circuit and outputting second data; a second driving circuit for inputting the second data from the logic circuit; a second gate circuit for the second data from the second driving circuit to pass therethrough; a second holding circuit holding the second data from the second gate circuit; and a power supply circuit supplying a first power supply voltage to the first and second gate circuits, the first and second holding circuits and the logic circuit, and supplying a second power supply voltage higher than the first power supply to the first and second driving circuits. | 2012-12-20 |
| 20120319720 | TEST CIRCUIT FOR BIPOLAR JUNCTION TRANSISTOR - A test circuit includes a first test circuit. The first test circuit includes a first light-emitting diode (LED) and a first resistor. An anode of the first LED is connected to a power supply. A cathode of the first LED is connected to a collector of a bipolar junction transistor (BJT) through the first resistor. An emitter of the BJT is grounded. A base of the BJT is connected to the power supply. A type of the BJT can be determined according to status of the first LED. | 2012-12-20 |
| 20120319721 | CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior. | 2012-12-20 |
| 20120319722 | METHOD AND APPARATUS FOR ALTERNATOR STATOR TURN-TO-TURN SHORT DETECTION - A method for detecting whether the stator in a vehicle alternator has a turn-to-turn short circuit. The method includes determining an output current or voltage signal of the alternator, where the output current or voltage signal includes a ripple current frequency as a result of an AC-to-DC conversion. The method determines the speed of the alternator and a current output of the alternator. The method then determines the ripple current frequency of the alternator from the alternator speed, and determines a winding frequency from the ripple current frequency. The method performs an FFT analysis on the voltage and current signal, determines an amplitude of the winding frequency and compares the amplitude of the winding frequency to a predetermined amplitude, where if the difference exceeds a predetermined threshold, a turn-to-turn short circuit is likely occurring. | 2012-12-20 |
| 20120319723 | ELECTRIC MACHINE FOR WHICH THE GROUNDING FUNCTION IS MONITORED AND METHOD - The grounding quality of an electric machine should be better monitored. Therefore, an electric machine is proposed, comprising a stator ( | 2012-12-20 |
| 20120319724 | SYSTEM AND METHODS FOR GENERATING UNCLONABLE SECURITY KEYS IN INTEGRATED CIRCUITS - A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use. | 2012-12-20 |
| 20120319725 | TESTING FOR MULTIPLEXER LOGIC ASSOCIATED WITH A MULTIPLEXED INPUT/OUTPUT PIN - An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux. | 2012-12-20 |
| 20120319726 | TERMINAL RESISTOR APPARATUS - A terminal resistor apparatus includes an input-side switch, an input-side terminal resistor, an output-side switch, and an output-side terminal resistor. When a plurality of the terminal resistor apparatus are connected, the input-side switch of the first terminal resistor apparatus will be conducted so that the input-side terminal resistor will be connected, but the output-side switch will not be conducted so that the output-side terminal resistor will not be connected. The input-side switch of the last terminal resistor apparatus will not be conducted so that the input-side terminal resistor will not be connected, but the output-side switch will be conducted so that the output-side terminal resistor will be connected. The input-side switches of the other terminal resistor apparatus will not be conducted so that the input-side terminal resistors will not be connected, and the output-side switches will not be conducted so that the output-side terminal resistors will not be connected. | 2012-12-20 |
| 20120319727 | CONFIGURABLE REFERENCE CIRCUIT FOR LOGIC GATES - This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the reference current the magnetic logic device may be caused to implement different combinational logic functions. | 2012-12-20 |
| 20120319728 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer. | 2012-12-20 |
| 20120319729 | FIELD PROGRAMMABLE GATE ARRAY - A field programmable gate array is disclosed, which comprises at least one logic element having at least one switching element. The switching element comprises a static support element and a movable connecting element for providing a non-volatile electrical connection. | 2012-12-20 |
| 20120319730 | SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE - Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block. | 2012-12-20 |
| 20120319731 | INTEGRATED CIRCUIT DEVICE COMPRISING CLOCK GATING CIRCUITRY, ELECTRONIC DEVICE AND METHOD FOR DYNAMICALLY CONFIGURING CLOCK GATING - An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled. | 2012-12-20 |
| 20120319732 | MAGNETIC LOGIC DEVICE - The present disclosure provides for magnetic logic devices and methods of operating such a device. In one embodiment, the device includes a bottom electrode configured to receive a first input current and a second input current, a bottom magnetic layer disposed over the bottom electrode, a nonmagnetic layer disposed over the bottom magnetic layer, a top magnetic layer disposed over the nonmagnetic layer, and a top electrode disposed over the top magnetic layer, the top electrode and the bottom electrode configured to provide an output voltage which is dependent on the first and second input currents and which follows an AND gate logic or an OR gate logic. | 2012-12-20 |
| 20120319733 | SEMICONDUCTOR DEVICE - A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time. | 2012-12-20 |
| 20120319734 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A PHASED-LOCKED LOOP CIRCUIT - A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled. | 2012-12-20 |
| 20120319735 | CIRCUIT AND METHOD FOR DETERMINING COMPARATOR OFFSETS OF ELECTRONIC DEVICES - A device includes a comparator, and a selection circuit coupled to the inputs of the comparator. The selection circuit receives reference voltages and a variable voltage. In a normal operation mode, the selection circuit provides the variable voltage and a selected reference voltage to the comparator and the comparator provides an indication based on the variable voltage. In a test mode, the selection circuit provides a first selected reference voltage and a second selected reference voltage to the comparator for determining a switching offset voltage of the comparator. | 2012-12-20 |
| 20120319736 | Comparator and method with adjustable speed and power consumption - A comparator ( | 2012-12-20 |
| 20120319737 | INVERTER AND SWITCHING CIRCUIT - Disclosed herein are an inverter and an antenna circuit. The inverter that receives control signals, inverts the control signals including a first control signal, a second control signal, and a third control signal, and outputs the inverted control signals, includes: a first MOS transistor having a gate to which a first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which a third control signal is applied and a source to which a second control signal is applied; and a third MOS transistor having a gate to which a second control signal is applied and a source to which a third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal. | 2012-12-20 |
| 20120319738 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A frequency-voltage converting circuit | 2012-12-20 |
| 20120319739 | SEMICONDUCTOR DEVICE SUPPLYING CHARGING CURRENT TO ELEMENT TO BE CHARGED - A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer. | 2012-12-20 |
| 20120319740 | Method and Circuit for Driving an Electronic Switch - Disclosed is an electronic circuit. The electronic circuit includes a transistor having a control terminal to receive a drive signal, and a load path between a first and a second load terminal. A voltage protection circuit is coupled to the transistor, has a control input, is configured to assume one of an activated state and a deactivated state as an operation state dependent on a control signal received at the control input, and is configured to limit a voltage between the load terminals or between one of the load terminals and the control terminal. A control circuit is coupled to the control input of the voltage protection circuit and is configured to deactivate the voltage protection circuit dependent on at least one operation parameter of the transistor and when a voltage across the load path or a load current through the load path is other than zero. | 2012-12-20 |
| 20120319741 | REDUCED CROSSTALK WIRING DELAY EFFECTS THROUGH THE USE OF A CHECKERBOARD PATTERN OF INVERTING AND NONINVERTING REPEATERS - A buffer arrangement in wire lines in which at least one aggressor wire line is located adjacent and substantially parallel to a victim wire line has a plurality of alternately arranged inverting and noninverting buffers. The alternately arranged in a checkerboard pattern in which noninverting and inverting buffers are located in the victim wire line in locations corresponding to locations of the inverting and noninverting buffers in the at least one aggressor wire line. | 2012-12-20 |
| 20120319742 | SYSTEMS AND METHODS FOR DRIVING A BIPOLAR JUNCTION TRANSISTOR BY ADJUSTING BASE CURRENT WITH TIME - System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period. | 2012-12-20 |
| 20120319743 | SIGNAL TRANSMITTING APPARATUS - A signal transmitting apparatus that may suppress generation of a noise voltage attributable to a common mode voltage is provided. A transistor P1 is connected between a first terminal of a sending coil and a power supply voltage. A transistor N1 is connected between the first terminal and a ground voltage. A transistor P2 is connected between a second terminal of the sending coil wand the power supply voltage. A transistor N2 is connected between the second terminal and the ground voltage. In a period-PE1, a coil current flowing in a positive direction is generated by turning on the transistors P1 and N2 and turning off the transistors P2 and N1, and then the transistor N1 is turned on in response to turning off the transistor P1. In a period PE2, a coil current flowing in a negative direction is generated by turning off the transistors P1 and N2 and turning on the transistors P2 and N1, and then the transistor N2 is turned on in response to turning off the transistor P2. | 2012-12-20 |
| 20120319744 | METHOD AND APPARATUS FOR SIMPLIFYING THE CONTROL OF A SWITCH - A half bridge converter includes a transformer with a high side switch coupled between a first input terminal and a primary winding of the transformer. A low side switch is coupled between a second input terminal and the primary winding. A first control circuit is coupled to the first input terminal and the primary winding to control the high side switch in response to a rate of voltage change with respect to time across the high side switch while the high side switch is off. A second control circuit coupled to the primary winding and the second input terminal to control the low side switch in response to a rate of voltage change with respect to time across the low side switch while the low side switch is off. | 2012-12-20 |
| 20120319745 | FREQUENCY MULTIPLIER OSCILLATION CIRCUIT AND METHOD OF MULTIPLYING FUNDAMENTAL WAVE - A frequency multiplier oscillation circuit (and a method of multiplying a fundamental wave) includes an oscillation unit, a multiplication unit, and a fundamental wave component removal unit. The oscillation unit outputs a fundamental wave. The multiplication unit multiplies the fundamental wave to output the multiplied wave. The fundamental wave component removal unit cancels a fundamental wave component included in the multiplied wave based on the fundamental wave that is output from the oscillation unit to output the multiplied wave to an output terminal. | 2012-12-20 |
| 20120319746 | ARRAY ANTENNA APPARATUS - An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal. | 2012-12-20 |
| 20120319747 | PHASE-LOCKED LOOP LOCK DETECT - Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time. | 2012-12-20 |
| 20120319748 | DIGITAL PHASE LOCKED LOOP SYSTEM AND METHOD - A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter. | 2012-12-20 |
| 20120319749 | DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT - One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal. | 2012-12-20 |
| 20120319750 | MULTI-PART CLOCK MANAGEMENT - An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components. | 2012-12-20 |
| 20120319751 | HIGH RESOLUTION CAPTURE - The high resolution capture (HRCAP) of this invention enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock. | 2012-12-20 |
| 20120319752 | LOOK-UP TABLES FOR DELAY CIRCUITRY IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) CHIPSETS - A method, new use for Look-Up Tables (LUTs), and a Field Programmable Gate Array (FPGA) chipset are provided for delaying data signals. The FPGA comprises an input and a set of LUTs operationally connected to and receiving from the interface a data signal and a clock signal. The set of LUTs delay the data signal by a delay so that a corresponding first delayed data signal output from the set of LUTs is so synchronized with the clock signal for appropriate sampling of the delayed data signal to be performed by the FPGA chipset. A process of manufacturing of the FPGA chipset comprises calculating a delay for delaying and synchronising the data signal with a clock signal to meet requirements of the chipset, calculating a number of LUTs for delaying the data signal, and implementing in a data path of the data signal the number of LUTs. | 2012-12-20 |
| 20120319753 | INTEGRATED CIRCUIT PULSE GENERATORS - An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state. | 2012-12-20 |
| 20120319754 | TRANSISTOR SWITCH CONTROL CIRCUIT - A synchronous driving circuit in the arts may cause a short through pheromone when a duty cycle of a duty cycle control signal is too short. The present invention sets a delay time with a suitable period when the duty cycle of the duty cycle control signal is too short to avoid the short through phenomenon. | 2012-12-20 |
| 20120319755 | HIGH LINEAR VOLTAGE VARIABLE ATTENUATOR (VVA) - An apparatus comprising one or more series transistor network elements and a plurality of shunt circuits. The series transistor network may be configured to generate an output signal in response to (i) an input signal, (ii) a first bias signal, and (iii) a plurality of variable impedances. The plurality of shunt circuits may each be configured to generate a respective one of the variable impedances in response to a second bias signal. The output signal may have an attenuation that is equal to or less than the input power. The amount of the attenuation may be controlled by the first bias signal and the second bias signal. The series transistor elements and the plurality of shunt circuits may be configured as two or more transistors each having two or more gates. | 2012-12-20 |
| 20120319756 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 2012-12-20 |
| 20120319757 | SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODES PENETRATING THROUGH SEMICONDUCTOR CHIP - Disclosed herein is a semiconductor device that includes: a first circuit formed on a chip having a main surface; first to n | 2012-12-20 |
| 20120319758 | BI-FET CASCODE POWER SWITCH - Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device. | 2012-12-20 |
| 20120319759 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION CONTROL METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - According to an embodiment, a semiconductor integrated circuit has a control section configured to execute feedback control by regulating a control parameter of a circuit section based on a temperature or an operation speed of the circuit section so that the temperature is stabilized, a history register configured to store historical data including first historical data that are time series data of the temperature, and second historical data that are time series data of the control parameter, and effectiveness determining section configured to determine effectiveness of the feedback control from the historical data. | 2012-12-20 |
| 20120319760 | RF PROXIMITY SENSOR - A sensor has a strip resonator filter that energizes an emitter patch which emits an electric field out from the strip resonator filter (away from the strip resonator filter). The capacitance of the filter, or specifically the coupling capacitance and radiation pattern of the slotted patch, is altered when an object such as a finger is near the sensor. Resulting changes in a signal outputted by the filter can be used to determine how close the object is to the sensor. The strip resonator filter may be a half wavelength strip resonator coupled filter having three separate strips. The patch may have a slot and two accompanying strips. An arrangement of multiple sensors may detect the position of an object in two or three dimensions. | 2012-12-20 |
| 20120319761 | METHOD FOR OPERATING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction. | 2012-12-20 |
| 20120319762 | POWER SWITCH - A method for switching between first and second voltages is provided. Initially, a first voltage is provided from a first input terminal to an output terminal through a first MOS transistor, and the first MOS transistor is deactivated. A back-gate of a second MOS transistor is shorted to the output terminal in response to the deactivation of the first MOS transistor and after a settling interval, and the second MOS transistor is activated while its back-gate is shorted to the terminal so as to provide a second voltage from a second input terminal to the output terminal. | 2012-12-20 |
| 20120319763 | BANDGAP CIRCUIT AND START CIRCUIT THEREOF - A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between the load unit and a ground, and receives a node voltage from the reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to a reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between the control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage. | 2012-12-20 |
| 20120319764 | Energy Borrowing to Reduce System Voltage Drop - An integrated circuit (IC) includes a first section having a sinking component sinking excessive current. A second section includes at least one sourcing component that, in operation, stores energy. A structure is provided to provide the stored energy from the at least one sourcing component to the sinking component, the stored energy being utilized by a load component included within the second section. | 2012-12-20 |
| 20120319765 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SUPPLYING POWER TO THE SAME - A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground. | 2012-12-20 |
| 20120319766 | SIGNAL OUTPUT CIRCUIT - In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal. | 2012-12-20 |
| 20120319767 | Single-Ended-To-Differential Filter Using Common Mode Feedback - A filter including common mode feedback can provide single-ended to differential-ended conversion with minimum loss of performance. | 2012-12-20 |
| 20120319768 | Complementary Darlington Emitter Follower with Improved Switching Speed and Improved Cross-over Control and Increased Output Voltage - In one embodiment, an apparatus includes a first transistor where the base of the first transistor is coupled to an input node. A second transistor is provided where the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to an output node. A third transistor is provided where the base of the third transistor is coupled to the input node. A fourth transistor is provided where the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output node and the base of the second transistor is coupled to the base of the fourth transistor. The base of the second transistor is coupled to the base of the fourth transistor through a shorting link. | 2012-12-20 |
| 20120319769 | COMBINER-LESS MULTIPLE INPUT SINGLE OUTPUT (MISO) AMPLIFICATION WITH BLENDED CONTROL - Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function. | 2012-12-20 |
| 20120319770 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier. | 2012-12-20 |
| 20120319771 | APPARATUS FOR CALIBRATING AMPLITUDE AND PHASE ERRORS, MULTIPORT AMPLIFIER INCLUDING THE SAME, AND METHOD OF AMPLIFYING THE MULTIPORT AMPLIFIER - A multiport amplifier modulates a reference quadrature phase shift keying (QPSK) signal using an input RF signal to an input hybrid network, generates a plurality of binary phase shift keying (BPSK) signals by demodulating RF signals that are amplified by a plurality of power amplifiers, detects an amplitude error and a phase error of two corresponding amplified RF signals by comparing a QPSK signal that is generated by coupling two RF signals having a phase difference of 90° among the plurality of BPSK signals with a reference QPSK signal, and compensates the detected amplitude error and phase error. | 2012-12-20 |
| 20120319772 | FLEXIBLE MULTI-CHANNEL AMPLIFIERS VIA WAVEFRONT MUXING TECHNIQUES - This invention aims to present a smart and dynamic power amplifier module that features both power combining and power sharing capabilities. The proposed flexible power amplifier (PA) module consists of a pre-processor, N PAs, and a post-processor. The pre-processor is an M-to-N wavefront (WF) multiplexer (muxer), while the post processor is a N-to-M WF de-multiplexer (demuxer), where N≧M≧2. Multiple independent signals can be concurrently amplified by a proposed multi-channel PA module with a fixed total power output, while individual signal channel outputs feature different power intensities with no signal couplings among the individual signals. In addition to basic configurations, some modules can be configured to feature both functions of parallel power amplifiers and also as M-to-M switches. Other programmable features include configurations of power combining and power redistribution functions with a prescribed amplitude and phase distributions, as well as high power PA with a linearizer. | 2012-12-20 |
| 20120319773 | POWER GENERATING CIRCUIT AND SWITCHING CIRCUIT - Disclosed herein is a power generating circuit including a first transistor in which a second control signal is applied to a control terminal and a first control signal is applied to one end, and which has the other end connected to an output terminal, a second transistor in which the first control signal is applied to a control terminal and the second control signal is applied to one end, and which has the other end connected to the output terminal a third transistor in which one of the first and the second control signals is applied to a control terminal and which has one end grounded, and a fourth transistor in which the other one thereof is applied to a control terminal and which has one end connected to the other end of the third transistor and the other end connected to the output terminal. | 2012-12-20 |
| 20120319774 | MULTI-STAGE GAIN CONTROL IN RECEIVERS AND OTHER CIRCUITS - Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively. | 2012-12-20 |
| 20120319775 | AUTOMATIC GAIN CONTROL APPARATUS AND METHOD - An automatic gain control apparatus for a wireless receiver, including multiple variable gain amplifiers, one variable gain amplifier provided for each one of multiple receive chains and a gain controller to control a gain of the variable gain amplifiers provided for the plurality of receive chains. The gain controller includes multiple output level measurement units to measure an output level of a corresponding receive chain; a common gain determination unit to determine a common gain for each of the variable gain amplifiers based on a statistical value obtained from the output levels; multiple adjusted gain determination units, each adjusted gain determination unit determining an adjusted gain independently for each variable gain amplifier within a range narrower than the range of the common; and a gain setting unit to set a gain to each of the variable gain amplifiers based on the common gain and the adjusted gain. | 2012-12-20 |
| 20120319776 | DC VOLTAGE ERROR PROTECTION CIRCUIT - This document discusses among other things apparatus and methods for protecting circuit elements from harmful voltages. In an example, an apparatus can include an amplifier configured to receive an input signal and to provide an estimate of a first output signal, a peak detector to receive the estimate and to generate a comparison signal that is active when the amplified input signal exceeds a threshold value, and a timer configured to activate a second output signal if the comparison signal is active for at least a selected time period. The timer can include a first digital input and the selected time period can be set using a state of the first digital input. | 2012-12-20 |
| 20120319777 | Method and Apparatus for Biasing Rail to Rail DMOS Amplifier Output Stage - An amplifier comprises: an input stage for receiving incoming signals; a high gain stage coupled to the input stage and providing driving signals in response to the incoming signals to an output driver stage; and an output terminal coupled to the output driver stage. The output driver stage comprises a high side driver circuit having a first terminal receiving a first driving signal pdrive from the high gain stage, a second terminal coupled VDD through a first voltage drop, and a third terminal coupled to the output terminal of the amplifier. | 2012-12-20 |
| 20120319778 | SEMICONDUCTOR POWER AMPLIFIER - A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes ; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof. | 2012-12-20 |
| 20120319779 | TRANSFORMER AND CMOS POWER AMPLIFIER INCLUDING THE SAME - Disclosed herein is a transformer including: a primary coil formed of a first conductor having a predetermined length and including a first end and second end for receiving a signal, wherein the first conductor is formed as a first loop; and a secondary coil that is coupled to the primary coil in an electromagnetic coupling, and is formed of a second conductor having a predetermined length and including a first end and a second end for outputting a signal, wherein the second conductor is formed as a second loop, wherein the primary coil and the secondary coil are stacked while crossing each other. Accordingly, power transformer efficiency may be increased. | 2012-12-20 |
| 20120319780 | WIDEBAND DOHERTY AMPLIFIER CIRCUIT HAVING A CONSTANT IMPEDANCE COMBINER - A three way wideband Doherty amplifier circuit includes a first peaking amplifier operable to turn on at a first power level, a second peaking amplifier operable to turn on at a second power level below the first power level and a main power amplifier operable to turn on at all power levels. The main power amplifier has a high impedance load modulated state when the first and second peaking amplifiers are turned off. The three way wideband Doherty amplifier circuit further includes a constant impedance combiner connected to an output of each amplifier. The constant impedance combiner has a characteristic impedance which matches the impedance of the main amplifier in the high impedance load modulated state with or without an output matching device connecting the main amplifier output to the constant impedance combiner, as viewed from the output of the main amplifier. | 2012-12-20 |
| 20120319781 | Receiver Circuits for Differential and Single-Ended Signals - Receiver circuits for differential and single-ended signals are disclosed. In some embodiments, a receiver may include a first amplifier configured to receive a first signal of a differential pair of signals at a first input and a second signal of the differential pair of signals at a second input when operating in differential mode. The receiver may also include a second amplifier coupled to the first amplifier, where the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input when operating in single-ended mode. In some embodiments, several receivers may be used, for example, to process a differential clock signal and one or more single-ended data signals referenced to the clock signal and/or differential data signals referenced to a single-ended clock signal. In some embodiments, the delays of each signal propagating through each respective receiver may be independently adjusted. | 2012-12-20 |
| 20120319782 | CLASS E POWER AMPLIFIER - The present invention includes a class-E power amplifier, comprising a driver stage (DS) including a first power amplifier with transistors, to which an input signal is inputted; a main stage (MS), including a second power amplifier with transistors, whose input is connected to the output of the DS; and a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit. In accordance with the present invention, as the voltage stress is reduced on the CMOS class-E power amplifier, the application of the high power supply voltage may be allowed and therefore the load impedance may be high while the same efficiency is maintained. | 2012-12-20 |
| 20120319783 | Inductance Enhanced Rotary Traveling Wave Oscillator Circuit and Method - A plurality of inductance enhanced interweaved rotary traveling wave oscillators (RTWO) is disclosed. Portions of the transmission line conductors are increased in length and run in parallel. Because the currents in these portions travel in the same direction, the inductance of these inductors is increased. By controlling the length of the transmission line conductors in these areas compared to the lengths where the currents in the oscillators travel in opposite directions, the overall impedance of the oscillators can be increased. Increased impedance leads to lower power and lower phase noise for the oscillators. Additionally, the interweaved oscillators are phase-locked to each other. | 2012-12-20 |
| 20120319784 | IR-UWB TRANSMITTER - A generator of very short pulses where a cascade of inverters of arbitrary length characterized in that said inverters are adapted to produce pulses on their power supply line instead of their usual output. | 2012-12-20 |
| 20120319785 | QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR AND MAGNETIC SENSOR - A quantum interference device causing electromagnetically induced transparency in an alkali metal atom includes: a light source generating first and second resonant lights with frequency differences Δω; a magnetic field generator applying a magnetic field to the atom; a light detector detecting intensities of the first and second resonant lights passing through the atom; and a controller causing a frequency difference between specified first and second resonant lights to equal a frequency difference corresponding to an energy difference between two ground levels of the atom based on the detected light. The controller causes the frequency Δω or magnetic field intensity to satisfy 2×δ×n=Δω or Δω×n=2×δ. The frequency δ corresponds to an energy difference between two Zeeman split levels differentiated by one magnetic quantum number and generated in the two ground levels of the atom by energy splitting. | 2012-12-20 |
| 20120319786 | AUTOCONFIGURABLE PHASE-LOCKED LOOP WHICH AUTOMATICALLY MAINTAINS A CONSTANT DAMPING FACTOR AND ADJUSTS THE LOOP BANDWIDTH TO A CONSTANT RATIO OF THE REFERENCE FREQUENCY - A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal. | 2012-12-20 |
| 20120319787 | VOLTAGE CONTROLLED OSCILLATOR HAVING A RESONATOR CIRCUIT WITH A PHASE NOISE FILTER - An oscillator circuit is provided for generating an oscillating signal. The oscillator circuit includes a transistor circuit, a resonator circuit, and first and second transmission line open stubs. The transistor circuit is coupled to a first node and a second node of the oscillator circuit. The transistor circuit is for facilitating oscillation of the oscillating signal. The resonator circuit is coupled to the first node and the second node, and includes an inductance and a capacitance. The first and second transmission line open stubs are coupled to the first and second nodes, respectively. The first and second transmission line open stubs have a length substantially equal to a quarter wavelength of a second harmonic of the oscillating signal, and are for removing the second harmonic from the oscillating signal. In another embodiment, first and second half wave AC shorted stubs are used to remove the second harmonic from the oscillating signal. | 2012-12-20 |
| 20120319788 | RELAXATION OSCILLATOR WITH LOW POWER CONSUMPTION - A relaxation oscillator for generating oscillator signal includes a ramp voltage generating circuit, a reference voltage generating circuit, a reference voltage switching circuit, and a digital logic circuit. The reference voltage generating circuit generates one or more reference voltages and the ramp voltage generating circuit generates one or more ramp voltages. The ramp voltages are compared with each of the reference voltages by sequentially switching the reference voltages using a reference voltage switching signal generated by the reference voltage switching circuit. The oscillator signal is generated by the digital logic circuit based on the results of the comparisons. | 2012-12-20 |
| 20120319789 | RELAXATION OSCILLATOR CIRCUIT WITH REDUCED SENSITIVITY OF OSCILLATION FREQUENCY TO COMPARATOR DELAY VARIATION - A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor. | 2012-12-20 |
| 20120319790 | MEMS RESONATOR - In order to provide a MEMS resonator having a higher Q factor, by suppressing losses in high-frequency signals due to barriers of thin-film lamination portions, in cases where there exist junction interfaces (barriers), such as pn junctions, in AC-current input/output lines for a vibrator ( | 2012-12-20 |
| 20120319791 | System and Method for Improved Start-Up of Self-Oscillating Electro-Mechanical Surgical Devices - An oscillating circuit for determining a resonant frequency of an electro-mechanical oscillating device and for driving the electro-mechanical oscillating device at the determined resonant frequency includes a driving circuit and a start-up, impetus injection circuit. The driving circuit is configured to receive one or more reference signals and further configured to provide a driving signal related to the reference signals to the electro-mechanical oscillating device. The start-up, impetus injection circuit is operably coupled to the electro-mechanical oscillating device and configured to selectively provide a start-up excitation signal to the electro-mechanical oscillation device. The start-up, impetus injection circuit is activated upon start-up of the oscillating circuit to drive the electro-mechanical oscillation device and the driving circuit determines a resonant frequency by measuring a parameter related to the resonant frequency of the electro-mechanical oscillating device. | 2012-12-20 |
| 20120319792 | PIEZOELECTRIC DEVICE AND FABRICATING METHOD THEREOF - A piezoelectric device and a fabricating method thereof are provided. Variation of output frequency is suppressed by forming an organic resin to protect an IC chip that is mounted in a cavity of a container body, and damage that may occur to the IC chip during the mounting process is prevented. The piezoelectric device includes a container body, a crystal resonator, an IC chip and a cover body. A surface of the IC chip, which is a mounting surface for mounting to the container body, has bumps thereon for connecting to terminal pads of a circuit wiring pattern configured on a bottom surface of a bottom cavity of the container body, and the other surface of the IC chip has an insulating protective sheet adhered and fixed thereon. | 2012-12-20 |
| 20120319793 | OSCILLATION CIRCUIT - There is provided an oscillation circuit including: a band-gap circuit that outputs an output voltage adjusted for temperature dependency so as to give a constant output voltage independent of temperature; a voltage-current conversion circuit including a first variable resistor, the voltage-current conversion circuit converting an output voltage output from the band-gap circuit into an output current corresponding to the resistance of the first variable resistor and outputting a bias current based on the converted output current; and a CR oscillation circuit including a second variable resistor, a capacitor and a comparator section, the CR oscillation circuit oscillating with an oscillation frequency based on the resistance of the second variable resistor and the capacitance value of the capacitor, and the CR oscillation circuit operating according to the amperage of the bias current the comparator section has input from the voltage-current conversion circuit. | 2012-12-20 |
| 20120319794 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 2012-12-20 |
