51st week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120319195 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material. | 2012-12-20 |
20120319196 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region. | 2012-12-20 |
20120319197 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 2012-12-20 |
20120319198 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench. | 2012-12-20 |
20120319199 | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps. | 2012-12-20 |
20120319200 | MONOLITHICALLY INTEGRATED CIRCUIT - A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement. | 2012-12-20 |
20120319201 | SEMICONDUCTOR DEVICES HAVING VERTICAL DEVICE AND NON-VERTICAL DEVICE AND METHODS OF FORMING THE SAME - In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate. | 2012-12-20 |
20120319202 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate having a device region; a gate, which is located on a surface of the substrate; a second conductive type source and a second conductive type drain in the device region at different sides of the gate respectively; and a second conductive type drift region, which is located in the device region, between the source and the drain. The gate includes: a conductive layer for receiving a gate voltage; and multiple dielectric layers with different thicknesses, located at different horizontal positions. From cross-section view, each dielectric layer is between the conductive layer and the substrate, and the multiple dielectric layers are arranged in an order from thinner to thicker from a side closer to the source to a side closer to the drain. | 2012-12-20 |
20120319203 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant. | 2012-12-20 |
20120319204 | Triggerable Bidirectional Semiconductor Device - A triggerable bidirectional semiconductor device has two terminals and at least one gate. The device comprises, within a layer of silicon on insulator, a central semiconductor zone incorporating the at least one gate and comprising a central region having a first conductivity type, two intermediate regions having a second conductivity type respectively arranged on either side of and in contact with the central region, two semiconductor end zones respectively arranged on either side of the central zone, each end zone comprising two end regions having opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device. | 2012-12-20 |
20120319205 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FILL ASPECT RATIO IN REPLACEMENT GATE TECHNOLOGY - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity. | 2012-12-20 |
20120319206 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon. | 2012-12-20 |
20120319207 | SEMICONDUCTOR DEVICE WITH THRESHOLD VOLTAGE CONTROL AND METHOD OF FABRICATING THE SAME - Semiconductor devices and methods of making semiconductor devices are provided. According to one embodiment, the field effect transistor can contain a semiconductor substrate containing shallow trench isolations; a p-FET and an n-FET; a silicon germanium layer in a recess in the upper surface of the p-FET; a pair of gate dielectrics including a hafnium compound and a rare earth compound disposed on the silicon germanium layer and the upper surface of the n-FET; and a pair of gate electrodes both including the same material disposed on the pair of gate dielectrics. | 2012-12-20 |
20120319208 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage. | 2012-12-20 |
20120319209 | Semiconductor Device Having Mixedly Mounted Components with Common Film Layers and Method of Manufacturing the Same - A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film. | 2012-12-20 |
20120319210 | METHOD FOR 1/F NOISE REDUCTION IN NMOS DEVICES - An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than | 2012-12-20 |
20120319211 | STRAINED CHANNEL FIELD EFFECT TRANSISTOR - The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features. | 2012-12-20 |
20120319212 | SRAM Structure with FinFETs Having Multiple Fins - A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor. | 2012-12-20 |
20120319213 | Semiconductor structure and method for manufacturing the same - The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure. | 2012-12-20 |
20120319214 | STRUCTURE OF METAL GATE AND FABRICATION METHOD THEREOF - A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench. | 2012-12-20 |
20120319215 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, in the present invention a STI is formed first, and then filling is performed to form an active region, to avoid the problem of generation of holes in the STI and improve the device reliability. | 2012-12-20 |
20120319216 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench. | 2012-12-20 |
20120319217 | Semiconductor Devices and Methods of Fabrication Thereof - In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed. | 2012-12-20 |
20120319218 | APPARATUSES FOR GENERATING ELECTRICAL ENERGY - Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties. | 2012-12-20 |
20120319219 | EPITAXIAL SILICON CMOS-MEMS MICROPHONES AND METHOD FOR MANUFACTURING - A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer. | 2012-12-20 |
20120319220 | METHOD OF BONDING SEMICONDUCTOR SUBSTRATE AND MEMS DEVICE - A method of bonding a semiconductor substrate having a substrate | 2012-12-20 |
20120319221 | METHOD AND SYSTEM FOR PROVIDING A MAGNETIC JUNCTION CONFIGURED FOR PRECESSIONAL SWITCHING USING A BIAS STRUCTURE - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a first pinned layer having a first pinned layer magnetization, a first nonmagnetic spacer layer, and a free layer having an easy axis. The first nonmagnetic spacer layer is between the first pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction and such that the free layer employs precessional switching. | 2012-12-20 |
20120319222 | SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND METHOD OF MANUFACTURING POLARIZING ELEMENT - The present invention relates to a solid-state imaging element which is able to provide the solid-state imaging element having a polarizing element having a simple configuration and structure based on a wire grid polarizer technique, a solid-state imaging device, an imaging apparatus, and a method of manufacturing a polarizing element. The solid-state imaging device includes a plurality of solid-state imaging elements | 2012-12-20 |
20120319223 | DIFFUSE OMNI-DIRECTIONAL BACK REFLECTORS AND METHODS OF MANUFACTURING THE SAME - Ultra-high reflectivity is projected for internal reflectors comprised of a metal film and nanostructured transparent conductive oxide (TCO) bi-layer on the back side of a semiconductor device. Oblique-angle deposition can be used to fabricate indium tin oxide (ITO) and other TCO optical thin-film coatings with a porous, columnar nanostructure. The resulting low-n dielectric films can then be employed as part of a conductive omni-directional reflector (ODR) structure capable of achieving high internal reflectivity over a broad spectrum of wavelengths and a wide range of angles. In addition, the dimensions and geometry of the nanostructured, low-n TCO films can be adjusted to enable diffuse reflections via Mie scattering. Diffuse ODR structures enhance the performance of light trapping and light guiding structures in photonic devices. | 2012-12-20 |
20120319224 | IMAGE PICKUP DEVICE AND CAMERA - An object is to provide a solid state image pickup device and a camera which do not worsen a sensor performance in terms of an optical property, a saturated charge amount and the like. A solid state image sensor including a pixel region having a plurality of pixels includes at least a photodiode and an amplifying portion amplifying photocharges outputted from the photodiode in the pixel region, and further includes a well electrode for taking well potential of a well region in which the amplifying portion is arranged. Between the well electrode and the photodiode, no element isolation regions by an insulation film are arranged. Moreover, on the surface of a first semiconductor region in which the photodiode stores the charges, a second semiconductor layer of a conductivity type reverse to that of the first semiconductor region is arranged. | 2012-12-20 |
20120319225 | DYNAMICALLY CONFIGURABLE PHOTOVOLTAIC CELL ARRAY - Embodiments of the present invention relate to photovoltaic cells. Specifically, the present invention relates to photovoltaic (PV) cells configurable for energy conversion and imaging. In a typical embodiment, each photovoltaic cell (PV) in the photovoltaic array is divided into a pixel-based array. Each photovoltaic cell is coupled to a set of switches and the photovoltaic cell is dynamically configured for energy conversion or imaging based on the settings of at least one of the switches. | 2012-12-20 |
20120319226 | FABRICATION OF ROBUST ELECTROTHERMAL MEMS WITH FAST THERMAL RESPONSE - Embodiments of the invention provide robust electrothermal MEMS with fast thermal response. In one embodiment, an electrothermal bimorph actuator is fabricated using aluminum as one bimorph layer and tungsten as the second bimorph layer. The heating element can be the aluminum or the tungsten, or a combination of aluminum and tungsten, thereby providing a resistive heater and reducing deposition steps. Polyimide can be used for thermal isolation of the bimorph actuator and the substrate. For MEMS micromirror designs, the polyimide can also be used for thermal isolation between the bimorph actuator and the micromirror. | 2012-12-20 |
20120319227 | BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 μm, and the anode buffer layer is arranged up to a depth of 18 to 25 μm. The anode buffer layer has a doping concentration between 8.0*10 | 2012-12-20 |
20120319228 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad. | 2012-12-20 |
20120319229 | SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES - Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band. | 2012-12-20 |
20120319230 | ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER - Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed. | 2012-12-20 |
20120319231 | Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 2012-12-20 |
20120319232 | Self-Aligned Dual Depth Isolation and Method of Fabrication - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 2012-12-20 |
20120319233 | BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION - High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces. | 2012-12-20 |
20120319234 | E-FUSE STRUCTURES AND METHODS OF OPERATING AND MANUFACTURING THE SAME - An e-fuse structure includes a first doped region and a second doped region formed in a substrate. The first doped region has a first conductivity type and the second doped region has a second conductivity type different from the first conductivity type. The first and second doped regions contact each other. A conductive pattern is disposed on the first and second doped regions and contacts the first and second doped regions. A first contact plug is disposed on the conductive pattern in an area corresponding to the first doped region, and a second contact plug is disposed on the conductive pattern in an area corresponding to the second doped region. | 2012-12-20 |
20120319235 | SEMICONDUCTOR DEVICE WITH A FUSE FORMED BY A DAMASCENE TECHNIQUE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse. | 2012-12-20 |
20120319236 | INTEGRATED CIRCUIT INDUCTORS WITH INTERTWINED CONDUCTORS - An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance. | 2012-12-20 |
20120319237 | CORNER-ROUNDED STRUCTURES AND METHODS OF MANUFACTURE - Corner-rounded structures and methods of manufacture are provided. The method includes forming at least two conductive wires with rounded corners on a substrate. The method further includes forming a insulator film on the substrate and between the at least two conductive wires with the rounded corners. | 2012-12-20 |
20120319238 | Large Dimension Device and Method of Manufacturing Same in Gate Last Process - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode. | 2012-12-20 |
20120319239 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer. | 2012-12-20 |
20120319240 | High Voltage Resistor With Pin Diode Isolation - Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. | 2012-12-20 |
20120319241 | OFFSET REDUCING RESISTOR CIRCUIT - The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit. | 2012-12-20 |
20120319242 | Dopant Implantation Hardmask for Forming Doped Isolation Regions in Image Sensors - Forming a doped isolation region in a substrate during manufacture of an image sensor. A method of an aspect includes forming a hardmask layer over the substrate, and forming a photoresist layer over the hardmask layer. An opening is formed in the photoresist layer over an intended location of the doped isolation region. An opening is etched in the hardmask layer by exposing the hardmask layer to one or more etchants through the opening. The opening in the hardmask layer may have a width of less than 0.4 micrometers. The doped isolation region may be formed in the substrate beneath the opening in the hardmask layer by performing a dopant implantation that introduces dopant through the opening in the hardmask layer. The method of an aspect may include forming sidewall spacers on sidewalls of the opening in the hardmask layer and using the sidewall spacers as a dopant implantation mask. | 2012-12-20 |
20120319243 | BIPOLAR JUNCTION TRANSISTOR - In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region. | 2012-12-20 |
20120319244 | METHOD FOR MANUFACTURING SEMICONDUCTOR LAYER, METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND SEMICONDUCTOR LAYER FORMING SOLUTION - A method for manufacturing a semiconductor layer according to an embodiment of the present invention comprises preparing a first compound, preparing a second compound, making a semiconductor layer forming solution, and forming a semiconductor layer including a group compound by using this semiconductor layer forming solution. The first compound contains a first chalcogen-element-containing organic compound, a first Lewis base, a I-B group element, and a first III-B group element. The second compound contains an organic ligand and a second III-B group element. The semiconductor layer forming solution contains the first compound, the second compound, and an organic solvent. | 2012-12-20 |
20120319245 | VENTED SUBSTRATE FOR SEMICONDUCTOR DEVICE - A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield. | 2012-12-20 |
20120319246 | IP PROTECTION - Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners. | 2012-12-20 |
20120319247 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MASK MATERIAL - A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed. | 2012-12-20 |
20120319248 | STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS - A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC. | 2012-12-20 |
20120319249 | SEMICONDUCTOR CHIP, SEMICONDUCTOR WAFER AND SEMICONDUCTOR CHIP MANUFACTURING METHOD - The semiconductor chip ( | 2012-12-20 |
20120319250 | BACK-SIDE CONTACT FORMATION - In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer. | 2012-12-20 |
20120319251 | Solder Ball Protection Structure with Thick Polymer Layer - An integrated circuit structure includes a substrate and a metal pad over the substrate. A post-passivation interconnect (PPI) line is connected to the metal pad, wherein the PPI line includes at least a portion over the metal pad. A PPI pad is connected to the PPI line. A polymer layer is over the PPI line and the PPI pad, wherein the polymer layer has a thickness greater than about 30 μm. An under-bump metallurgy (UBM) extends into an opening in the polymer layer and electrically connected to the PPI pad. | 2012-12-20 |
20120319252 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes performing a cycle a predetermined number of times to form a film on a substrate. The cycle includes feeding a first material containing a first element, to be adsorbed on a substrate surface, to a processing chamber where the substrate is accommodated; feeding a second material containing a second element, adsorbed on the substrate surface, to the processing chamber after the adsorption of the first material; feeding a third material containing a third element to the processing chamber, so that the substrate surface is modified; and removing an atmosphere in the processing chamber. A content of the second element in the film is controlled by adjusting an adsorption quantity of the first material and an adsorption quantity of the second material with respect to a saturated adsorption quantity of the first material adsorbed on the substrate surface. | 2012-12-20 |
20120319253 | SEMICONDUCTOR MODULE MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND MANUFACTURING DEVICE - In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other. | 2012-12-20 |
20120319254 | WIRING BOARD WITH BUILT-IN SEMICONDUCTOR ELEMENT - A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer. | 2012-12-20 |
20120319255 | Thermal Enhanced High Density Flip Chip Package - Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers. | 2012-12-20 |
20120319256 | SEMICONDUCTOR PACKAGE FOR MEMS DEVICE AND METHOD OF MANUFACTURING SAME - In some embodiments, a semiconductor package can include: (a) a base having a cavity; (b) an interposer coupled to the base and at least partially over the cavity such that the interposer and the base form a back chamber, the interposer has a first opening into the back chamber; (c) a micro-electro-mechanical system device located over the interposer at the first opening; and (d) a lid coupled to the base. Other embodiments also are disclosed. | 2012-12-20 |
20120319257 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area. | 2012-12-20 |
20120319258 | STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF - A method of forming a conductive pattern on a metallic frame for manufacturing a stack frame for electrical connections is disclosed. In one embodiment, a recess is formed in the metallic frame and a conductive element is bonded in the recess to make a stack frame for electrical connections. In another embodiment, the process can be performed on both top surface and bottom surface of metallic frame to make another stack frame for electrical connections. In yet another embodiment, a package structure and a manufacturing method of forming a conductive pattern on a lead frame for electrical connections are disclosed. | 2012-12-20 |
20120319259 | POWER MODULE PACKAGE AND METHOD FOR FABRICATING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: first and second lead frames arranged to face each other, both or either of the first and second frames being made of aluminum; anodized layers formed on portions of the lead frame(s) made of aluminum in the first and second lead frames; and semiconductor devices mounted on first surfaces of the first and second lead frames. | 2012-12-20 |
20120319260 | POWER MODULE PACKAGE AND SYSTEM MODULE HAVING THE SAME - Disclosed herein is a power module package, including: a first substrate having first semiconductor chips mounted thereon; and a second substrate having second semiconductor chips mounted thereon, the second substrate being coupled with the first substrate such that a side surface in a thickness direction thereof is disposed on an upper surface of the first substrate. | 2012-12-20 |
20120319261 | HERMETICALLY SEALED WAFER PACKAGES - Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring. | 2012-12-20 |
20120319262 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly. | 2012-12-20 |
20120319263 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive. | 2012-12-20 |
20120319264 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 2012-12-20 |
20120319265 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED LASER VIA INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad. | 2012-12-20 |
20120319266 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached. | 2012-12-20 |
20120319267 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation. | 2012-12-20 |
20120319268 | CONDUCTIVE CONNECTION SHEET, METHOD FOR CONNECTING TERMINALS, METHOD FOR FORMING CONNECTION TERMINAL, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A conductive connecting sheet ( | 2012-12-20 |
20120319269 | Enhanced Bump Pitch Scaling - An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member. | 2012-12-20 |
20120319270 | Wafer Level Chip Scale Package with Reduced Stress on Solder Balls - A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus. | 2012-12-20 |
20120319271 | BUMP STRUCTURE AND PROCESS OF MANUFACTURING THE SAME - A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other. | 2012-12-20 |
20120319272 | Flip Chip Interconnect Solder Mask - A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements. | 2012-12-20 |
20120319273 | Flip Chip Interconnect Solder Mask - A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements. | 2012-12-20 |
20120319274 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A circuit substrate having a mounting surface on which a semiconductor chip is mounted and at least one connection pad formed on the mounting surface is connected to a support plate having at least one mounting portion with a diameter larger than a diameter of the connection pad, through a truncated-cone-shaped solder layer which is formed from at least one solder ball on the basis of a difference between the diameter of the mounting portion and the diameter of the connection pad. The resin layer is formed between the mounting surface of the circuit substrate and the support plate and the support plate is subsequently removed, whereby a truncated-cone-shaped via is formed in the resin layer along the truncated-cone-shaped solder layer. A reflow process is thereafter performed, whereby the truncated-cone-shaped solder layer is formed into a spherical solder layer within the truncated-cone-shaped via. | 2012-12-20 |
20120319275 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 2012-12-20 |
20120319276 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 2012-12-20 |
20120319277 | THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD THEREOF - Disclosed is a thin film transistor panel, comprising a substrate, an insulation layer and transparent conducting material. The insulation layer comprises projections at the back side not facing the substrate. A space between two adjacent projections is 1 μm-10 μm; the transparent conducting material is formed on the top surface and the lateral surface of the projections of the insulation layer. Otherwise, the transparent conducting material is formed on the top surface and the plane surface around the bottom of the projections or formed on the top surface, the lateral surface and the plane surface around the bottom of the projections. The present invention also discloses a manufacturing method of the thin film transistor panel. | 2012-12-20 |
20120319278 | GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer. | 2012-12-20 |
20120319279 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, wiring lines formed above the semiconductor substrate, and an air gap formed between the adjacent wiring lines. In the semiconductor device, top surfaces and side walls of the wiring lines are covered with the diffusion prevention film, and the air gap is in contact with the interconnects via a diffusion prevention film. | 2012-12-20 |
20120319280 | SEMICONDUCTOR DEVICE AND BONDING MATERIAL FOR SEMICONDUCTOR DEVICE - In a semiconductor device | 2012-12-20 |
20120319281 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 2012-12-20 |
20120319282 | Reliable Packaging and Interconnect Structures - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 2012-12-20 |
20120319283 | SEMICONDUCTOR DEVICE HAVING EXTERNAL ELECTRODES EXPOSED FROM ENCAPSULATION MATERIAL - A semiconductor device includes a semiconductor element including an anode electrode and a cathode electrode, an encapsulating material which covers the semiconductor element, a first external electrode which is electrically connected to the cathode electrode and is at least partially exposed outside of the encapsulating material, a second external electrode which is electrically connected to the anode electrode and is at least partially exposed outside of the encapsulating material, and a sacrificial metallic body which is arranged outside of the encapsulating material so as to be in direct contact with the first external electrode or to be electrically connected to the first external electrode through saltwater, and contains metal having larger ionization tendency than any metal contained in the first external electrode. | 2012-12-20 |
20120319284 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE ON PACKAGE SUPPORT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated packaging system includes: providing a substrate; mounting a die over the substrate; mounting an interposer having a slot over the die; covering a first encapsulant over the die and the interposer, a central region of the interposer exposed from the first encapsulant; and forming a hole through the first encapsulant to expose a peripheral portion of the interposer. | 2012-12-20 |
20120319285 | INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer. | 2012-12-20 |
20120319286 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side. | 2012-12-20 |
20120319287 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR LAYOUT - A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively. | 2012-12-20 |
20120319288 | Semiconductor Package - A semiconductor package and a carrier for a semiconductor package are provided, the carrier having a top surface and a bottom surface separated by side walls. The carrier includes a seat for a component, and at least one terminal region for electrically connecting the component to the carrier when mounted to the seat, wherein a test portal is arranged at an outer surface of the carrier, and wherein one or more routing paths are arranged in the carrier for routing one or more electrical contacts arranged at the carrier to the test portal. | 2012-12-20 |
20120319289 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having plural electrode pads, and a wiring substrate having plural electrode pads to mount the semiconductor chip on the wiring substrate, wherein the plural electrode pads of the semiconductor chip include a first electrode pad, and a second electrode pad arranged on an outer periphery side of the first electrode pad, the plural electrode pads of the wiring substrate include a third electrode pad, and a fourth electrode pad arranged on an outer periphery side of the third electrode pad, the first electrode pad and the third electrode pad are connected via a first connecting portion, and the second electrode pad and the fourth electrode pad are connected via a second connecting portion including a pin. | 2012-12-20 |
20120319290 | ELECTRICAL CONNECTION FOR MULTICHIP MODULES - A semiconductor chip is provided. The semiconductor chip includes a semiconductor substrate, a circuit on the substrate, an insulating layer formed on the circuit, and a plurality of electrically floating conductor lines formed on the insulating layer, at a major surface of the semiconductor chip. | 2012-12-20 |
20120319291 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a dielectric layer disposed over a substrate. A metallic line is disposed in the dielectric layer. A through-silicon-via (TSV) structure continuously extends through the dielectric layer and the substrate. A surface of the metallic line is substantially leveled with a surface of the TSV structure. | 2012-12-20 |
20120319292 | STRUCTURE OF A WAFER LEVEL SUBSTRATE FOR CARRYING LIGHT EMITTING DEVICES - Structure and fabricating method of a wafer level substrate for carrying light emitting devices are provided in present invention. The wafer level silicon substrate structure includes a first substrate and a second substrate. A metal line is constructed on a surface of the first substrate according to a predetermined pattern. The predetermined pattern is divided into a plurality of first portions and a plurality of second portions. The second substrate is adhered to the surface of the first substrate. The second substrate has a plurality of through holes. Each of the through holes is respectively corresponding to the first portions. Each of the first portions is adapted to electrically connect with a light emitting device. The provided wafer level substrate structure configured with light emitting devices is capable of providing uniform light output, having better light extraction property, improving process yield, higher production yield and achieving product uniformity. | 2012-12-20 |
20120319293 | MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE - A microelectronic device comprises a first surface ( | 2012-12-20 |
20120319294 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LASER HOLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation. | 2012-12-20 |